spectrum digital website

5
D
4
3
2
REV
POWER DOMAINS
EVM_12V0
EVM_5V0
EVM_3V3
EVM_1V8_A
EVM_1V8_D
EVM_1V5
EVM_1V0_AVS
EVM_1V0_CONN
EVM_0V9
EVM_DDR_VTT
12 VOLT INPUT FROM EXTERNAL POWER SUPPLY
5.0 VOLT OUTPUT FROM TPS65232
3.3 VOLT OUTPUT FROM TPS65232
1.8 VOLT ANALOG LDO OUTPUT FROM TPS65001
1.8 VOLT DIGITAL OUTPUT FROM TPS65001
1.5 VOLT OUTPUT FROM TPS54620
1.0 VOLT CORE FROM TPS40041
1.0 VOLT NON-CORE FROM TPS65232
0.9 VOLT OUTPUT FROM TPS65001
0.75 VOLT TERMINATOR DDR3
B
DATE
APPROVED
A
Initial schematic for layout
02/15/2010
RRP
B
Beta build
10/31/2010
RRP
B
Production build
5/15/2011
RRP
D
SCHEMATIC CONTENTS
01) TITLE PAGE
02) NETRA MCASP'S
03) NETRA SERIAL I/O
04) NETRA ETHERNET INTERFACE
05) NETRA USB INTERFACE
06) NETRA GPMC
07) NETRA DDR0 EMIF
08) NETRA DDR1 EMIF
09) NETRA ANALOG VIDEO
10) NETRA VIDEO PORT
11) NETRA HDMI INTERFACE
12) NETRA SATA/PCIe
13) SERDES CLOCKS
14) NETRA JTAG
15) NETRA CLOCKS
16) NETRA POWER 1
17) NETRA POWER 2
18) NETRA POWER 3
19) NETRA GROUND PINS
20) CAPS
21) DDR3 EMIF0 MEMORIES
22) EMIF0 TESTPOINTS
23) DDR CAPS
24) DDR3 VTT TERMINATION
25) DDR3 EMIF1 MEMORIES
26) EMIF0 TESTPOINTS
27) DDR CAPS
28) PCIe INTERFACE CONNECTOR
29) PCIe 3V3 POWER
30) USB HOST INTERFACE CONNECTORS
C
1
DESCRIPTION
31)
32)
33)
34)
35)
36)
37)
38)
39)
40)
41)
42)
43)
44)
45)
46)
47)
48)
49)
50)
51)
52)
53)
54)
55)
56)
57)
58)
I2C EEPROM
I2C EXPANDER
RS232 INTERFACE
IR RECIEVER
SD/MMC CONNECTOR
SPI EEPROM
NAND FLASH
ETHERNET PHY
ETHERNET POWER
ETHERNET CONNECTOR
AUDIO CODEC TLV320AIC3106
ANALOG VIDEO OUT
SCART ANALOG VIDEO OUT
VIDEO PORT EXPANSION
VIDEO PORT EXPANSION 2
GPMC EXPANSION CONNECTOR
SERIAL I/O EXPANSION CONNECTOR
MCASP EXPANSION CONNECTOR
POWER MONITORS
POWER MONITOR CPU
POWER 5V0,3V3,1V0_CONN
POWER 1V5
POWER VTT
POWER 1V0 CORE
POWER 0V9/1V8_A/1V8_D
POWER IN
POWER SEQUENCING
REVISION HISTORY
I2C0 ADDRESS MAP
C
BASE BINARY
HEX BASE ( RJ )
DEVICE
SHEET
PCF8575
27
I2C EEPROM
31
TLV320AIC3106
36
RJ - Right Justified
I2C1 ADDRESS MAP
B
BASE BINARY
HEX BASE ( RJ )
DEVICE
SHEET
PCF8575
27
RJ - Right Justified
REVISION STATUS OF SHEETS
REV
A
A
A
A
A
A
A
A
SH
51
52
53
54
55
56
57
58
REV
A
A
A
A
A
A
A
A
A
A
SH
41
42
43
44
45
46
47
48
49
50
REV
A
A
A
A
A
A
A
A
A
A
SH
31
32
33
34
35
36
37
38
39
40
DWN
R.R.P.
CHK
A
REV
A
A
A
A
A
A
A
A
A
A
SH
21
22
23
24
25
26
27
28
29
30
REV
A
A
A
A
A
A
A
A
A
A
T.W.K.
ENGR
R.R.P.
ENGR-MGR
R.R.P.
QA
SH
11
12
13
14
15
16
17
18
19
20
REV
C
A
A
A
A
A
A
A
A
A
SH
1
2
3
4
5
6
7
8
9
10
C.M.D.
MFG
NEXT ASSY
USED ON
R.R.P.
RLSE
5
APPLICATION
R.R.P.
4
DATE
02/15/2010
DATE
02/15/2010
DATE
02/15/2010
DATE
02/15/2010
DATE
02/15/2010
DATE
02/15/2010
DATE
02/15/2010
SPECTRUM DIGITAL INCORPORATED
Title:
Page Contents:
TITLE PAGE
Size:B
DWG NO
Date:
3
2
A
NETRA EVM
Revision:
C
512872-0001
Tuesday, June 14, 2011
Sheet
1
1
of
58
5
4
3
2
1
U31-9
D
48 MCARD_CD1
MCARD_CD1
AL28
RSV34
48 MCARD_CD2
MCARD_CD2
AL29
RSV35
48 MCARD_MDET
MCARD_MDET
AM29
RSV33
48 MCARD_RESET
MCARD_RESET
AT28
RSV40
48 MCARD_VCCEN
MCARD_VCCEN
AR29
RSV38
48 MCARD_VPPEN
MCARD_VPPEN
AT29
RSV39
48 MCARD_VS1
MCARD_VS1
AN29
RSV36
48 MCARD_VS2
MCARD_VS2
AP29
RSV37
MCTL_SCLK
AT30
EMAC[1]_TXCLK
MCTL_SCTL
AR30
EMAC[1]_COL
48 MCTL_SDI
MCTL_SDI
AN31
EMAC[1]_CRS
48 MCTL_SDO
MCTL_SDO
AN30
EMAC[1]_RXER
MTSI_BYTSTRT
48 MCTL_SCLK
48 MCTL_SCTL
C
48 MTSI_BYTSTRT
48 MTSI_DCLK
48
48
48
48
48
48
48
48
MTSI_DATA0
MTSI_DATA1
MTSI_DATA2
MTSI_DATA3
MTSI_DATA4
MTSI_DATA5
MTSI_DATA6
MTSI_DATA7
AT33
EMAC[1]_RXDV
MTSI_DCLK
AT37
EMAC[1]_RXCLK
MTSI_DATA0
MTSI_DATA1
MTSI_DATA2
MTSI_DATA3
MTSI_DATA4
MTSI_DATA5
MTSI_DATA6
MTSI_DATA7
AT36
AT35
AU36
AT34
AU35
AR33
AU34
AP32
EMAC[1]_RXD[0]
EMAC[1]_RXD[1]
EMAC[1]_RXD[2]
EMAC[1]_RXD[3]
EMAC[1]_RXD[4]
EMAC[1]_RXD[5]
EMAC[1]_RXD[6]
EMAC[1]_RXD[7]
AH31
AJ27
AK28
AH30
AG29
AJ31
AJ35
MCA[0]_AXR[0]
MCA[0]_AXR[1]
MCA[0]_AXR[2]/MCB_FSX
MCA[0]_AXR[3]/MCB_FSR
MCA[0]_AXR[4]/MCB_DX
MCA[0]_AXR[5]/MCB_DR
AK37
AJ32
AJ33
AJ34
AJ36
AJ37
MCA[1]_AHCLKX
MCA[1]_AHCLKR
MCA[1]_ACLKR
MCA[1]_ACLKX
MCA[1]_AFSR
MCA[1]_AFSX
MCA[1]_AMUTE
AM37
AL37
AK36
AL36
AK35
AK34
AK33
CPU.MCA1_AHCLKX
CPU.MCA1_AHCLKR
CPU.MCA1_ACLKR
CPU.MCA1_ACLKX
MCA[1]_AXR[0]
MCA[1]_AXR[1]
AL33
AK32
MCA1_AXR0
MCA1_AXR1
48 MTSO_DCLK
B
48
48
48
48
48
48
48
48
MTSO_BYTSTRT
AU30
EMAC[1]_TXEN
MTSO_DCLK
AU33
EMAC[1]_GMTCLK
MTSO_DATA0
MTSO_DATA1
MTSO_DATA2
MTSO_DATA3
MTSO_DATA4
MTSO_DATA5
MTSO_DATA6
MTSO_DATA7
MTSO_DATA0
MTSO_DATA1
MTSO_DATA2
MTSO_DATA3
MTSO_DATA4
MTSO_DATA5
MTSO_DATA6
MTSO_DATA7
AP31
AR32
AT32
AU32
AU31
AT31
AP30
AM30
R414
R396
R397
R411
1
1
1
1
2
2
2
2
22
22
22
22
MCA0_AHCLKX
MCA0_AHCLKR
MCA0_ACLKR
MCA0_ACLKX
MCA0_AFSR
MCA0_AFSX
MCA0_AMUTE
MCA0_AHCLKX 48
MCA0_AHCLKR 48
MCA0_ACLKR 48
MCA0_ACLKX 48
MCA0_AFSR 48
MCA0_AFSX 48
MCA0_AMUTE 48
MCA0_AXR0
MCA0_AXR1
MCA0_AXR2
MCA0_AXR3
MCA0_AXR4
MCA0_AXR5
R150
R152
R155
R144
MCA0_AXR0
MCA0_AXR1
MCA0_AXR2
MCA0_AXR3
MCA0_AXR4
MCA0_AXR5
1
1
1
1
2
2
2
2
22
22
22
22
MCA1_AHCLKX
MCA1_AHCLKR
MCA1_ACLKR
MCA1_ACLKX
MCA1_AFSR
MCA1_AFSX
MCA1_AMUTE
D
48
48
48
48
48
48
MCA1_AHCLKX 48
MCA1_AHCLKR 48
MCA1_ACLKR 48
MCA1_ACLKX 48
MCA1_AFSR 48
MCA1_AFSX 48
MCA1_AMUTE 48
MCA1_AXR0 48
MCA1_AXR1 48
C
EVM_3V3
MCA[2]_AHCLKX/MCB_CLKR
MCA[2]_AHCLKR/MCB_CLKS
MCA[2]_ACLKR/MCB_CLKR/MCB_DR
MCA[2]_ACLKX/MCB_CLKX
MCA[2]_AFSR/MCB_CLKX/MCB_FSR
MCA[2]_AFSX/MCB_CLKS/MCB_FSX
MCA[2]_AMUTE
MCA[2]_AXR[0]
MCA[2]_AXR[1]/MCB_DX
48 MTSO_BYTSTRT
CPU.MCA0_AHCLKX
CPU.MCA0_AHCLKR
CPU.MCA0_ACLKR
CPU.MCA0_ACLKX
MCA[0]_AHCLKX
MCA[0]_AHCLKR
MCA[0]_ACLKR
MCA[0]_ACLKX
MCA[0]_AFSR
MCA0_AFSX
MCA[0]_AMUTE
AN36
AM34
AL34
AM36
AM35
AN35
AP36
AR36
AR37
CPU.MCA2_ACLKHX
CPU.MCA2_AHCLKR
CPU.MCA2_ACLKR
CPU.MCA2_ACLKX
EXP_MCA2_AFSR
MCA2_AFSX
EXP_MCA2_AMUTE
R138
R401
R405
R141
1
2 22
1
2 22
1
2 22
1
2 22
EXP_MCA2_AFSR 48
MCA2_ACLKHX
EXP_MCA2_AHCLKR
EXP_MCA2_ACLKR
MCA2_ACLKX
C515
.1uF
c402-25
EXP_MCA2_AHCLKR 48
EXP_MCA2_ACLKR 48
U63
EXP_MCA2_AMUTE 48
MCA2_AFSX
MCA2_ACLKX
MCA2_ACLKHX
MCA2_AXR1
MCA2_AXR0
MCA2_AXR0
MCA2_AXR1
EMAC[1]_TXD[0]
EMAC[1]_TXD[1]
EMAC[1]_TXD[2]
EMAC[1]_TXD[3]
EMAC[1]_TXD[4]
EMAC[1]_TXD[5]
EMAC[1]_TXD[6]
EMAC[1]_TXD[7]
Vcc
24
1B1
1B2
1B3
1B4
1B5
2
5
6
9
10
2A1
2A2
2A3
2A4
2A5
2B1
2B2
2B3
2B4
2B5
15
16
19
20
23
2OE
GND
12
3
4
7
8
11
1A1
1A2
1A3
1A4
1A5
1
1OE
14
17
18
21
22
13
B_AIC_WCLK 41
B_AIC_BCLK 41
B_AIC_MCLK 41
B_AIC_DOUT 41
B_AIC_DIN 41
EXP_MCA2_AXR0
EXP_MCA2_AXR1
EXP_MCA2_ACLKHX
EXP_MCA2_ACLKX
EXP_MCA2_AFSX
EXP_MCA2_AXR0 48
EXP_MCA2_AXR1 48
EXP_MCA2_ACLKHX 48
EXP_MCA2_ACLKX 48
EXP_MCA2_AFSX 48
B
SN74CBTLV3384PW
EVM_3V3
NETRA_3
A
32 AIC_EXPANSION
1
4
2
3
MCLK: MCA2_AHCLKX (drive this clock into McASP)
BCLK: MCA2_ACLKX (McASP will drive this into the AIC)
WCLK: MCA2A_FSX (McASP will drive this into the AIC)
DIN: MCA2_AXR[0]
DOUT: MCA2_AXR1[1]
Drive the MCLK into McASP1 Tx.
McASP generates the Tx bit and frame clocks.
Configure McASP such that the Rx section
operates off of the Tx section clocks.
5
C497
.1uF
U62
SN74LVC1G00DCKRG4
SPECTRUM DIGITAL INCORPORATED
Title:
EVM_3V3
EVM_3V3 3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
Page Contents:
NETRA McASP/MCARD
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
2
of
58
5
4
3
2
1
U31-4
CLKOUT
47 CLKOUT
47 TIM5_OUT
47 TIM6_OUT
47 TIM7_OUT
47 SC0_VCCEN
47
SC0_C4
47 SC0_CLK
47 SC0_DATA
F1
H33
CLKOUT
U4
SD_CLK/GPMC_A[13]/GP1[1]
U2
CPU.MMC_CLK
R168
1
2 22
MMC_CLK
SD_CMD/GPMC_A[21]/GP1[2]
U3
CPU.MMC_CMD R427
1
2 22
MMC_CMD
TIM4_OUT/GP0[28]
TIM5_OUT
H34
TIM6_OUT
H1
TIM6_OUT/GPMC_A[24]/GP0[30]
TIM7_OUT
G1
TIM7_OUT/GPMC_A[12]/GP0[31]
SC0_VCCEN
J4
GPMC_A[23]/GP1[14]
SC0_C4
J5
GP1[13]
SC0_CLK
SC0_DATA
J6
J7
GPMC_A[26]/GP1[11]
GPMC_A[25]/GP1[12]
MMC_POW
SD_POW/GPMC_A[14]/GP1[0]
MMC_POW 35
MMC_CLK 35
MMC_CMD 35
TIM5_OUT/GP0[29]
D
MMC_DAT0
MMC_DAT1
MMC_DAT2
MMC_DAT3
SD_DAT[0]/GPMC_A[20]/GP1[3]
SD_DAT[1]_SDIRQ/GPMC_A[19]/GP1[4]
SD_DAT[2]_SDRW/GPMC_A[18]/GP1[5]
SD_DAT[3]/GPMC_A[17]/GP1[6]
U1
T1
T2
T13
SD_SDWP/GPMC_A[15]/GP1[8]
SD_SDCD/GPMC_A[16]/GP1[7]
R5
R13
MMC_SD_WP
MMC_SD_CD
UART0_TXD
N8
UART0_TXD
UART0_RXD
N10
UART0_RXD
MMC_DAT0
MMC_DAT1
MMC_DAT2
MMC_DAT3
SC0_DET
SC0_DET
K8
GPMC_A[27]/GP1[9
47
SC0_RST
SC0_RST
K2
GPMC_A[22]/GP1[10]
UART0_RIN/GPMC_A[17]/GPMC_A[22]/GP1[19]
N3
UART0_RIN
SC0_VPPEN
J3
GPMC_A[24]/GP1[15]
UART0_RTSn/GP1[27]
N9
UART0_RTSN
UART0_DTRn/GPMC_A[20]/GPMC_A[12]/GP1[16]
N6
UART0_DTRN
UART0_DSRn/GPMC_A[19]/GPMC_A[24]/GP1[17]
N4
UART0_DSRN
UART0_CTSn/GP1[28]
N7
UART0_CTSN
N5
UART0_DCDN
47 SC1_VCCEN
C
47
SC1_C4
47 SC1_CLK
47 SC1_DATA
SC1_VCCEN
H3
GPMC_A[21]/GP0[26]
SC1_C4
H4
GP0[25]
SC1_CLK
SC1_DATA
H5
H6
GPMC_A[14]/GP0[23]
GPMC_A[13]/GP0[24]
J2
GPMC_A[16]/GP0[21]
J1
GPMC_A[15]/GP0[22]
47
SC1_DET
SC1_DET
47
SC1_RST
SC1_RST
SC1_VPPEN
47 SC1_VPPEN
36,46 SPI_MISO
36,46 SPI_MOSI
N11
SPI_D[0]
SPI_MOSI
P13
SPI_D[1]
R171 1
2 22
CPU.SPI_SCLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_CS3
36,46 SPI_CS0
46 SPI_CS1
47 SPI_CS2
46 SPI_CS3
R2
R1
P2
P3
P1
UART1_TXD/GPMC_A[25]/GPMC_A[19]
N2
UART1_TXD
N1
UART1_RXD
UART1_RTSn/GPMC_A[14]/GPMC_A[18]/GP1[25]
M2
UART1_RTSN
UART1_CTSn/GPMC_A[13]/GPMC_A[17]/GP1[26]
L3
UART1_CTSN
SPI_SCS[0]n
SPI_SCS[1]n/GPMC_A[23]
SPI_SCS[2]n/GPMC_A[22]
SPI_SCS[3]n/GPMC_[A21]/GP1[22]
UART0_RXD 46
UART0_RTSN 46
UART0_DTRN 47
UART0_DSRN 47
C
UART0_CTSN 47
UART0_DCDN 47
UART1_TXD 46
UART2_TXD
L2
UART2_TXD
UART2_RXD
M1
UART2_RXD
UART2_RTSn/GPMC_A[15]/GPMC_A[26]/GP1[23]
L9
UART2_RTSN
UART2_CTSn/GPMC_A[16]/GPMC_A[25]/GP1[24]
K7
UART2_CTSN
SPI_SCLK
MMC_SD_WP 35
MMC_SD_CD 35
UART0_RIN 47
UART1_RXD/GPMC_A[26]/GPMC_A[20]
GPMC_A[12]/GP0[27]
SPI_MISO
SPI_SCLK
36,46 SPI_SCLK
H2
UART0_DCDn/GPMC_A[18]/GPMC_A[23]/GP1[18]
35
35
35
35
UART0_TXD 46
47
47 SC0_VPPEN
B
2 22 CPU.CLKOUT
TIM4_OUT
47 TIM4_OUT
D
R185 1
UART1_RXD 34,46
UART1_RTSN 47
UART1_CTSN 47
UART2_TXD 33,47
UART2_RXD 33,46
UART2_RTSN 47
UART2_CTSN 47
B
EVM_3V3
I2C[0]_SCL
I2C[0]_SDA
N32
N33
I2C[1]_SCL
I2C[1]_SDA
N34
N35
R20
2.2K
EVM_3V3
R14
2.2K
R289
2.2K
R279
2.2K
IIC0_SCL 31,32,41,48,50
IIC0_SDA 31,32,41,48,50
NETRA_3
IIC1_SCL 32,48
IIC1_SDA 32,48
SPECTRUM DIGITAL INCORPORATED
A
EVM_3V3
Title:
EVM_3V3 2,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
Page Contents:
NETRA SERIAL I/O
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
3
of
58
5
4
3
2
1
D
D
U31-10
CPU_GMII0_GMTCLK
R165 1
2 22
GMII0_GMTCLK
EMAC[0]_GMTCLK
AC37
EMAC[0]_RXD[0]
EMAC[0]_RXD[1]
EMAC[0]_RXD[2]
EMAC[0]_RXD[3]
EMAC[0]_RXD[4]
EMAC[0]_RXD[5]
EMAC[0]_RXD[6]
EMAC[0]_RXD[7]
AD37
AD36
AC36
AD35
AC35
AD25
AC25
AE36
EMAC[0]_RXCLK
AE37
EMAC[0]_RXDV
EMAC[0]_RXER
EMAC[0]_COL
EMAC[0]_CRS
AE35
AE34
AB25
AA25
EMAC[0]_TXD[0]
EMAC[0]_TXD[1]
EMAC[0]_TXD[2]
EMAC[0]_TXD[3]
EMAC[0]_TXD[4]
EMAC[0]_TXD[5]
EMAC[0]_TXD[6]
EMAC[0]_TXD[7]
AE33
AE32
AE31
AE30
AG28
AF36
AG36
AG35
CPU_GMII0_TXD0
CPU_GMII0_TXD1
CPU_GMII0_TXD2
CPU_GMII0_TXD3
CPU_GMII0_TXD4
CPU_GMII0_TXD5
CPU_GMII0_TXD6
CPU_GMII0_TXD7
EMAC[0]_TXEN
AG37
CPU_GMII0_TXEN
R1591
2 22
GMII0_TXEN
EMAC[0]_TXCLK
AF37
CPU_GMII0_TCLK
R161 1
2 22
GMII0_TCLK
MDIO_MCLK
AH37
MDIO_MDCLK
MDIO_MDIO
AH36
MDIO_MDIO
C
GMII0_GMTCLK 38
GMII0_RXD0
GMII0_RXD1
GMII0_RXD2
GMII0_RXD3
GMII0_RXD4
GMII0_RXD5
GMII0_RXD6
GMII0_RXD7
GMII0_RXD0
GMII0_RXD1
GMII0_RXD2
GMII0_RXD3
GMII0_RXD4
GMII0_RXD5
GMII0_RXD6
GMII0_RXD7
GMII0_RCLK
GMII0_RCLK 38
GMII0_RXDV
GMII0_RXER
GMII0_COL
GMII0_CRS
R417
R419
R420
R421
R423
R160
R158
R416
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
22
22
22
22
22
22
22
22
38
38
38
38
38
38
38
38
GMII0_RXDV 38
GMII0_RXER 38
GMII0_COL 38
GMII0_CRS 38
C
GMII0_TXD0
GMII0_TXD1
GMII0_TXD2
GMII0_TXD3
GMII0_TXD4
GMII0_TXD5
GMII0_TXD6
GMII0_TXD7
GMII0_TXD0
GMII0_TXD1
GMII0_TXD2
GMII0_TXD3
GMII0_TXD4
GMII0_TXD5
GMII0_TXD6
GMII0_TXD7
38
38
38
38
38
38
38
38
GMII0_TXEN 38
GMII0_TCLK 38
MDIO_MDCLK 38,48
MDIO_MDIO 38,48
NETRA_3
B
B
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
NETRA ETHERNET
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
4
of
58
5
4
EVM_3V3
E5
NFM21PC474R1C3D
3
1
2
1
3.3 VOLT
CPU_VDDA33USB
C611
0.1uF
2
3
C610
0.001uF
C609
0.01uF
DIFFERENTIAL PAIR
90 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
C612
1uF
D
D
U31-12
T29
R29
EVM_1V8_D
E6
NFM21PC474R1C3D
1
1.8 VOLT
CPU_VDDA18USB
3
2
C642
1uF
C641
1uF
C640
0.1uF
R25
VDD_USB0_3P3
VDD_USB0_3P3
T30
R30
C
T25
T27
N27
N36
USB0_DRVVBUS
P35
USB0_DP
USB0_DN
P37
P36
USB0_R1
N37
VDD_USB1_VBUS
T36
USB1_DRVVBUS
R35
USBB1_DRV_VBUS
USB1_DP
USB1_DN
R37
R36
USB1_DP
USB1_DM
USB1_R1
T37
USB0_VBUS 30
USBB0_DRV_VBUS
USBB0_DRV_VBUS 30
USB0_DP
USB0_DM
USB0_DP 30
USB0_DM 30
VDD_USB0_1P8
C639
0.001uF
T28
USB0_VBUS
VDD_USB0_VBUS
R172
10K 1%
RSV5
VDD_USB1_3P3
VDD_USB1_3P3
USB1_VBUS
USB1_VBUS 30
USBB1_DRV_VBUS 30
C
USB1_DP 30
USB1_DM 30
VDD_USB1_1P8
R169
10K 1%
RSV6
DIFFERENTIAL PAIR
90 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
VDD_USB_0P9
NETRA_3
B
B
EVM_0V9
0.9 VOLT
C634
0.1uF
EVM_1V8_D
EVM_1V8_D 15,16,49,52,55
A
SPECTRUM DIGITAL INCORPORATED
A
EVM_3V3
NETRA EVM
Title:
EVM_3V3 2,3,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
EVM_0V9
EVM_0V9
49,55
Page Contents:
NETRA USB
Size:B
DWG NO
Date:
5
4
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
5
of
58
5
4
3
2
1
EVM_3V3
SW3
C
B
45 VLYNQ_SCRUN
AK2
RSV43
45 VLYNQ_CLOCK
AJ1
RSV42
RSV51
RSV50
RSV49
RSV48
45
45
45
45
VLYNQ_RXD0
VLYNQ_RXD1
VLYNQ_RXD2
VLYNQ_RXD3
AB13
AJ6
AJ5
AJ4
45
45
45
45
VLYNQ_TXD0
VLYNQ_TXD1
VLYNQ_TXD2
VLYNQ_TXD3
AJ3
AK3
AJ2
AH8
AC5
GPMC_A27 46
V1
GPMC_CLK 46
GPMC_ADV_ALE
AE10
GPMC_ADVN_ALE 37,46
GPMC_BE0_CLE
AE11
GPMC_BE0N_CLE 37,46
GPMC_BE1n
AF1
GPMC_BE1N 46
GPMC_DIR/GP1[20]
AE7
GPMC_DIR 46
GPMC_WEn
AG2
GPMC_WEN 37,46
GPMC_OE_REn
AF2
GPMC_OEN_REN 37,46
GPMC_WPn
AE9
GPMC_WPN 37,46
GPMC_CS[0]n
GPMC_CS[1]n
GPMC_CS[2]n
GPMC_CS[3]n
GPMC_CS[4]n/GP1[21]
GPMC_CS[5]n/GPMC_A[12]
AH7
AH1
AH2
AG9
AG3
AG1
GPMC_CS0
GPMC_CS1
GPMC_CS2
GPMC_CS3
GPMC_CS4
GPMC_CS5
GPMC_A[27]/GP0[20]
GPMC_CLK/GP1[29]
1
2
3
4
5
6
7
8
9
10
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1
2
3
4
5
6
7
8
9
10
R352
R349
R340
R336
R331
R327
R322
R316
R308
R304
D
R305
DIP_SWITCH-10
10K
R353
GPMC_A8 46
GPMC_A9 46
GPMC_A10 46
GPMC_A11 46
R350
AD4
AD2
AD1
AC2
3K
GPMC_A[8]/GP0[16]/CS0BW
GPMC_A[9]/GP0[17]/CS0WAIT
GPMC_A[10]/GP0[18]
GPMC_A[11]/GP0[19]
R341
46
46
46
46
10K
GPMC_A4
GPMC_A5
GPMC_A6
GPMC_A7
R337
AE1
AE2
AD8
AD3
10K
GPMC_A[4]/GP0[12]/BTMODE[3]
GPMC_A[5]/GP0[13]/BTMODE[4]
GPMC_A[6]/GP0[14]/CS0MUX[0]
GPMC_A[7]/GP0[15]/CS0MUX[1]
R332
46
46
46
46
3K
GPMC_D[8]
GPMC_D[9]
GPMC_D[10]
GPMC_D[11]
GPMC_D[12]
GPMC_D[13]
GPMC_D[14]
GPMC_D[15]
GPMC_A0
GPMC_A1
GPMC_A2
GPMC_A3
R328
W4
Y1
W3
W1
W2
V10
V3
V2
AE6
AE5
AE4
AE3
10K
37,46 GPMC_D8
37,46 GPMC_D9
37,46 GPMC_D10
37,46 GPMC_D11
37,46 GPMC_D12
37,46 GPMC_D13
37,46 GPMC_D14
37,46 GPMC_D15
GPMC_A[0]/GP0[8]
GPMC_A[1]/GP0[9]/BTMODE[0]
GPMC_A[2]/GP0[10]/BTMODE[1]
GPMC_A[3]/GP0[11]/BTMODE[2]
R323
GPMC_D[0]
GPMC_D[1]
GPMC_D[2]
GPMC_D[3]
GPMC_D[4]
GPMC_D[5]
GPMC_D[6]
GPMC_D[7]
3K
AC1
AA4
AB2
AA3
Y3
AA2
Y10
Y2
R317
GPMC_D0
GPMC_D1
GPMC_D2
GPMC_D3
GPMC_D4
GPMC_D5
GPMC_D6
GPMC_D7
37,46
37,46
37,46
37,46
37,46
37,46
37,46
37,46
10K
GPMC_WAIT
R309
U31-5
AE8
37,46 GPMC_WAIT
20
19
18
17
16
15
14
13
12
11
3K
D
BTMODE0
BTMODE1
BTMODE2
BTMODE3
BTMODE4
CS0MUX0
CS0MUX1
CS0BW
CS0WAIT
10K
BTMODE0
BTMODE1
BTMODE2
BTMODE3
BTMODE4
CS0MUX0
CS0MUX1
CS0BW
CS0WAIT
C
37,46
46
46
46
46
46
EVM_3V3
B
Place Switch by NAND and SPI ROM
R83
10K
R82
10K
SW4
1
2
RSV47
RSV46
RSV45
RSV44
4
3
NAND_BOOTn
SPI_BOOTn
NAND_BOOTn 37
SPI_BOOTn 36
SW DIP-2
ENABLE ON BOARD MEMORIES
NETRA_3
SPECTRUM DIGITAL INCORPORATED
A
A
EVM_3V3
NETRA EVM
Title:
EVM_3V3 2,3,5,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
Page Contents:
NETRA GPMC/VLYNQ INTERFACE
Size:B
DWG NO
Date:
5
4
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
6
of
58
5
4
3
2
1
U31-3
21
21
21
21
21
21
21
21
D
DDR0_D0
DDR0_D1
DDR0_D2
DDR0_D3
DDR0_D4
DDR0_D5
DDR0_D6
DDR0_D7
21 DDR0_DQM0
21 DDR0_DQS0
21 DDR0_DQSN0
21 DDR0_D8
21 DDR0_D9
21 DDR0_D10
21 DDR0_D11
21 DDR0_D12
21 DDR0_D13
21 DDR0_D14
21 DDR0_D15
21 DDR0_DQM1
C
21 DDR0_DQS1
21 DDR0_DQSN1
21
21
21
21
21
21
21
21
DDR0_D16
DDR0_D17
DDR0_D18
DDR0_D19
DDR0_D20
DDR0_D21
DDR0_D22
DDR0_D23
21 DDR0_DQM2
21 DDR0_DQS2
21 DDR0_DQSN2
B
21
21
21
21
21
21
21
21
DDR0_D24
DDR0_D25
DDR0_D26
DDR0_D27
DDR0_D28
DDR0_D29
DDR0_D30
DDR0_D31
21 DDR0_DQM3
21 DDR0_DQS3
21 DDR0_DQSN3
DDR0_D0
DDR0_D1
DDR0_D2
DDR0_D3
DDR0_D4
DDR0_D5
DDR0_D6
DDR0_D7
B1
F2
E2
G4
D2
B2
F3
C1
DDR[0]_D[0]
DDR[0]_D[1]
DDR[0]_D[2]
DDR[0]_D[3]
DDR[0]_D[4]
DDR[0]_D[5]
DDR[0]_D[6]
DDR[0]_D[7]
DDR0_DQM0
C2
DDR[0]_DQM[0]
DDR0_DQS0
DDR0_DQSN0
F4
E3
DDR[0]_DQS[0]
DDR[0]_DQS[0]n
DDR0_D8
DDR0_D9
DDR0_D10
DDR0_D11
DDR0_D12
DDR0_D13
DDR0_D14
DDR0_D15
C5
D7
C6
D6
A5
B6
A3
B3
DDR[0]_D[8]
DDR[0]_D[9]
DDR[0]_D[10]
DDR[0]_D[11]
DDR[0]_D[12]
DDR[0]_D[13]
DDR[0]_D[14]
DDR[0]_D[15]
DDR0_DQM1
B5
DDR[0]_DQM[1]
DDR0_DQS1
DDR0_DQSN1
B4
A4
DDR[0]_DQS[1]
DDR[0]_DQS[1]n
DDR0_D16
DDR0_D17
DDR0_D18
DDR0_D19
DDR0_D20
DDR0_D21
DDR0_D22
DDR0_D23
C8
A7
H10
B7
F8
D8
F9
E7
DDR0_DQM2
G9
DDR0_DQS2
DDR0_DQSN2
B8
A8
DDR0_D24
DDR0_D25
DDR0_D26
DDR0_D27
DDR0_D28
DDR0_D29
DDR0_D30
DDR0_D31
E9
B11
B10
E8
G10
C11
J11
C9
DDR0_DQM3
D9
DDR0_DQS3
DDR0_DQSN3
B9
A9
DDR[0]_D[16]
DDR[0]_D[17]
DDR[0]_D[18]
DDR[0]_D[19]
DDR[0]_D[20]
DDR[0]_D[21]
DDR[0]_D[22]
DDR[0]_D[23
DDR[0]_BA[0]
DDR[0]_BA[1]
DDR[0]_BA[2]
F13
B14
N15
DDR0_BA0
DDR0_BA1
DDR0_BA2
DDR0_BA0 21,22,24
DDR0_BA1 21,22,24
DDR0_BA2 21,22,24
DDR[0]_A[0]
DDR[0]_A[1]
DDR[0]_A[2]
DDR[0]_A[3]
A13
N17
D15
G13
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
21,22,24
21,22,24
21,22,24
21,22,24
DDR[0]_A[4
DDR[0]_A[5]
DDR[0]_A[6]
DDR[0]_A[7]
H13
J13
L13
A14
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
21,22,24
21,22,24
21,22,24
21,22,24
DDR0]_A[8]
DDR[0]_A[9]
DDR[0]_A[10]
DDR[0]_A[11]
N14
K13
C14
B13
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
21,22,24
21,22,24
21,22,24
21,22,24
DDR[0]_A[12]
DDR[0]_A[13]
DDR[0]_A[14]
N16
B16
D17
DDR0_A12
DDR0_A13
DDR0_A14
DDR0_A12 21,22,24
DDR0_A13 21,22,24
DDR0_A14 21,22,24
DDR[0]_CS[0]n
B17
DDR0_CSN0
DDR0_CSN0 21,22,24
DDR[0]_CS[1]n
F18
DDR[0]_D[24]
DDR[0]_D[25]
DDR[0]_D[26]
DDR[0]_D[27]
DDR[0]_D[28]
DDR[0]_D[29]
DDR[0]_D[30]
DDR[0]_D[31]
C
DDR[0]_CKE
C18
DDR0_CKE
DDR0_CKE 21,22,24
DDR[0]_CASn
C13
DDR0_CASN
DDR0_CASN 21,22,24
DDR[0]_RASn
D13
DDR0_RASN
DDR0_RASN 21,22,24
DDR[0_ODT[1]
A16
DDR[0]_ODT[0]
E18
DDR0_ODT0
DDR0_ODT0 21,22,24
DDR[0]_WEn
E13
DDR0_W EN
DDR0_W EN 21,22,24
DDR[0]_CLK[0]
DDR[0]_CLK[0]n
B12
A12
DDR0_CLK0
DDR0_CLK0N
DDR0_CLK0 21,22,24
DDR0_CLK0N 21,22,24
DDR[0]_CLK[1]
DDR[0]_CLK[1]n
A15
B15
DDR[0]_DQM[2]
DDR[0]_DQS[2]
DDR[0]_DQS[2]n
D
DDR[0]_VTP
DDR[0]_RSTn
A6
R199
B
49.9
DDR0_RST
D18
DDR0_RST 21
DDR[0]_DQM[3]
DDR[0]_DQS[3]
DDR[0]_DQS[3]n
EVM_1V5
VREFSSTL_DDR[0]
A17
EVM_DDR_REF_OUT
NETRA_3
C705
NO-POP
EVM_DDR_REF_OUT
DIFFERENTIAL PAIRS
EVM_DDR_REF_OUT
C708
NO-POP
EVM_DDR_REF_OUT 8,21,23,25,27,53
A
SPECTRUM DIGITAL INCORPORATED
EVM_1V5
Title:
EVM_1V5
Page Contents:
NETRA DDR0 INTERFACE
Size:B
DWG NO
8,16,17,21,23,24,25,27,49,52,53,55,56
Date:
5
A
NETRA EVM
4
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
7
of
58
5
4
3
2
1
U31-14
D
25
25
25
25
25
25
25
25
DDR1_D0
DDR1_D1
DDR1_D2
DDR1_D3
DDR1_D4
DDR1_D5
DDR1_D6
DDR1_D7
25 DDR1_DQM0
25 DDR1_DQS0
25 DDR1_DQSN0
25 DDR1_D8
25 DDR1_D9
25 DDR1_D10
25 DDR1_D11
25 DDR1_D12
25 DDR1_D13
25 DDR1_D14
25 DDR1_D15
25 DDR1_DQM1
C
25 DDR1_DQS1
25 DDR1_DQSN1
25
25
25
25
25
25
25
25
DDR1_D16
DDR1_D17
DDR1_D18
DDR1_D19
DDR1_D20
DDR1_D21
DDR1_D22
DDR1_D23
25 DDR1_DQM2
25 DDR1_DQS2
25 DDR1_DQSN2
B
25
25
25
25
25
25
25
25
DDR1_D24
DDR1_D25
DDR1_D26
DDR1_D27
DDR1_D28
DDR1_D29
DDR1_D30
DDR1_D31
25 DDR1_DQM3
25 DDR1_DQS3
25 DDR1_DQSN3
DDR1_D0
DDR1_D1
DDR1_D2
DDR1_D3
DDR1_D4
DDR1_D5
DDR1_D6
DDR1_D7
B37
F36
E36
G34
D36
B36
F35
C37
DDR[1]_D[0]
DDR[1]_D[1]
DDR[1]_D[2]
DDR[1]_D[3]
DDR[1]_D[4]
DDR[1]_D[5]
DDR[1]_D[6]
DDR[1]_D[7]
DDR[1]_BA[0]
DDR[1]_BA[1]
DDR[1]_BA[2]
F25
B24
N23
DDR1_BA0
DDR1_BA1
DDR1_BA2
DDR1_BA0 24,25,26
DDR1_BA1 24,25,26
DDR1_BA2 24,25,26
DDR[1]_A[0]
DDR[1]_A[1]
DDR[1]_A[2]
DDR[1]_A[3]
A25
N21
D23
G25
DDR1_A0
DDR1_A1
DDR1_A2
DDR1_A3
DDR1_A0
DDR1_A1
DDR1_A2
DDR1_A3
24,25,26
24,25,26
24,25,26
24,25,26
DDR[1]_A[4]
DDR[1]_A[5]
DDR[1]_A[6]
DDR[1]_A[7]
H25
J25
L25
A24
DDR1_A4
DDR1_A5
DDR1_A6
DDR1_A7
DDR1_A4
DDR1_A5
DDR1_A6
DDR1_A7
24,25,26
24,25,26
24,25,26
24,25,26
DDR[1]_A[8]
DDR[1]_A[9]
DDR[1]_A[10]
DDR[1]_A[11]
N24
K25
C24
B25
DDR1_A8
DDR1_A9
DDR1_A10
DDR1_A11
DDR1_A8
DDR1_A9
DDR1_A10
DDR1_A11
24,25,26
24,25,26
24,25,26
24,25,26
DDR[1]_A[12]
DDR[1]_A[13]
DDR[1]_A[14]
N22
B22
D21
DDR1_A12
DDR1_A13
DDR1_A14
DDR1_A12 24,25,26
DDR1_A13 24,25,26
DDR1_A14 24,25,26
DDR[1]_CS[0]n
B21
DDR1_CSN0
DDR1_CSN0 24,25,26
DDR[1]_CS[1]n
F20
D
DDR1_DQM0
C36
DDR[1]_DQM[0]
DDR1_DQS0
DDR1_DQSN0
F34
E35
DDR[1]_DQS[0]
DDR[1]_DQS[0]n
DDR1_D8
DDR1_D9
DDR1_D10
DDR1_D11
DDR1_D12
DDR1_D13
DDR1_D14
DDR1_D15
C33
D31
C32
D32
A33
B32
A35
B35
DDR[1]_D[8]
DDR[1]_D[9]
DDR[1]_D[10]
DDR[1]_D[11]
DDR[1]_D[12]
DDR[1]_D[13]
DDR[1]_D[14]
DDR[1]_D[15]
DDR1_DQM1
B33
DDR[1]_DQM[1]
DDR1_DQS1
DDR1_DQSN1
B34
A34
DDR[1]_DQS[1]
DDR[1]_DQS[1]n
DDR1_D16
DDR1_D17
DDR1_D18
DDR1_D19
DDR1_D20
DDR1_D21
DDR1_D22
DDR1_D23
C30
A31
H28
B31
F30
D30
F29
E31
DDR[1]_D[16]
DDR[1]_D[17]
DDR[1]_D[18]
DDR[1]_D[19]
DDR[1]_D[20]
DDR[1]_D[21]
DDR[1]_D[22]
DDR[1]_D[23]
DDR1_DQM2
G29
DDR[1]_DQM[2]
C
DDR1_DQS2
DDR1_DQSN2
B30
A30
DDR[1]_DQS[2]
DDR[1]_DQS[2]n
DDR1_D24
DDR1_D25
DDR1_D26
DDR1_D27
DDR1_D28
DDR1_D29
DDR1_D30
DDR1_D31
E29
B27
B28
E30
G28
C27
J27
C29
DDR[1]_D[24]
DDR[1]_D[25]
DDR[1]_D[26]
DDR[1]_D[27]
DDR[1]_D[28]
DDR[1]_D[29]
DDR[1]_D[30]
DDR[1]_D[31]
DDR1_DQM3
D29
DDR[1]_DQM[3]
DDR1_DQS3
DDR1_DQSN3
B29
A29
DDR[1]_DQS[3]
DDR[1]_DQS[3]n
DDR[1]_CKE
C20
DDR1_CKE
DDR1_CKE 24,25,26
DDR[1]_CASn
C25
DDR1_CASN
DDR1_CASN 24,25,26
DDR[1]_RASn
D25
DDR1_RASN
DDR1_RASN 24,25,26
DDR[1]_ODT[1]
A22
DDR[1]_ODT[0]
E20
DDR1_ODT0
DDR1_ODT0 24,25,26
DDR[1]_WEn
E25
DDR1_W EN
DDR1_W EN 24,25,26
DDR[1]_CLK[0]
DDR[1]_CLK[0]n
B26
A26
DDR[1]_CLK[1]
DDR[1]_CLK[1]n
A23
B23
DDR[1]_VTP
A32
DDR[1]_RSTn
D20
VREFSSTL_DDR[1]
A21
DDR1_CLK0
DDR1_CLK0N
DDR1_CLK0 24,25,26
DDR1_CLK0N 24,25,26
B
R198
49.9
DDR1_RST
DDR1_RST 25
EVM_1V5
EVM_DDR_REF_OUT
NETRA_3
C706
NO-POP
EVM_DDR_REF_OUT
EVM_DDR_REF_OUT
DIFFERENTIAL PAIRS
EVM_DDR_REF_OUT 7,21,23,25,27,53
A
C709
NO-POP
EVM_1V5
SPECTRUM DIGITAL INCORPORATED
Title:
EVM_1V5
7,16,17,21,23,24,25,27,49,52,53,55,56
Page Contents:
NETRA DDR1 INTERFACE
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
8
of
58
5
4
3
CPU_VDDA_1P0V
AE21
RSV52
AM22
RSV59
AG22
AG23
RSV53
RSV54
C582
0.1uF
EVM_1V8_A
E1
NFM21PC474R1C3D
3
1
2
D
C62
CPU_VDDA_1P8V
C64
0.1uF
0.1uF
AL22
AK22
CPU_VDDA_1P0V
AG20
IOUTA
AT21
IOUTA
42
IOUTB
AR21
IOUOTB
42
IOUTC
AP21
IOUTC
42
IOUTD
AR20
IOUTD
42
IOUTE
AT19
IOUTE
42
IOUTF
AT20
IOUTF
42
VDDA_SD_1P0
C61
2
1
D
RSV58
RSV57
EVM_1V0_CON
E2
NFM21PC474R1C3D
3
1
2
0.1uF
CPU_VDDA_1P8V
C575
C574
C573
0.1uF
C
0.1uF
0.1uF
R394
AN20
VSSA_SD
IOUTG
AU20
IOUTG
43
AH20
AJ21
AH21
VDDA_SD_1P8
VDDA_SD_1P8
VDDA_SD_1P8
RSV41
AU21
RFOUT
42
1.21K AP19
AU19
AL20
AM20
VSSA_SD
VSSA_SD
VSSA_SD
AJ23
AH23
RSV56
RSV55
C
EVM_1V0_CON
VDAC_RBIAS_SD
EVM_1V0_CON 11,15,16,17,20,49,51,55
EVM_1V8_A
EVM_1V8_A 49,55
C86
0.1uF
CPU_VDDA_1P8V
C70
CPU_VDDA_1P8V 16
0.1uF
CPU_VDDA_1P8V
B
CPU_VDDA_1P8V
AM21
AN21
RSV60
RSV61
AT22
VDDA_REF_1P8
AH19
VDAC_VREF
AU22
VSSA_REF_1P8
AG21
VDDA_HD_1P0
AL21
VSSA_HD
AJ22
AH22
VDDA_HD_1P8
VDDA_HD_1P8
B
C65
VDAC_VREF
0.1uF
C563
0.1uF
CPU_VDDA_1P0V
C587
EVM_1V8_A
0.1uF
R489
1K
CPU_VDDA_1P8V
C537
3
C800
1uF
0.1uF
R361
1.21K AE22
1
2
4
5
A
0.1uF
CPU_VDDA_1P8V
C548
VREF_1.24V
U67
TLV431ADBV
C798
0.1uF
R490
C799
0.1uF
15.0K
AK21
AK20
R491
10.0K
VDAC_RBIAS_HD
SPECTRUM DIGITAL INCORPORATED
VSSA_HD
VSSA_HD
Title:
U31-7
Page Contents:
ANALOG VIDEO OUTPUT
Size:B
DWG NO
NETRA_3
Date:
5
4
A
NETRA EVM
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
9
of
58
5
4
3
2
1
U31-6
45 TSO0_BYTSTRT
45 TSO0_DATA
45 TSO0_PACERR
45 TSO0_PACVAL
45 TSO0_DCLK
D
44 TSO1_BYTSTRT
44 TSO1_DATA
45 TSO1_PACERR
44 TSO1_PACVAL
44 TSO1_DCLK
TSO0_BYTSTRT
TSO0_DATA
TSO0_PACERR
TSO0_PACVAL
R153
R151
R156
R157
TSO0_DCLK
R143 1
TSO1_BYTSTRT
TSO1_DATA
TSO1_PACERR
TSO1_PACVAL
R363
R112
R415
R113
TSO1_DCLK
R114 1
1
1
1
1
22
22
22
22
AL2
AM2
AL1
AK1
RSV30
RSV29
RSV32
RSV31
RSV25
RSV24
RSV27
RSV26
AN2
AU3
AR1
AT1
R149
R124
R137
R136
2 22
AP1
RSV28
RSV23
AP2
R142 1
VOUT[1]_C[5]/VIN[1]A_D[11]
VOUT[1]_C[4]/VIN[1]A_D[10]
VOUT[1]_C[7]/VIN[1]A_D[13]
VOUT[1]_C[6]/VIN[1]A_D[12]
AP8
AN7
AD13
AN8
R365
R379
R424
R368
VOUT[1]_C[3]/VIN[1]A_D[9]
AM8
R364 1
2 22
TSI1_DCLK
VIN[0]A_D[21]/VIN[0]B_FLD
VIN[0]A_D[20]/VIN[0]B_DE
VIN[0]A_D[23]/VIN[0]B_HSYNC
VIN[0]A_D[22]/VIN[0]B_VSYNC
AU4
AN3
AT2
AR2
R117
R404
R132
R140
2
2
2
2
22
22
22
22
TSI2_BYTSTRT
TSI2_DATA
TSI2_PACERR
TSI2_PACVAL
VIN[1]A_D[14]
AM3
R399 1
2 22
TSI2_DCLK
VOUT[1]_Y_YC[8]/VIN[1]A_D[6]
VOUT[1]_Y_YC[7]/VIN[1]A_D[5]
VOUT[1]_C[2]/VIN[1]A_D[8]
VOUT[1]_Y_YC[9]/VIN[1]A_D[7]
AT6
AR6
AK6
AP6
R116
R400
R413
R378
2
2
2
2
22
22
22
22
TSI3_BYTSTRT
TSI3_DATA
TSI3_PACERR
TSI3_PACVAL
VOUT[1]_Y_YC[6]/VIN[1]A_D[4]
AC13
R425 1
VIN[0]A_D[17]/VIN[1]A_VSYNC/VOUT[1]_VSYNC
VIN[0]A_D[16]/VIN[1]A_HSYNC/VOUT[1]_FLD
VIN[0]A_D[19]/VIN[1]A_DE/VOUT[1]_C[9]
VIN[0]A_D[18]/VIN[1]A_FLD/VOUT[1]_C[8]
AL5
AT5
AK4
AK5
R410
R118
R408
R418
VOUT[1]_HSYNC/VIN[1]A_D[15]
AR5
VOUT[0]_B_CB_C[1]/VOUT[1]_HSYNC/VOUT[1]_AVID
VOUT[0]_B_CB_C[0]/VOUT[1]_C[9]/VIN[1]B_HSYNC_DE
VOUT[0]_G_Y_YC[1]/VOUT[1]_FLD/VIN[1]B_FLD
VOUT[0]_G_Y_YC[0]/VOUT[1]_VSYNC/VIN[1]B_VSYNC
2
2
2
2
1
1
1
1
22
22
22
22
AP7
AU7
AJ7
AU6
VOUT[1]_Y_YC[3]/VIN[1]A_D[1]
VOUT[1]_Y_YC[2]/VIN[1]A_D[0]
VOUT[1]_Y_YC[5]/VIN[1]A_D[3]
VOUT[1]_Y_YC[4]/VIN[1]A_D[2]
2 22
AT7
VOUT[1]_CLK/VIN[1]A_CLK
2
2
2
2
44 VIN0_CLK0
VIN0_CLK0
R371 1
2 22
CPU_VIN0_CLK0
AR14
VIN[0]A_CLK
44 VIN0_CLK1
VIN0_CLK1
R120 1
2 22
CPU_VIN0_CLK1
AR19
VIN[0]B_CLK
44
44
44
44
44
44
44
44
VIN0_D0
VIN0_D1
VIN0_D2
VIN0_D3
VIN0_D4
VIN0_D5
VIN0_D6
VIN0_D7
VIN0_D0
VIN0_D1
VIN0_D2
VIN0_D3
VIN0_D4
VIN0_D5
VIN0_D6
VIN0_D7
AJ19
AU18
AH18
AR18
AT18
AT17
AP18
AR17
VIN[0]A_D[0]
VIN[0]A_D[1]
VIN[0]A_D[2]
VIN[0]A_D[3]
VIN[0]A_D[4]
VIN[0]A_D[5]
VIN[0]A_D[6]
VIN[0]A_D[7]
44
44
44
44
44
44
44
44
VIN0_D8
VIN0_D9
VIN0_D10
VIN0_D11
VIN0_D12
VIN0_D13
VIN0_D14
VIN0_D15
VIN0_D8
VIN0_D9
VIN0_D10
VIN0_D11
VIN0_D12
VIN0_D13
VIN0_D14
VIN0_D15
AP17
AE16
AT16
AU17
AU16
AT15
AU15
AU14
VIN[0]A_D[8]
VIN[0]A_D[9]
VIN[0]A_D[10]
VIN[0]A_D[11]
VIN[0]A_D[12]
VIN[0]A_D[13]
VIN[0]A_D[14]
VIN[0]A_D[15]
AT14
VOUT[0]_CLK
AP13
AL13
AN13
AK13
AJ13
AM13
AH13
AT12
VOUT[0]_B_CB_C[2]
VOUT[0]_B_CB_C[3]
VOUT[0]_B_CB_C[4]
VOUT[0]_B_CB_C[5]
VOUT[0]_B_CB_C[6]
VOUT[0]_B_CB_C[7]
VOUT[0]_B_CB_C[8]
VOUT[0]_B_CB_C[9]
VOUT0_CLK
44
44
44
44
44
44
44
44
B
VOUT_C2
VOUT_C3
VOUT_C4
VOUT_C5
VOUT_C6
VOUT_C7
VOUT_C8
VOUT_C9
VOUT_C2
VOUT_C3
VOUT_C4
VOUT_C5
VOUT_C6
VOUT_C7
VOUT_C8
VOUT_C9
R96
1
2 22
R370
R373
R386
R389
R374
R388
R375
R108
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
CPU_VOUT_CLK
CPU_VOUT_C2
CPU_VOUT_C3
CPU_VOUT_C4
CPU_VOUT_C5
CPU_VOUT_C6
CPU_VOUT_C7
CPU_VOUT_C8
CPU_VOUT_C9
22
22
22
22
22
22
22
22
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
22
22
22
22
TSI0_BYTSTRT
TSI0_DATA
TSI0_PACERR
TSI0_PACVAL
2 22
2
2
2
2
TSI0_DCLK
TSI3_DCLK
22
22
22
22
TSI4_BYTSTRT
TSI4_DATA
TSI4_PACERR
TSI4_PACVAL
R362 1
2 22
TSI4_DCLK
AT9
AR9
AU8
AP9
R100
R369
R111
R384
2
2
2
2
22
22
22
22
TSI5_BYTSTRT
TSI5_DATA
TSI5_PACERR
TSI5_PACVAL
VOUT[0]_R_CR[0]/VOUT[1]_C[8]/VOUT[1]_CLK
AJ11
R367 1
2 22
TSI5_DCLK
VIN[0]A_VSYNC
VIN[0]A_HSYNC
VIN[0]A_DE
VIN[0]A_FLD
AM4
AU5
AT3
AL4
R403
R115
R131
R407
2
2
2
2
22
22
22
22
TSI6_BYTSTRT
TSI6_DATA
TSI6_PACERR
TSI6_PACVAL
VOUT[1]_AVID/VIN[1]B_CLK
AT4
R125 1
2 22
TSI6_DCLK
VOUT[0]_FLD
VOUT[0]_VSYNC
VOUT[0]_R_CR[1]
VOUT[0]_AVID
AL9
AN9
AT8
AR8
R381
R383
R101
R102
2
2
2
2
VOUT[0]_HSYNC
AM9
R380 1
44
44
44
44
44
44
44
44
VOUT_YC2
VOUT_YC3
VOUT_YC4
VOUT_YC5
VOUT_YC6
VOUT_YC7
VOUT_YC8
VOUT_YC9
VOUT_YC2
VOUT_YC3
VOUT_YC4
VOUT_YC5
VOUT_YC6
VOUT_YC7
VOUT_YC8
VOUT_YC9
R393
R372
R391
R390
R376
R97
R107
R387
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
22
22
22
22
22
22
22
22
CPU_VOUT_YC2
CPU_VOUT_YC3
CPU_VOUT_YC4
CPU_VOUT_YC5
CPU_VOUT_YC6
CPU_VOUT_YC7
CPU_VOUT_YC8
CPU_VOUT_YC9
AE15
AP14
AL14
AM14
AE14
AT13
AU13
AR13
VOUT[0]_G_Y_YC[2]
VOUT[0]_G_Y_YC[3]
VOUT[0]_G_Y_YC[4]
VOUT[0]_G_Y_YC[5]
VOUT[0]_G_Y_YC[6]
VOUT[0]_G_Y_YC[7]
VOUT[0]_G_Y_YC[8]
VOUT[0]_G_Y_YC[9]
44
44
44
44
44
44
44
44
VOUT_CR2
VOUT_CR3
VOUT_CR4
VOUT_CR5
VOUT_CR6
VOUT_CR7
VOUT_CR8
VOUT_CR9
VOUT_CR2
VOUT_CR3
VOUT_CR4
VOUT_CR5
VOUT_CR6
VOUT_CR7
VOUT_CR8
VOUT_CR9
R98
R385
R392
R99
R109
R382
R366
R110
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
22
22
22
22
22
22
22
22
CPU_VOUT_CR2
CPU_VOUT_CR3
CPU_VOUT_CR4
CPU_VOUT_CR5
CPU_VOUT_CR6
CPU_VOUT_CR7
CPU_VOUT_CR8
CPU_VOUT_CR9
AT11
AR11
AG13
AT10
AU10
AL10
AK10
AU9
VOUT[0]_R_CR[2]/VOUT[0]_HSYNC/VOUT[1]_Y_YC[2]
VOUT[0]_R_CR[3]/VOUT[0]_VSYNC/VOUT[1]_Y_YC[3]
VOUT[0]_R_CR[4]/VOUT[0]_FLD/VOUT[1]_Y_YC[4]
VOUT[0]_R_CR[5]/VOUT[0]_AVID/VOUT[1]_Y_YC[5]
VOUT[0]_R_CR[6]/VOUT[0]_G_Y_YC[0]/VOUT[1]_Y_YC[6]
VOUT[0]_R_CR[7]/VOUT[0]_G_Y_YC[1]/VOUT[1]_Y_YC[7]
VOUT[0]_R_CR[8]/VOUT[0]_B_CB_C[0]/VOUT[1]_Y_YC[8]
VOUT[0]_R_CR[9]/VOUT[0]_B_CB_C[1]/VOUT[1]_Y_YC[9]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
22
22
22
22
2 22
TSI2_DCLK 45
TSI3_BYTSTRT 44
TSI3_DATA 45
TSI3_PACERR 45
TSI3_PACVAL 45
TSI3_DCLK 45
C
TSI4_BYTSTRT 45
TSI4_DATA 44
TSI4_PACERR 45
TSI4_PACVAL 45
TSI4_DCLK 45
TSI5_BYTSTRT 44
TSI5_DATA 44
TSI5_PACERR 44
TSI5_PACVAL 44
TSI5_DCLK 44
TSI6_BYTSTRT 45
TSI6_DATA 44
TSI6_PACERR 45
TSI6_PACVAL 45
B
TSI6_DCLK 44
TSI7_BYTSTRT 44
TSI7_DATA 44
TSI7_PACERR 44
TSI7_PACVAL 44
TSI7_DCLK 44
SPECTRUM DIGITAL INCORPORATED
3
2
A
NETRA EVM
Page Contents:
DIGITAL VIDEO PORTS AND TRANSPORT STREAMS
Size:B
DWG NO
Date:
4
TSI1_BYTSTRT 44
TSI1_DATA 44
TSI1_PACERR 45
TSI1_PACVAL 44
TSI2_BYTSTRT 44
TSI2_DATA 45
TSI2_PACERR 45
TSI2_PACVAL 45
TSI7_DCLK
Title:
5
D
TSI1_DCLK 44
TSI7_BYTSTRT
TSI7_DATA
TSI7_PACERR
TSI7_PACVAL
NETRA_3
A
TSI0_BYTSTRT 45
TSI0_DATA 44
TSI0_PACERR 45
TSI0_PACVAL 45
TSI0_DCLK 45
TSI1_BYTSTRT
TSI1_DATA
TSI1_PACERR
TSI1_PACVAL
22
22
22
22
2 22
C
44 VOUT0_CLK
1
1
1
1
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
10 o f
58
5
4
3
2
1
EVM_3V3
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
Place Filters as close to U31
as possible
R260
10K
EVM_5V0
D
C446
0.1uF
C453
0.1uF
D
C447
0.1uF
C454
0.1uF
U31-8
AN19
AN18
HDMI_TMDSDP2
HDMI_TMDSDN2
AT27
AU27
HDMI_TMDSDP2
HDMI_TMDSDN2
HDMI_TMDSDP1
HDMI_TMDSDN1
AT26
AU26
HDMI_TMDSDP1
HDMI_TMDSDN1
HDMI_TMDSDP0
HDMI_TMDSDN0
AT25
AU25
HDMI_TMDSDP0
HDMI_TMDSDN0
RSV22
RSV21
HDMI_CEC
HDMI_TMDSCLKP
AT24
AU24 HDMI_TMDSCLKN
R483
L25
1
AP25
HDMI_SCL
HDMI_SDA
AL25
AK25
HDMI_TMDSCLKP
HDMI_TMDSCLKN
C
AP23
AN23
AP24
AN24
AR27
VDDA_HDMI
VDDA_HDMI
VDDA_HDMI
VDDA_HDMI
VDDA_HDMI
HDMI_HPDET
AE24
HDMI_EXTSWING
AN25
R480
L22
1
R481
L23
1
R482
L24
1
NO-POP(301)
NO-POP
2
NO-POP(301)
NO-POP
2
NO-POP(301)
NO-POP
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
5V_SUPPLY
LV_SUPPLY
GND.1
TMDSI_D2+
TMDS_GND.1
TMDSI_D2TMDSI_D1+
TMDS_GND.2
TMDSI_D1TMDSI_D0+
TMDS_GND.3
TMDSI_D0TMDSI_CK+
TMDS_GND.4
TMDSI_CKCE_REMOTE_IN
DDC_CLK_IN
DDC_DAT_IN
HOTPLUG_DET_IN
5V_OUT
ESD_BYP
GND.2
TMDSO_D2+
TMDS_GND.5
TMDSO_D2TMDSO_D1+
TMDS_GND.6
TMDSO_D1TMDSO_D0+
TMDS_GND.7
TMDSO_D0TMDSO_CK+
TMDS_GND.8
TMDSO_CKCE_REMOTE_OUT
DDC_CLK_OUT
DDC_DAT_OUT
HOTPLUG_DET_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HDMI_TMDSDN2
HDMI_TMDSDP1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
HDMI_TMDSDN1
HDMI_TMDSDP0
HDMI_TMDSDN0
HDMI_TMDSCLKP
HDMI_TMDSCLKN
MTG1
MTG2
MTG3
MTG4
R249
10K
EVM_5V0
EVM_5V0
D2+
D2 SHIELD
D2D1+
D1 SHIELD
D1D0+
D0 SHIELD
D0CK+
CK SHIELD
CKCE REMOTE
NC.14
DDC CLK
DDC DATA
GND
+5V
HP DET
C
MTG1
MTG2
MTG3
MTG4
HDMI-RA-19-TYPEA
EVM_3V3
R395
5.90K 1%
R250
2K
VDDA_HDMI
1 VOLT
VDDA_HDMI
NO-POP(301)
NO-POP
2
HDMI_TMDSDP2
TPD12S521
NETRA_3
EVM_1V0_CON
P6
U1
R251
2K
R252
27K
EVM_3V3
L17
B
B
0.82Uh
C565
10uF
R4
100K
C533
10uF
C542
1uF
C551
0.1uF
C555
0.01uF
R3
47K
C556
0.01uF
R2
47K
R1
47K
DIFFERENTIAL SIGNALS ROUTE THROUGH ESD DEVICE
PLACE THESE CAPACITORS AS CLOSE TO VDDA PINS AS POSSIBLE
EVM_1V0_CON
EVM_1V0_CON 9,15,16,17,20,49,51,55
A
EVM_3V3
SPECTRUM DIGITAL INCORPORATED
EVM_3V3 2,3,5,6,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
Title:
EVM_5V0
EVM_5V0 28,30,44,46,48,49,51,54,55,56
Page Contents:
HDMI
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
B
512872-0001
Thursday, April 28, 2011
Sheet
1
11 o f
58
5
4
3
2
1
D
D
J12
Pin # Function
1 Ground
2 A+ (Transmit)
3 A- (Transmit)
4 Ground
5 B- (Receive)
6 B+ (Receive)
7 Ground
- coding notch
8
9
MH1 1
2
3
4
5
6
MH9 7
1
2
3
4
5
6
7
SATA HEADER 7
A 7-pin Serial ATA data cable
CON.SATA_TXP0 C107
.1uF
SATA_TXP0
CON.SATA_TXN0
C113
.1uF
SATA_TXN0
CON.SATA_RXN0
C106
.1uF
SATA_RXN0
CON.SATA_RXP0
C112
.1uF
SATA_RXP0
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
C
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
U31-11
R15
T32
T31
J11
Pin # Function
1 Ground
2 A+ (Transmit)
3 A- (Transmit)
4 Ground
5 B- (Receive)
6 B+ (Receive)
7 Ground
- coding notch
8
9
MH1 1
2
3
4
5
6
MH9 7
1
2
3
4
5
6
7
CON.SATA_TXP1
CON.SATA_TXN1
C78
C89
.1uF
V37
V36
.1uF
SATA_TXP1
SATA_TXN1
SATA HEADER 7
A 7-pin Serial ATA data cable
CON.SATA_RXN1
C88
.1uF
CON.SATA_RXP1
C77
.1uF
SATA_RXN1
SATA_RXP1
SATA_TXP0
SATA_TXN0
SATA_RXN0
SATA_RXP0
V33
U33
SATA_TXP1
SATA_TXN1
V35
W35
SATA_RXN1
SATA_RXP1
AB34
AB33
0
CON.PCIE_RXN0
0
CON.PCIE_RXP0
V29
Y29
PCIE_RXN0
PCIE_RXP0
PCIE_RXN1
PCIE_RXP1
V30
V31
PCIE_RXN1
PCIE_RXP1
R27
0
PCIE_TXN0
PCIE_TXP0
AB30
AB31
PCIE_TXN0
PCIE_TXP0
R63
0
AB28
Y27
PCIE_TXN1
PCIE_TXP1
C196
.1uF
C211
.1uF
C159
.1uF CON.PCIE_TXN1
C160
.1uF
PCIE_RXN0
PCIE_RXP0
PCIE_TXN1
PCIE_TXP1
R13
SERDES_CLKP
SERDES_CLKN
CON.PCIE_RXN0 28
C
CON.PCIE_RXP0 28
CON.PCIE_RXN1
CON.PCIE_RXN1 28
CON.PCIE_RXP1
CON.PCIE_TXN0
CON.PCIE_TXP0
CON.PCIE_TXP1
CON.PCIE_RXP1 28
CON.PCIE_TXN0 28
CON.PCIE_TXP0 28
CON.PCIE_TXN1 28
CON.PCIE_TXP1 28
R154
NETRA_3
NO-POP
B
13 SERDES_IN_REFP
13 SERDES_IN_REFN
SERDES_IN_REFP
C116
SERDES_IN_REFN
C115
.1uF
CPU_SERDES_IN_REFP
.1uF
CPU_SERDES_IN_REFN
B
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
SATA INTERFACE
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
12 o f
58
5
4
3
2
1
3V3_VDDA
D
10K
10K
3V3_VDDA
10K
10K
10K
D
10K
10K
3V3_VDDA
R122
Ferrite Chip
C91
C557
C567
C564
10.0uF
0.01uF
0.001uF
0.1uF
0
R95
0
R103
EVM_3V3
VDD_CDC
L26
R128
R104
NO-POP
R377
R123
0
R398
R129
NO-POP
R402
0
R409
R139
NO-POP
3V3_VDDA
L13
LVDS OUTPUT
OSCOUT PIN = OFF
U30
PR1
PR0
NC.24
15
14
13
OD2
OD1
OD0
VCC_OUT.1
VCC_OUT.2
1
4
10
11
OS1
OS0
OUTP1
OUTN1
3
2
PCI_CONN_REFP
PCI_CONN_REFN
6
5
SERDES_IN_REFP
SERDES_IN_REFN
NO-POP
7
12
VCC_PLL1
VCC_PLL2
VCC_VCO
VCC_IN
OUTP0
OUTN0
CE
RSTn
XIN
21
22
REG_CAP2
REG_CAP1
17
19
33
OSCOUT
23
PWR_PAD
NC.27
NC.30
B
NC.8
28
29
31
32
27
30
14,38,41,47 RSTOUTn
C109
C572
C571
0.1uF
10.0uF
0.1uF
0.1uF
FERRITE CHIP
C
PCI_CONN_REFP 28
PCI_CONN_REFN 28
SERDES_IN_REFP 12
SERDES_IN_REFN 12
TP15
1
C75
C76
10.0uF
10.0uF
Y2
25.0000MHz
C87
NO-POP
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
B
3
4
R148
8
C568
0.1uF
18
16
9
20
GND.1
CE = '1' = ON
C569
1
2
R147
10K
3V3_VDDA
26
25
24
NC.28
NC.29
NC.31
NC.32
C
R406
R135
EVM_3V3
TP
CDCM61002
R475
0
VCO = PRE-SCALE X DIVIDER X FIN
VCO = 3 X 24 X 25MHZ
VCO = 1800 MHZ
OUTCLOCK = VCO FREQ /( PRESCALE*OD) = 100mHZ
OUTCLOCK = 1800 /( 6*3) = 100mHZ
EVM_3V3
EVM_3V3 2,3,5,6,11,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
SERDES CLOCKS
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
13 o f
58
5
4
3
2
1
EVM_3V3
EVM_3V3
R430
10K
C658
0.1uF
D
5
D
EMU_RSTn
U37
U31-13
1
4
G33
RESETn
F37
PORn
G36
NMIn
2
3
47 EXP_WARM_RESET
SN74LVC1G08DCKRG4
EVM_3V3
EVM_3V3
5
C659
0.1uF
WD_OUT
C661
0.1uF
1
2
5
4
U36
SN74LVC1G00DCKRG4
3
28 OPT_SW2
4
RTCK
3
EVM_3V3
TDO
5
C660
0.1uF
56 CPU_PORz
1
28 PCI_PORz
2
EVM_3V3
GP0_IO0
GP0_IO1
GP0_IO2
GP0_IO3
54
54
54
54
H32
G2
G5
H35
GP0_IO4
GP0_IO5
GP0_IO6
GP0_IO7
47
47
47
47
J32
J33
MSP430_INT 50
GP1_IO30 50
J34
TDI
R428 1
2 22
N30
TDO
TMS
N31
TMS
TRSTn
K36
TRSTn
J35
L36
L37
M36
M37
EMU0
EMU1
EMU2
EMU3
EMU4
GP1[30]/SATA_ACT0_LED
GP1[31]/SATA_ACT1_LED
C
GP1_IO31 38
ENET_INTn 38
U35
R182
10K
4
3
K31
L29
K30
J31
J36
TDI_T
SN74LVC1G08DCKRG4
GP0[0]
GP0[1]
GP0[2]
GP0[3]/TCLKIN
2 22
J37
RSTOUTn 13,38,41,47
WD_OUT
H36
R180 1
TCK_T
PORz
G37
WD_OUT
GP0[4]
GP0[5]/MCA[2]_AMUTEIN/GPMC_A[24]
TCLK GP0[6]/MCA[1]_AMUTEIN/GPMC_A[23]
GP0[7]/MCA[0]_AMUTEIN
RTCK
U34
1
2
C
RSTOUTn
EMU0
EMU1
EMU2
EMU3
EMU4
CPU_NMIn
SN74LVC1G08DCKRG4
R429
R177
R176
R173
R175
R181
NO-POP
1
1
1
1
1
2
2
2
2
2
22
22
22
22
22
NETRA_3
B
B
EVM_3V3
R163
0
R162
4.7K
J15
EVM_3V3
TDI_T
R193
4.7K
TRSTn
R190
0
EVM_3V3
R189
TMS
TDI
22
R192
4.7K
TCK_T
R191
TDO
RTCK
TCK
EMU0
22
EMU_RSTn
EMU2
EMU4
A
1
3
5
7
9
11
13
15
17
19
TMS
TDI
TVD
TDO
TCKRTN
TCLK
EMU0
SRST
EMU2
EMU4
TRSTn
TDIS
KEY
GND.1
GND.2
GND.3
EMU1
GND.4
EMU3
GND.5
2
4
6
8
10
12
14
16
18
20
EVM_3V3
R164
4.7K
EMU1
EMU3
SPECTRUM DIGITAL INCORPORATED
20 PIN CTI INTERFACE
Title:
EVM_3V3
EVM_3V3 2,3,5,6,11,13,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
Page Contents:
JTAG/GPIO/RESET
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
14 o f
58
5
4
3
2
1
U31-15
1.8 VOLT
D
N19
RSV3
N20
RSV4
DEVOSC_DVDD18
E19
DEV_MXI/DEV_CLKIN
A19
5
18 pF
C224
C757
0.001uF
C759
0.1uF
EVM_3V3
U55
CPU_DEVOSC
C764
1uF
C768
1uF
4
OUT
1
IN
GND
2
NC/FB ENn
3
C336
0.1uF
D
Y4
27MHz
TPS77018DBV
H37
CLKIN32
DEV_MXO
C19
DEVOSC_VSS
B19
18 pF
C264
EVM_3V3
EVM_1V8_D
R494
10K
RSV18
P33
RSV16
R34
3
EVM_1V0_CON
RSV17
P34
RSV19
P32
1K
Q8
FJV3109R
1
R496
10K
C
2
R495
C
C802
0.1uF
NETRA_3
R188
0
B
B
EVM_3V3
L5
2
1
BLM21PG221SN1D
R68
10K
C26
.1uF
c402-25
U15
EVM_1V0_CON
EVM_3V3
1
EN
VCC
4
2
GND
OUT
3
EVM_1V0_CON 9,11,16,17,20,49,51,55
32K HERTZ
EVM_1V8_D
SPECTRUM DIGITAL INCORPORATED
A
A
EVM_1V8_D 5,16,49,52,55
NETRA EVM
Title:
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
Page Contents:
NETRA CLOCKS
Size:B
DWG NO
Date:
5
4
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
15 o f
58
5
4
E3
NFM21PC474R1C3D
3
1
2
B18
A18
C195
0.001uF
VDDA_PLL
VDDA_PLL
VDDR_SATA
VDDR_SATA
V25
U25
C618
0.1uF
C174
0.01uF
B20
A20
U19
VDDR_PCIE
VDDR_PCIE
1.8 VOLT
AJ24
C608
0.1uF
D
EVM_1V5
1.5 VOLT
VSSA_PLL
VSSA_PLL
VSSA_PLL
CPU_VDDA_1P8V
C552
0.1uF
EVM_1V5
U31-2
CPU_VDDA_PLL
C214
0.1uF
1
1.5 VOLT
1.5 VOLT
D
2
Y25
W25
C632
0.1uF
C617
0.1uF
DVDD1P8
C534
0.001uF
EVM_1V0_CON
E4
NFM21PC474R1C3D
1
3
1.0 VOLT
CPU_VDDA_1P8V
VDDT_SATA
VDDT_SATA
VDDT_SATA
VDDT_SATA
1.8 VOLT
AJ20
C
C90
0.1uF
V32
Y33
Y34
V34
DVDD1P8
CPU_VDDT
C585
0.01uF
C586
0.001uF
C583
0.1uF
C584
0.1uF
2
EVM_1V5
3
C
C67
0.001uF
1.8 VOLT
EVM_1V8_D
1.0 VOLT
R422
VPP_1V8
0
C581
0.1uF
C580
0.1uF
AG25
AG24
AH25
AH24
RSV12
RSV13
RSV14
RSV15
VDDT_PCIE
VDDT_PCIE
VDDT_PCIE
VDDT_PCIE
VDDT_PCIE
AB27
Y28
AB29
Y30
AB32
CPU_VDDT
C579
0.01uF
C578
0.001uF
C577
0.1uF
C576
0.1uF
NETRA_3
U31-22
U31-17
B
CPU_VDDA_1P8V
CPU_VDDA_1P8V 9
N28
RSV10
N29
RSV11
EVM_1V0_CON
EVM_1V0_CON 9,11,15,17,20,49,51,55
EVM_1V0_CON
RSV20
D14
RSV8
D24
RSV1
AB36
RSV2
P25
RSV9
AU37
RSV7
AE23
B
NETRA_3
EVM_1V0_CON 9,11,15,17,20,49,51,55
NETRA_3
EVM_1V8_D
A
SPECTRUM DIGITAL INCORPORATED
EVM_1V8_D 5,15,49,52,55
Title:
EVM_1V5
EVM_1V5
Page Contents:
NETRA POWER PINS
Size:B
DWG NO
7,8,17,21,23,24,25,27,49,52,53,55,56
Date:
5
A
NETRA EVM
4
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
16 o f
58
5
4
3
2
1
1 VOLT
EVM_1V0_CON
EVM_1V0_CON
C63
33uF
D
+
C74
C538
0.1uF
EVM_1V0_CON
U31-18
C72
0.1uF
C540
0.1uF
C92
0.1uF
C554
0.1uF
C85
0.1uF
C549
0.1uF
0.1uF
C84
C550
0.1uF
0.1uF
N13
N25
CVDDC
CVDDC
CVDDC
CVDDC
AE13
AE25
P14
P15
P23
P24
CVDDC
CVDDC
CVDDC
CVDDC
CVDDC
CVDDC
CVDDC
CVDDC
AC14
AC15
AC23
AC24
R14
R15
R23
R24
CVDDC
CVDDC
CVDDC
CVDDC
CVDDC
CVDDC
CVDDC
CVDDC
AD14
AD15
AD23
AD24
EVM_1V0_CON
+
C69
0.1uF
C535
0.1uF
C66
0.1uF
C532
0.1uF
C530
0.1uF
C55
0.1uF
C52
0.1uF
C562
0.1uF
C529
0.1uF
C117
33uF
C95
0.1uF
D
EVM_1V0_CON
NETRA_3
EVM_1V0_CON 9,11,15,16,20,49,51,55
1.5 VOLT
EVM_1V5
C189
0.1uF
C
C680
0.1uF
C207
0.1uF
C674
0.1uF
C208
0.1uF
EVM_1V5
+
EVM_1V5
U31-19
EVM_1V5
C354
33uF
C647
0.1uF
C646
0.1uF
C679
0.1uF
A2
A11
E1
E11
J15
J14
J16
J17
J18
K14
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
C188
0.1uF
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
K15
K16
K17
K18
K19
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
L14
L15
L16
L17
L18
L19
EVM_1V5
C142
0.1uF
C185
0.1uF
C205
0.1uF
C184
0.1uF
C203
0.1uF
C187
0.1uF
C186
0.1uF
C
EVM_1V5
C151
0.1uF
NETRA_3
C183
0.1uF
C206
0.1uF
C230
33uF
C204
0.1uF
+
1.5 VOLT
EVM_1V5
EVM_1V5
U31-20
EVM_1V5
B
+
C368
33uF
C176
C201
C202
C149
0.1uF
0.1uF
0.1uF
0.1uF
EVM_1V5
C180
0.1uF
C178
0.1uF
C182
0.1uF
C181
0.1uF
C177
0.1uF
A27
A36
D37
E27
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
J19
J21
J20
J22
J23
J24
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
C179
0.1uF
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
K20
K21
K22
K23
K24
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
DVDD_DDR[1]
L20
L21
L22
L23
L24
EVM_1V5
B
C200
0.1uF
C197
0.1uF
C681
0.1uF
C682
0.1uF
C198
0.1uF
C150
0.1uF
C199
0.1uF
C223
33uF
+
EVM_1V5
C683
C648
C700
0.1uF
0.1uF
0.1uF
NETRA_3
EVM_1V5
EVM_1V5
A
7,8,16,21,23,24,25,27,49,52,53,55,56
SPECTRUM DIGITAL INCORPORATED
Title:
Page Contents:
NETRA POWER PINS II
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
17 o f
58
5
4
3
2
1
3.3 VOLT
EVM_3V3
EVM_3V3
U31-21
EVM_3V3
C138
C139
C98
C559
C541
C96
C561
C546
C539
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
D
EVM_3V3
EVM_3V3
C560
C545
C79
C544
C553
C536
C56
C73
C71
C80
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
EVM_3V3
EVM_3V3
C547
C650
C649
C651
C543
C68
C531
C144
C145
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C
EVM_3V3
EVM_3V3
+
C51
33uF
+
C131
33uF
C93
C81
C82
C558
0.1uF
0.1uF
0.1uF
0.1uF
L1
L5
L30
L35
P8
P9
P10
P11
P27
P28
P29
P30
R9
R10
R11
R27
R28
T9
T10
T11
U9
U10
U11
Y9
AA1
AA9
AA10
AA11
AB9
AB10
AB11
AC9
AC10
AC11
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
AC27
AC28
AC29
AD9
AD10
AD11
AD27
AD28
AD29
AE27
EVM_3V3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
AE28
AE29
AG14
AG15
AG16
AG17
AG33
AH14
AH15
AH16
EVM_3V3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
AH17
AJ14
AJ15
AJ16
AJ17
EVM_3V3
DVDD_3P3
DVDD_3P3
DVDD_3P3
DVDD_3P3
AN1
AN11
AN27
AN37
DVDD_3P3
DVDD_3P3
DVDD_3P3
C128
0.1uF
C637
0.1uF
C124
0.1uF
C120
0.1uF
C111
0.1uF
C591
0.1uF
C566
0.1uF
C146
0.1uF
C108
0.1uF
C589
0.1uF
D
EVM_3V3
C592
C133
0.1uF
C615
0.1uF
C652
0.1uF
C125
0.1uF
C644
.1uF
C570
.1uF
C121
.1uF
C129
.1uF
C83
.1uF
0.1uF
EVM_3V3
C613
C636
C638
0.1uF
0.1uF
0.1uF
C134
0.1uF
C114
C105
C122
C593
C614
C135
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C
EVM_3V3
EVM_3V3
AU2
AU11
AU29
C643
C590
C147
C130
0.1uF
0.1uF
0.1uF
0.1uF
+
+
C140
33uF
C53
33uF
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
NETRA_3
EVM_1V0_AVS
CORE AVS SUPPLY 1.0 VOLT
EVM_1V0_AVS 20,49,54
U31-16
EVM_1V0_AVS
B
EVM_1V0_AVS
C645
C597
C600
C601
C594
C598
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C620
0.1uF
C599
C137
C619
0.1uF
0.1uF
0.1uF
EVM_1V0_AVS
EVM_1V0_AVS
C164
33uF
+
C141
33uF
+
C604
C605
C606
C603
0.1uF
0.1uF
0.1uF
0.1uF
A
EVM_1V0_AVS
P16
P17
P18
P19
P20
P21
P22
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
AD16
AD17
AD18
AD19
AD20
AD21
AD22
R16
R17
R18
R19
R20
R21
R22
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
AC16
AC17
AC18
AC19
AC20
AC21
AC22
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
B
EVM_1V0_AVS
C622
C629
C627
0.1uF
0.1uF
0.1uF
4
3
0.1uF
C621
C602
C595
C624
C596
C631
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
EVM_1V0_AVS
EVM_1V0_AVS
C628
C626
C623
C625
0.1uF
0.1uF
0.1uF
0.1uF
+
+
C123
33uF
C165
33uF
SPECTRUM DIGITAL INCORPORATED
Page Contents:
NETRA POWER PINS III
Size:B
DWG NO
Date:
2
A
NETRA EVM
Title:
NETRA_3
5
C630
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
18 o f
58
4
2
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U31-1
3
W20
W21
W22
W23
W24
Y4
Y5
Y6
Y7
Y8
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y31
Y32
Y36
Y37
AA5
AA6
AA7
AA8
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AB1
AB6
AB7
AB8
AB35
AB37
AC3
AC4
AC6
AC7
AC8
5
D
A1
A10
A28
A37
C15
C17
C21
C23
D1
E14
E24
E37
F7
F14
F15
F16
F17
F21
F22
F23
F31
F24
G6
G7
G14
G15
G16
G17
G18
G20
G21
G22
G23
G24
G31
G32
H11
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H27
K1
K37
L8
L12
L26
L33
M11
M27
N18
P4
P5
P6
P7
P31
R3
R4
R6
R7
R8
R31
C
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D
AC30
AC31
AC33
AC32
AC34
AD5
AD6
AD7
AD30
AD31
AD32
AD33
AD34
AE17
AE18
AE19
AE20
AF11
AF27
AG5
AG8
AG12
AG26
AG30
AJ18
AJ25
AK11
AK15
AK16
AK17
AK18
AK19
AK23
AK24
AK27
AL6
AL7
AL15
AL16
AL17
AL18
AL19
AL23
AL24
AL31
AL32
AM1
AM7
AM15
AM16
AM17
AM18
AM19
AM23
AM24
AM25
AM31
AN14
AN15
AP15
AP37
AR15
AR23
AR24
AR25
AT23
AU1
AU12
AU23
AU28
C
B
SPECTRUM DIGITAL INCORPORATED
Page Contents:
NETRA GROUND PINS
Size:B
DWG NO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Date:
5
4
3
2
A
NETRA EVM
Title:
U20
U21
U22
U23
U24
V4
V5
V6
V7
V8
V9
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V27
V28
W6
W7
W8
W9
W13
W14
W15
W16
W17
W18
W19
NETRA_3
R32
R33
T6
T7
T8
T33
T34
T35
U5
U6
U7
U8
U13
U14
U15
U16
U17
U18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
19 o f
58
5
4
3
2
1
EVM_1V0_AVS
EVM_1V0_AVS
EVM_1V0_AVS
EVM_1V0_AVS 18,49,54
C440
0.1uF
C433
0.1uF
C392
0.1uF
C441
0.1uF
C434
0.1uF
C414
0.1uF
C407
0.1uF
C391
0.1uF
C398
0.1uF
C405
0.1uF
C412
0.1uF
C419
0.1uF
C399
0.1uF
C426
0.1uF
C442
0.1uF
D
D
EVM_1V0_AVS
C428
0.1uF
EVM_1V0_CON
C435
0.1uF
C427
0.1uF
C406
0.1uF
C413
0.1uF
C420
0.1uF
C400
0.1uF
C393
0.1uF
EVM_1V0_CON 9,11,15,16,17,49,51,55
C
C
EVM_1V0_CON
EVM_1V0_CON
C390
0.1uF
C397
0.1uF
C389
0.1uF
C439
0.1uF
C432
0.1uF
C431
0.1uF
C438
0.1uF
C396
0.1uF
B
B
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
CAPS, 1V0_CON,1V0_AVS
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
20 o f
58
5
4
3
U52
D
7,22,24 DDR0_A0
7,22,24 DDR0_A1
7,22,24 DDR0_A2
7,22,24 DDR0_A3
7,22,24 DDR0_A4
7,22,24 DDR0_A5
7,22,24 DDR0_A6
7,22,24 DDR0_A7
7,22,24 DDR0_A8
7,22,24 DDR0_A9
7,22,24 DDR0_A10
7,22,24 DDR0_A11
7,22,24 DDR0_A12
7,22,24 DDR0_A13
7,22,24 DDR0_A14
7,22,24 DDR0_BA0
7,22,24 DDR0_BA1
7,22,24 DDR0_BA2
7,22,24 DDR0_RASN
7,22,24 DDR0_CASN
7,22,24 DDR0_W EN
7,22,24 DDR0_ODT0
7,22,24 DDR0_CKE
7,22,24 DDR0_CSN0
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
DDR0_BA0
DDR0_BA1
DDR0_BA2
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J2
K8
J3
DDR0_RASn
DDR0_CASn
DDR0_WEn
DDR0_ODT0
DDR0_CKE
DDR0_CE0n
F3
G3
H3
G1
G9
H2
7,22,24 DDR0_CLK0
7,22,24 DDR0_CLK0N
DDR0_CK0 F7
DDR0_CK0n G7
7 DDR0_RST
DDR0_RESETn N2
EVM_DDR_REF_OUT
C
R227
240
B
7
7
7
7
DDR0_D5
DDR0_D0
DDR0_D4
DDR0_D6
7
7
7
7
DDR0_D7
DDR0_D1
DDR0_D2
DDR0_D3
7
7
7
7
MEM00_D0
MEM00_D1
MEM00_D2
MEM00_D3
MEM00_D4
MEM00_D5
MEM00_D6
MEM00_D7
TDDR0_DM0
E1
EVM_DDR_REF_OUT
TDDR0_DQS0
TDDR0_DQSN0
A3
F1
F9
H1
H9
J7
VREFCA
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSS.6
VSS.7
VSS.8
VSS.9
VSS.10
VSS.11
VSS.12
H8
ZQ
B2
B8
C9
D1
D9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
EVM_1V5
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDD.6
VDD.7
VDD.8
VDD.9
A2
A9
D7
G2
G8
K1
K9
M1
M9
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
B9
C1
E2
E9
R226
240
EDJ1108DBSE
RN3
RPACK4-0
8
1
7
2
6
3
5
4
0
TDDR0_DM0
R204
R205
0
0
TDDR0_DQS0
TDDR0_DQSN0
8
7
6
5
RN13
5
6
7
8
E1
EVM_DDR_REF_OUT
TDDR0_DQS1
TDDR0_DQSN1
A3
F1
F9
H1
H9
J7
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
DDR0_BA0
DDR0_BA1
DDR0_BA2
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J2
K8
J3
DDR0_RASn
DDR0_CASn
DDR0_WEn
DDR0_ODT0
DDR0_CKE
DDR0_CE0n
F3
G3
H3
G1
G9
H2
DDR0_CK0 F7
DDR0_CK0n G7
DDR0_RESETn N2
RESET
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSS.6
VSS.7
VSS.8
VSS.9
VSS.10
VSS.11
VSS.12
H8
ZQ
B2
B8
C9
D1
D9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
EVM_DDR_REF_OUT
EVM_1V5
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDD.6
VDD.7
VDD.8
VDD.9
A2
A9
D7
G2
G8
K1
K9
M1
M9
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
B9
C1
E2
E9
DDR0_DQS1 R442
DDR0_DQSN1 R441
0
0
TDDR0_DQS1
TDDR0_DQSN1
DDR0_D17
DDR0_D19
DDR0_D18
DDR0_D16
7
7
7
7
DDR0_D22
DDR0_D20
DDR0_D23
DDR0_D21
7 DDR0_DQM2
R225
240
7
7
7
7
DDR0_D25
DDR0_D29
DDR0_D31
DDR0_D26
DDR0_D27
DDR0_D24
DDR0_D30
DDR0_D28
7 DDR0_DQM3
7 DDR0_DQS3
7 DDR0_DQSN3
4
U49
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DM/TDQS
A9
TDQS
A10/AP
DQS
A11
DQS
A12/BC
A13
A14/NC VREFDQ
BA0
BA1
NC.1
BA2
NC.2
NC.3
RAS
NC.4
CAS
NC.5
WE
NC.6
ODT
CKE
CS
B3
C7
C2
C8
E3
E8
D2
E7
B7
A7
C3
D3
MEM02_D0
MEM02_D1
MEM02_D2
MEM02_D3
MEM02_D4
MEM02_D5
MEM02_D6
MEM02_D7
TDDR0_DM2
E1
EVM_DDR_REF_OUT
TDDR0_DQS2
TDDR0_DQSN2
A3
F1
F9
H1
H9
J7
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSS.6
VSS.7
VSS.8
VSS.9
VSS.10
VSS.11
VSS.12
H8
ZQ
B2
B8
C9
D1
D9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DDR0_RASn
DDR0_CASn
DDR0_WEn
DDR0_ODT0
DDR0_CKE
DDR0_CE0n
F3
G3
H3
G1
G9
H2
DDR0_RESETn N2
RESET
VREFCA
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J2
K8
J3
DDR0_CK0 F7
DDR0_CK0n G7
CK
CK
J8
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
DDR0_BA0
DDR0_BA1
DDR0_BA2
EVM_DDR_REF_OUT
EVM_1V5
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDD.6
VDD.7
VDD.8
VDD.9
A2
A9
D7
G2
G8
K1
K9
M1
M9
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
B9
C1
E2
E9
R224
240
8
7
6
5
RPACK4-0
1 MEM02_D6
2 MEM02_D2
3 MEM02_D0
4 MEM02_D4
DDR0_D22
DDR0_D20
DDR0_D23
DDR0_D21
RN14
5
6
7
8
RPACK4-0
4 MEM02_D7
3 MEM02_D1
2 MEM02_D5
1 MEM02_D3
R444
0
TDDR0_DM2
DDR0_DQSN2 R445
DDR0_DQS2 R446
DDR0_DM2
0
0
TDDR0_DQSN2
TDDR0_DQS2
DDR0_D25
DDR0_D29
DDR0_D31
DDR0_D26
DDR0_D27
DDR0_D24
DDR0_D30
DDR0_D28
DDR0_DM3
8
7
6
5
RPACK4-0
1
2
3
4
RN15
5
6
7
8
B3
C7
C2
C8
E3
E8
D2
E7
B7
A7
C3
D3
MEM03_D0
MEM03_D1
MEM03_D2
MEM03_D3
MEM03_D4
MEM03_D5
MEM03_D6
MEM03_D7
TDDR0_DM3
E1
EVM_DDR_REF_OUT
D
TDDR0_DQS3
TDDR0_DQSN3
A3
F1
F9
H1
H9
J7
CK
CK
RESET
VREFCA
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSS.6
VSS.7
VSS.8
VSS.9
VSS.10
VSS.11
VSS.12
H8
ZQ
B2
B8
C9
D1
D9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
C
EVM_1V5
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDD.6
VDD.7
VDD.8
VDD.9
A2
A9
D7
G2
G8
K1
K9
M1
M9
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
B9
C1
E2
E9
EDJ1108DBSE
B
EVM_DDR_REF_OUT
EVM_DDR_REF_OUT 7,8,23,25,27,53
MEM03_D6
MEM03_D2
MEM03_D0
MEM03_D4
EVM_1V5
EVM_1V5
RPACK4-0
4 MEM03_D7
MEM03_D1
3
MEM03_D5
2
MEM03_D3
1
R439
0
TDDR0_DM3
DDR0_DQS3 R450
DDR0_DQSN3 R449
0
0
TDDR0_DQS3
TDDR0_DQSN3
7,8,16,17,23,24,25,27,49,52,53,55,56
SPECTRUM DIGITAL INCORPORATED
2
A
NETRA EVM
Title:
Page Contents:
EMIF DDR0 DDR3 MEM BANK0
Size:B
DWG NO
Date:
3
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DM/TDQS
A9
TDQS
A10/AP
DQS
A11
DQS
A12/BC
A13
A14/NC VREFDQ
BA0
BA1
NC.1
BA2
NC.2
NC.3
RAS
NC.4
CAS
NC.5
WE
NC.6
ODT
CKE
CS
J8
EDJ1108DBSE
DDR0_D17
DDR0_D19
DDR0_D18
DDR0_D16
RN7
7
7
7
7
RPACK4-0
MEM01_D7
4
MEM01_D1
3
MEM01_D5
2
MEM01_D3
1
0
7
7
7
7
7 DDR0_DQSN2
7 DDR0_DQS2
RPACK4-0
MEM01_D6
1
MEM01_D2
2
MEM01_D0
3
MEM01_D4
4
R215
5
MEM01_D0
MEM01_D1
MEM01_D2
MEM01_D3
MEM01_D4
MEM01_D5
MEM01_D6
MEM01_D7
TDDR0_DM1
CK
CK
VREFCA
MEM00_D7
MEM00_D1
MEM00_D5
MEM00_D3
TDDR0_DM1
7 DDR0_DQM1
B3
C7
C2
C8
E3
E8
D2
E7
B7
A7
C3
D3
RN4
R438
DDR0_DM1
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DM/TDQS
A9
TDQS
A10/AP
DQS
A11
DQS
A12/BC
A13
A14/NC VREFDQ
BA0
BA1
NC.1
BA2
NC.2
NC.3
RAS
NC.4
CAS
NC.5
WE
NC.6
ODT
CKE
CS
J8
1
U50
EDJ1108DBSE
DDR0_DM0
DDR0_D9
DDR0_D11
DDR0_D8
DDR0_D10
F3
G3
H3
G1
G9
H2
MEM00_D6
MEM00_D2
MEM00_D0
MEM00_D4
DDR0_DQS0
DDR0_DQSN0
7 DDR0_D9
7 DDR0_D11
7 DDR0_D8
7 DDR0_D10
DDR0_RASn
DDR0_CASn
DDR0_WEn
DDR0_ODT0
DDR0_CKE
DDR0_CE0n
EVM_DDR_REF_OUT
RPACK4-0
4
3
2
1
A
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J2
K8
J3
DDR0_RESETn N2
RESET
RN5
DDR0_D13
DDR0_D12
DDR0_D14
DDR0_D15
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_A14
DDR0_BA0
DDR0_BA1
DDR0_BA2
DDR0_CK0 F7
DDR0_CK0n G7
CK
CK
RN12
5
6
7
8
DDR0_D13
DDR0_D12
DDR0_D14
DDR0_D15
7 DDR0_DQS1
7 DDR0_DQSN1
B3
C7
C2
C8
E3
E8
D2
E7
B7
A7
C3
D3
DDR0_D7
DDR0_D1
DDR0_D2
DDR0_D3
7 DDR0_DQM0
7 DDR0_DQS0
7 DDR0_DQSN0
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DM/TDQS
A9
TDQS
A10/AP
DQS
A11
DQS
A12/BC
A13
A14/NC VREFDQ
BA0
BA1
NC.1
BA2
NC.2
NC.3
RAS
NC.4
CAS
NC.5
WE
NC.6
ODT
CKE
CS
J8
DDR0_D5
DDR0_D0
DDR0_D4
DDR0_D6
2
U51
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
21 o f
58
5
4
3
2
1
This section is an outline of vias labeled as Testpoints in the schematic. This allows us to determine pwb line lengths for memory to
memory and CPU to memory it is purely a visibility tool no actual "component" is used the vias are just replaced with a via that is
labeled a test point
DATA D24-D31 MEMORY
DATA D16-D23 MEMORY
DATA D8-D15 MEMORY
DATA D0-D7 MEMORY
D
D
7,21,24 DDR0_A0
DDR0_A0
7,21,24 DDR0_A1
DDR0_A1
7,21,24 DDR0_A2
1
TPM15
1
TPMB15
1
TPMC15
1
TPMD15
1
TPM19
1
TPMB19
1
TPMC19
DDR0_A2
1
TPM18
1
1
TPMD19
TPMB18
1
TPMC18
1
7,21,24 DDR0_A3
DDR0_A3
1
TPM13
TPMD18
1
TPMB13
1
TPMC13
1
7,21,24 DDR0_A4
DDR0_A4
1
TPMD13
TPM17
1
TPMB17
1
TPMC17
1
7,21,24 DDR0_A5
DDR0_A5
TPMD17
1
TPM16
1
TPMB16
1
TPMC16
1
7,21,24 DDR0_A6
TPMD16
DDR0_A6
1
TPM21
1
TPMB21
1
TPMC21
1
TPMD21
7,21,24 DDR0_A7
DDR0_A7
1
TPM20
1
TPMB20
1
TPMC20
1
TPMD20
7,21,24 DDR0_A8
DDR0_A8
1
TPM24
1
TPMB24
1
TPMC24
1
TPMD24
7,21,24 DDR0_A9
DDR0_A9
1
TPM22
1
TPMB22
1
TPMC22
1
TPMD22
7,21,24 DDR0_A10
DDR0_A10
1
TPM7
1
TPMB7
1
TPMC7
1
TPMD7
7,21,24 DDR0_A11
DDR0_A11
1
TPM23
1
TPMB23
1
TPMC23
1
TPMD23
7,21,24 DDR0_A12
DDR0_A12
1
TPM14
1
TPMB14
1
TPMC14
1
TPMD14
7,21,24 DDR0_A13
DDR0_A13
1
TPM25
1
TPMB25
1
TPMC25
1
TPMD25
7,21,24 DDR0_A14
DDR0_A14
1
TPM26
1
TPMB26
1
TPMC26
1
TPMD26
7,21,24 DDR0_BA0
DDR0_BA0
1
TPM11
1
TPMB11
1
TPMC11
1
TPMD11
7,21,24 DDR0_BA1
DDR0_BA1
1
TPM12
1
TPMB12
1
TPMC12
1
TPMD12
7,21,24 DDR0_BA2
DDR0_BA2
1
TPM10
1
TPMB10
1
TPMC10
1
TPMD10
7,21,24 DDR0_RASN
DDR0_RASn
1
TPM2
1
TPMB2
1
TPMC2
1
TPMD2
7,21,24 DDR0_CASN
DDR0_CASn
1
TPM6
1
TPMB6
1
TPMC6
1
TPMD6
7,21,24 DDR0_W EN
DDR0_WEn
1
TPM8
1
TPMB8
1
TPMC8
1
TPMD8
7,21,24 DDR0_ODT0
DDR0_ODT0
1
TPM5
1
TPMB5
1
TPMC5
1
TPMD5
7,21,24 DDR0_CKE
DDR0_CKE
1
TPM4
1
TPMB4
1
TPMC4
1
TPMD4
7,21,24 DDR0_CSN0
DDR0_CE0n
1
TPM9
1
TPMB9
1
TPMC9
1
TPMD9
7,21,24 DDR0_CLK0
DDR0_CK0
1
TPM1
1
TPMB1
1
TPMC1
1
TPMD1
DDR0_CK0n
1
TPM3
1
TPMB3
1
TPMC3
1
TPMD3
C
B
7,21,24 DDR0_CLK0N
C
B
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
DDR0 ADDRESS CONTROL TEST POINTS FOR ROUTING
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
22 o f
58
5
4
3
2
1
EVM_1V5
EVM_1V5
C191
0.1uF
C193
0.1uF
C686
0.1uF
7,8,16,17,21,24,25,27,49,52,53,55,56
C665
0.1uF
C667
0.1uF
C702
0.1uF
C677
0.1uF
C697
0.1uF
C690
0.1uF
D
D
EVM_DDR_REF_OUT
EVM_1V5
EVM_DDR_REF_OUT 7,8,21,25,27,53
EVM_1V5
EVM_DDR_REF_OUT
C670
0.1uF
C678
0.1uF
C687
0.1uF
C699
0.1uF
C696
0.1uF
C684
0.1uF
C685
0.1uF
C675
0.1uF
C167
0.1uF
C192
0.1uF
C673
0.1uF
C691
0.1uF
C163
0.1uF
C664
0.1uF
C156
0.1uF
C669
0.1uF
C656
0.1uF
EVM_DDR_REF_OUT
C672
0.1uF
EVM_1V5
C260
0.1uF
C262
0.1uF
C263
0.1uF
C349
0.1uF
C351
0.1uF
C261
0.1uF
EVM_1V5
EVM_1V5
EVM_1V5
EVM_DDR_REF_OUT
C
C695
0.1uF
C701
0.1uF
C676
0.1uF
C663
0.1uF
C655
0.1uF
C654
0.1uF
C703
0.1uF
C166
0.1uF
EVM_DDR_REF_OUT
C169
0.1uF
C698
0.1uF
C170
0.1uF
C194
0.1uF
C668
0.1uF
C168
0.1uF
C688
0.1uF
C158
0.1uF
C157
0.1uF
C662
0.1uF
C
C348
0.1uF
EVM_1V5
C733
0.1uF
C350
0.1uF
EVM_1V5
C743
0.1uF
C715
0.1uF
C724
0.1uF
C745
0.1uF
C720
0.1uF
C285
0.1uF
C322
0.1uF
C722
0.1uF
C732
0.1uF
C175
0.1uF
C155
0.1uF
C671
0.1uF
C689
0.1uF
C190
0.1uF
C286
0.1uF
C323
0.1uF
C254
0.1uF
C277
0.1uF
C287
0.1uF
C331
0.1uF
C255
0.1uF
C741
0.1uF
C730
0.1uF
C233
0.1uF
C309
0.1uF
C276
0.1uF
C711
0.1uF
C311
0.1uF
C245
0.1uF
C308
0.1uF
C234
0.1uF
C244
0.1uF
C324
0.1uF
C740
0.1uF
C731
0.1uF
C296
0.1uF
C312
0.1uF
C295
0.1uF
EVM_1V5
EVM_1V5
B
C231
0.1uF
C242
0.1uF
C274
0.1uF
C284
0.1uF
C306
0.1uF
C321
0.1uF
C328
0.1uF
C305
0.1uF
C252
0.1uF
C293
0.1uF
EVM_1V5
C788
0.1uF
B
EVM_1V5
C728
0.1uF
C753
0.1uF
C783
0.1uF
C767
0.1uF
C762
0.1uF
C748
0.1uF
C253
0.1uF
C723
0.1uF
C275
0.1uF
EVM_1V5
C742
0.1uF
C330
0.1uF
C721
0.1uF
C310
0.1uF
C772
0.1uF
EVM_1V5
C712
0.1uF
C294
0.1uF
C713
0.1uF
C243
0.1uF
C719
0.1uF
C718
0.1uF
C329
0.1uF
C307
0.1uF
C232
0.1uF
C778
0.1uF
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
DDR MEMORY CAPS DDR0 INTERFACE
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
23 o f
58
5
4
DDR0_CK0
7,21,22 DDR0_CLK0
7,21,22 DDR0_CLK0N
D
DDR0_CLK0N
R452
DDR0_RASN
DDR0_CKE
DDR0_CASN
DDR0_ODT0
RN20
8
7
6
5
7,21,22 DDR0_A10
7,21,22 DDR0_W EN
7,21,22 DDR0_CSN0
7,21,22 DDR0_BA2
DDR0_A10
DDR0_W EN
DDR0_CSN0
DDR0_BA2
RN22
8
7
6
5
RPack4-47
1
2
3
4
DDR0_BA1
DDR0_BA0
DDR0_A3
DDR0_A12
RN24
8
7
6
5
RPack4-47
1
2
3
4
7,21,22 DDR0_BA1
7,21,22 DDR0_BA0
7,21,22 DDR0_A3
7,21,22 DDR0_A12
DDR0_A0
DDR0_A5
DDR0_A4
DDR0_A2
DDR0_A0
DDR0_A5
DDR0_A4
DDR0_A2
RN26
8
7
6
5
RPack4-47
1
2
3
4
7,21,22
7,21,22
7,21,22
7,21,22
DDR0_A1
DDR0_A7
DDR0_A6
DDR0_A9
DDR0_A1
DDR0_A7
DDR0_A6
DDR0_A9
RN28
8
7
6
5
RPack4-47
1
2
3
4
DDR0_A11
DDR0_A8
DDR0_A13
DDR0_A14
RN30
8
7
6
5
RPack4-47
1
2
3
4
7,21,22 DDR0_A11
7,21,22 DDR0_A8
7,21,22 DDR0_A13
7,21,22 DDR0_A14
49.9
RPack4-47
1
2
3
4
7,21,22
7,21,22
7,21,22
7,21,22
C
EVM_1V5
49.9
R454
7,21,22 DDR0_RASN
7,21,22 DDR0_CKE
7,21,22 DDR0_CASN
7,21,22 DDR0_ODT0
3
C714
C735
0.1uF
0.1uF
C750
0.1uF
C755
0.1uF
C760
0.1uF
C765
0.1uF
C770
0.1uF
C774
0.1uF
C776
0.1uF
C781
0.1uF
C784
0.1uF
C789
8,25,26 DDR1_CLK0
8,25,26 DDR1_CLK0N
0.1uF
C746
0.1uF
2
EVM_1V5
EVM_1V5
1
DDR1_CK0
R453
49.9
DDR1_CLK0N
R455
49.9
8,25,26 DDR1_RASN
8,25,26 DDR1_CKE
8,25,26 DDR1_CASN
8,25,26 DDR1_ODT0
DDR1_RASN
DDR1_CKE
DDR1_CASN
DDR1_ODT0
RN21
5
6
7
8
RPack4-47
4
3
2
1
8,25,26 DDR1_A10
8,25,26 DDR1_W EN
8,25,26 DDR1_CSN0
8,25,26 DDR1_BA2
DDR1_A10
DDR1_W EN
DDR1_CSN0
DDR1_BA2
RN23
5
6
7
8
RPack4-47
4
3
2
1
8,25,26 DDR1_BA1
8,25,26 DDR1_BA0
8,25,26 DDR1_A3
8,25,26 DDR1_A12
DDR1_BA1
DDR1_BA0
DDR1_A3
DDR1_A12
RN25
5
6
7
8
RPack4-47
4
3
2
1
8,25,26
8,25,26
8,25,26
8,25,26
DDR1_A0
DDR1_A5
DDR1_A4
DDR1_A2
DDR1_A0
DDR1_A5
DDR1_A4
DDR1_A2
RN27
5
6
7
8
RPack4-47
4
3
2
1
8,25,26
8,25,26
8,25,26
8,25,26
DDR1_A1
DDR1_A7
DDR1_A6
DDR1_A9
DDR1_A1
DDR1_A7
DDR1_A6
DDR1_A9
RN29
5
6
7
8
RPack4-47
4
3
2
1
DDR1_A11
DDR1_A8
DDR1_A13
DDR1_A14
RN31
5
6
7
8
RPack4-47
4
3
2
1
8,25,26 DDR1_A11
8,25,26 DDR1_A8
8,25,26 DDR1_A13
8,25,26 DDR1_A14
EVM_1V5
C716
0.1uF
C736
0.1uF
C749
0.1uF
C751
0.1uF
C756
0.1uF
C766
0.1uF
C771
0.1uF
D
C761
0.1uF
C775
0.1uF
C777
0.1uF
C782
0.1uF
C785
0.1uF
C786
0.1uF
C
EVM_1V5
EVM_1V5
EVM_DDR_VTT
B
B
EVM_DDR_VTT
EVM_DDR_VTT
EVM_DDR_VTT 49,53
EVM_1V5
EVM_1V5
A
7,8,16,17,21,23,25,27,49,52,53,55,56
SPECTRUM DIGITAL INCORPORATED
Title:
Page Contents:
EMIF DDR0 DDR3 MEM BANK1
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
24 o f
58
5
8,24,26 DDR1_A0
8,24,26 DDR1_A1
8,24,26 DDR1_A2
8,24,26 DDR1_A3
8,24,26 DDR1_A4
8,24,26 DDR1_A5
8,24,26 DDR1_A6
8,24,26 DDR1_A7
8,24,26 DDR1_A8
8,24,26 DDR1_A9
8,24,26
DDR1_A10
D
8,24,26 DDR1_A11
8,24,26 DDR1_A12
8,24,26 DDR1_A13
8,24,26 DDR1_A14
,24,26 DDR1_BA0
,24,26 DDR1_BA1
,24,26 DDR1_BA2
DDR1_A0
DDR1_A1
DDR1_A2
DDR1_A3
DDR1_A4
DDR1_A5
DDR1_A6
DDR1_A7
DDR1_A8
DDR1_A9
DDR1_A10
DDR1_A11
DDR1_A12
DDR1_A13
DDR1_A14
DDR1_BA0
DDR1_BA1
DDR1_BA2
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J2
K8
J3
4,26 DDR1_RASN
4,26 DDR1_CASN
24,26 DDR1_W EN
24,26 DDR1_ODT0
24,26 DDR1_CKE
4,26 DDR1_CSN0
DDR1_RASn
DDR1_CASn
DDR1_WEn
DDR1_ODT0
DDR1_CKE
DDR1_CE0n
F3
G3
H3
G1
G9
H2
24,26 DDR1_CLK0
,26 DDR1_CLK0N
DDR1_CK0 F7
DDR1_CK0n G7
8 DDR1_RST
DDR1_RESETn N2
EVM_DDR_REF_OUTJ8
C
R228
240
4
U47
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DM/TDQS
A9
TDQS
A10/AP
DQS
A11
DQS
A12/BC
A13
A14/NC VREFDQ
BA0
BA1
NC.1
BA2
NC.2
NC.3
RAS
NC.4
CAS
NC.5
WE
NC.6
ODT
CKE
CS
B3
C7
C2
C8
E3
E8
D2
E7
B7
A7
C3
D3
MEM10_D0
MEM10_D1
MEM10_D2
MEM10_D3
MEM10_D4
MEM10_D5
MEM10_D6
MEM10_D7
TDDR1_DM0
E1
EVM_DDR_REF_OUT
TDDR1_DQS0
TDDR1_DQSN0
A3
F1
F9
H1
H9
J7
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J2
K8
J3
DDR1_RASn
DDR1_CASn
DDR1_WEn
DDR1_ODT0
DDR1_CKE
DDR1_CE0n
F3
G3
H3
G1
G9
H2
DDR1_CK0 F7
DDR1_CK0n G7
CK
CK
DDR1_RESETn N2
RESET
EVM_DDR_REF_OUT
VREFCA
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSS.6
VSS.7
VSS.8
VSS.9
VSS.10
VSS.11
VSS.12
H8
ZQ
B2
B8
C9
D1
D9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
EVM_1V5
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDD.6
VDD.7
VDD.8
VDD.9
A2
A9
D7
G2
G8
K1
K9
M1
M9
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
B9
C1
E2
E9
R229
240
EDJ1108DBSE
B
8
8
8
8
DDR1_D3
DDR1_D1
DDR1_D2
DDR1_D4
8
8
8
8
DDR1_D7
DDR1_D0
DDR1_D6
DDR1_D5
8 DDR1_DQM0
8 DDR1_DQS0
8 DDR1_DQSN0
8 DDR1_D10
8 DDR1_D8
8 DDR1_D11
8 DDR1_D9
DDR1_D3
DDR1_D1
DDR1_D2
DDR1_D4
DDR1_D7
DDR1_D0
DDR1_D6
DDR1_D5
DDR1_DM0
DDR1_D15
DDR1_D14
DDR1_D12
DDR1_D13
8 DDR1_DQM1
8 DDR1_DQS1
8 DDR1_DQSN1
RN17
5
6
7
8
R208
DDR1_DQS0 R206
DDR1_DQSN0 R207
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DM/TDQS
A9
TDQS
A10/AP
DQS
A11
DQS
A12/BC
A13
A14/NC VREFDQ
BA0
BA1
NC.1
BA2
NC.2
NC.3
RAS
NC.4
CAS
NC.5
WE
NC.6
ODT
CKE
CS
B3
C7
C2
C8
E3
E8
D2
E7
B7
A7
C3
D3
MEM11_D0
MEM11_D1
MEM11_D2
MEM11_D3
MEM11_D4
MEM11_D5
MEM11_D6
MEM11_D7
TDDR1_DM1
E1
EVM_DDR_REF_OUT
TDDR1_DQS1
TDDR1_DQSN1
DDR1_RASn
DDR1_CASn
DDR1_WEn
DDR1_ODT0
DDR1_CKE
DDR1_CE0n
F3
G3
H3
G1
G9
H2
DDR1_RESETn N2
RESET
VREFCA
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSS.6
VSS.7
VSS.8
VSS.9
VSS.10
VSS.11
VSS.12
H8
ZQ
B2
B8
C9
D1
D9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
EVM_DDR_REF_OUT
EVM_1V5
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDD.6
VDD.7
VDD.8
VDD.9
A2
A9
D7
G2
G8
K1
K9
M1
M9
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
B9
C1
E2
E9
R230
240
RPack4-0
1
2
3
4
MEM10_D6
MEM10_D2
MEM10_D0
MEM10_D4
RPack4-0
MEM10_D7
4
MEM10_D1
3
MEM10_D5
2
MEM10_D3
1
0
0
0
8
8
8
8
DDR1_D23
DDR1_D20
DDR1_D22
DDR1_D21
8
8
8
8
DDR1_D19
DDR1_D17
DDR1_D18
DDR1_D16
8 DDR1_DQS2
8 DDR1_DQSN2
TDDR1_DQS0
TDDR1_DQSN0
DDR1_D28
DDR1_D30
DDR1_D24
DDR1_D27
DDR1_D15
DDR1_D14
DDR1_D12
DDR1_D13
RN19
5
6
7
8
RPack4-0
MEM11_D7
4
MEM11_D1
3
MEM11_D5
2
MEM11_D3
1
8
8
8
8
DDR1_D31
DDR1_D29
DDR1_D26
DDR1_D25
R211
0
DDR1_DQS1 R209
DDR1_DQSN1 R210
0
0
8 DDR1_DQM3
TDDR1_DM1
8 DDR1_DQS3
8 DDR1_DQSN3
TDDR1_DQS1
TDDR1_DQSN1
4
E1
EVM_DDR_REF_OUT
TDDR1_DQS2
TDDR1_DQSN2
A3
F1
F9
H1
H9
J7
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSS.6
VSS.7
VSS.8
VSS.9
VSS.10
VSS.11
VSS.12
H8
ZQ
B2
B8
C9
D1
D9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DDR1_A0
DDR1_A1
DDR1_A2
DDR1_A3
DDR1_A4
DDR1_A5
DDR1_A6
DDR1_A7
DDR1_A8
DDR1_A9
DDR1_A10
DDR1_A11
DDR1_A12
DDR1_A13
DDR1_A14
DDR1_BA0
DDR1_BA1
DDR1_BA2
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J2
K8
J3
DDR1_RASn
DDR1_CASn
DDR1_WEn
DDR1_ODT0
DDR1_CKE
DDR1_CE0n
F3
G3
H3
G1
G9
H2
DDR1_CK0 F7
DDR1_CK0n G7
DDR1_RESETn N2
RESET
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
DDR1_D23
DDR1_D20
DDR1_D22
DDR1_D21
RN10
8
7
6
5
RPack4-0
1
2
3
4
MEM12_D6
MEM12_D2
MEM12_D0
MEM12_D4
DDR1_D19
DDR1_D17
DDR1_D18
DDR1_D16
RN18
5
6
7
8
RPack4-0
4
3
2
1
MEM12_D7
MEM12_D1
MEM12_D5
MEM12_D3
DDR1_DM2
R214
DDR1_DQS2
DDR1_DQSN2
0
R212
R213
0
0
RN8
8
8
8
8
MEM12_D0
MEM12_D1
MEM12_D2
MEM12_D3
MEM12_D4
MEM12_D5
MEM12_D6
MEM12_D7
TDDR1_DM2
CK
CK
VREFCA
EVM_DDR_REF_OUT
EVM_1V5
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDD.6
VDD.7
VDD.8
VDD.9
A2
A9
D7
G2
G8
K1
K9
M1
M9
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
B9
C1
E2
E9
DDR1_D28
DDR1_D30
DDR1_D24
DDR1_D27
8
7
6
5
DDR1_D31
DDR1_D29
DDR1_D26
DDR1_D25
RN16
5
6
7
8
R223
240
DDR1_DM3
DDR1_DQS3
DDR1_DQSN3
R216
0
0
MEM13_D0
MEM13_D1
MEM13_D2
MEM13_D3
MEM13_D4
MEM13_D5
MEM13_D6
MEM13_D7
TDDR1_DM3
E1
EVM_DDR_REF_OUT
TDDR1_DQS3
TDDR1_DQSN3
D
A3
F1
F9
H1
H9
J7
CK
CK
RESET
VREFCA
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSS.6
VSS.7
VSS.8
VSS.9
VSS.10
VSS.11
VSS.12
H8
ZQ
B2
B8
C9
D1
D9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
EVM_1V5
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDD.6
VDD.7
VDD.8
VDD.9
A2
A9
D7
G2
G8
K1
K9
M1
M9
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
B9
C1
E2
E9
C
EDJ1108DBSE
B
EVM_1V5
EVM_1V5
7,8,16,17,21,23,24,27,49,52,53,55,56
TDDR1_DM2
EVM_DDR_REF_OUT
TDDR1_DQS2
TDDR1_DQSN2
EVM_DDR_REF_OUT 7,8,21,23,27,53
MEM13_D7
MEM13_D5
MEM13_D1
MEM13_D3
SPECTRUM DIGITAL INCORPORATED
A
NETRA EVM
Title:
Page Contents:
EMIF DDR1 DDR3 MEM BANK0
TDDR1_DQS3
TDDR1_DQSN3
Size:B
DWG NO
Date:
3
B3
C7
C2
C8
E3
E8
D2
E7
B7
A7
C3
D3
TDDR1_DM3
0
R448
R447
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DM/TDQS
A9
TDQS
A10/AP
DQS
A11
DQS
A12/BC
A13
A14/NC VREFDQ
BA0
BA1
NC.1
BA2
NC.2
NC.3
RAS
NC.4
CAS
NC.5
WE
NC.6
ODT
CKE
CS
J8
RPack4-0
MEM13_D6
1
MEM13_D2
2
MEM13_D0
3
MEM13_D4
4
RPack4-0
4
3
2
1
1
U48
B3
C7
C2
C8
E3
E8
D2
E7
B7
A7
C3
D3
EDJ1108DBSE
8 DDR1_DQM2
TDDR1_DM0
A0
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DM/TDQS
A9
TDQS
A10/AP
DQS
A11
DQS
A12/BC
A13
A14/NC VREFDQ
BA0
BA1
NC.1
BA2
NC.2
NC.3
RAS
NC.4
CAS
NC.5
WE
NC.6
ODT
CKE
CS
J8
EDJ1108DBSE
RPack4-0
MEM11_D6
1
MEM11_D2
2
MEM11_D0
3
MEM11_D4
4
5
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J2
K8
J3
DDR1_CK0 F7
DDR1_CK0n G7
RN6
8
7
6
5
DDR1_DM1
DDR1_A0
DDR1_A1
DDR1_A2
DDR1_A3
DDR1_A4
DDR1_A5
DDR1_A6
DDR1_A7
DDR1_A8
DDR1_A9
DDR1_A10
DDR1_A11
DDR1_A12
DDR1_A13
DDR1_A14
DDR1_BA0
DDR1_BA1
DDR1_BA2
CK
CK
J8
2
U54
A3
F1
F9
H1
H9
J7
DDR1_D10
DDR1_D8
DDR1_D11
DDR1_D9
A
8
8
8
8
RN9
8
7
6
5
3
U53
DDR1_A0
DDR1_A1
DDR1_A2
DDR1_A3
DDR1_A4
DDR1_A5
DDR1_A6
DDR1_A7
DDR1_A8
DDR1_A9
DDR1_A10
DDR1_A11
DDR1_A12
DDR1_A13
DDR1_A14
DDR1_BA0
DDR1_BA1
DDR1_BA2
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
25 o f
58
5
4
3
2
1
This section is an outline of vias labeled as Testpoints in the schematic. This allows us to determine pwb line lengths for memory to
memory and CPU to memory it is purely a visibility tool no actual "component" is used the vias are just replaced with a via that is
labeled a test point
DATA D24-D31 MEMORY
DATA D16-D23 MEMORY
DATA D8-D15 MEMORY
DATA D0-D7 MEMORY
D
D
8,24,25 DDR1_A0
DDR1_A0
8,24,25 DDR1_A1
DDR1_A1
8,24,25 DDR1_A2
1
TP2M15
1
TP2MB15
1
TP2MC15
1
TP2MD15
1
TP2M19
1
TP2MB19
1
TP2MC19
DDR1_A2
1
TP2M18
1
1
TP2MD19
TP2MB18
1
TP2MC18
1
8,24,25 DDR1_A3
DDR1_A3
1
TP2M13
TP2MD18
1
TP2MB13
1
TP2MC13
1
8,24,25 DDR1_A4
DDR1_A4
1
TP2MD13
TP2M17
1
TP2MB17
1
TP2MC17
1
8,24,25 DDR1_A5
DDR1_A5
TP2MD17
1
TP2M16
1
TP2MB16
1
TP2MC16
1
8,24,25 DDR1_A6
TP2MD16
DDR1_A6
1
TP2M21
1
TP2MB21
1
TP2MC21
1
TP2MD21
8,24,25 DDR1_A7
DDR1_A7
1
TP2M20
1
TP2MB20
1
TP2MC20
1
TP2MD20
8,24,25 DDR1_A8
DDR1_A8
1
TP2M24
1
TP2MB24
1
TP2MC24
1
TP2MD24
8,24,25 DDR1_A9
DDR1_A9
1
TP2M22
1
TP2MB22
1
TP2MC22
1
TP2MD22
8,24,25 DDR1_A10
DDR1_A10
1
TP2M7
1
TP2MB7
1
TP2MC7
1
TP2MD7
8,24,25 DDR1_A11
DDR1_A11
1
TP2M23
1
TP2MB23
1
TP2MC23
1
TP2MD23
8,24,25 DDR1_A12
DDR1_A12
1
TP2M14
1
TP2MB14
1
TP2MC14
1
TP2MD14
8,24,25 DDR1_A13
DDR1_A13
1
TP2M25
1
TP2MB25
1
TP2MC25
1
TP2MD25
8,24,25 DDR1_A14
DDR1_A14
1
TP2M26
1
TP2MB26
1
TP2MC26
1
TP2MD26
8,24,25 DDR1_BA0
DDR1_BA0
1
TP2M11
1
TP2MB11
1
TP2MC11
1
TP2MD11
8,24,25 DDR1_BA1
DDR1_BA1
1
TP2M12
1
TP2MB12
1
TP2MC12
1
TP2MD12
8,24,25 DDR1_BA2
DDR1_BA2
1
TP2M10
1
TP2MB10
1
TP2MC10
1
TP2MD10
8,24,25 DDR1_RASN
DDR1_RASn
1
TP2M2
1
TP2MB2
1
TP2MC2
1
TP2MD2
8,24,25 DDR1_CASN
DDR1_CASn
1
TP2M6
1
TP2MB6
1
TP2MC6
1
TP2MD6
8,24,25 DDR1_W EN
DDR1_WEn
1
TP2M8
1
TP2MB8
1
TP2MC8
1
TP2MD8
8,24,25 DDR1_ODT0
DDR1_ODT0
1
TP2M5
1
TP2MB5
1
TP2MC5
1
TP2MD5
8,24,25 DDR1_CKE
DDR1_CKE
1
TP2M4
1
TP2MB4
1
TP2MC4
1
TP2MD4
8,24,25 DDR1_CSN0
DDR1_CE0n
1
TP2M9
1
TP2MB9
1
TP2MC9
1
TP2MD9
8,24,25 DDR1_CLK0
DDR1_CK0
1
TP2M1
1
TP2MB1
1
TP2MC1
1
TP2MD1
DDR1_CK0n
1
TP2M3
1
TP2MB3
1
TP2MC3
1
TP2MD3
C
B
8,24,25 DDR1_CLK0N
C
B
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
DDR1 ADDRESS CONTROL TEST POINTS FOR ROUTING
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
26 o f
58
5
4
3
2
1
EVM_1V5
C249
0.1uF
C302
0.1uF
C319
0.1uF
EVM_1V5
7,8,16,17,21,23,24,25,49,52,53,55,56
C303
0.1uF
C327
0.1uF
C315
0.1uF
C281
0.1uF
C320
0.1uF
C314
0.1uF
D
D
EVM_1V5
C288
0.1uF
C289
0.1uF
C326
0.1uF
C283
0.1uF
C236
0.1uF
C360
0.1uF
C333
0.1uF
C239
0.1uF
C250
0.1uF
C290
0.1uF
C304
0.1uF
C240
0.1uF
C237
0.1uF
C282
0.1uF
C251
0.1uF
C270
0.1uF
C361
0.1uF
EVM_1V5
C
C358
0.1uF
C241
0.1uF
C268
0.1uF
C
EVM_DDR_REF_OUT
EVM_DDR_REF_OUT 7,8,21,23,25,53
EVM_1V5
EVM_1V5
EVM_DDR_REF_OUT
EVM_DDR_REF_OUT
C357
0.1uF
C727
0.1uF
C300
0.1uF
C219
0.1uF
C334
0.1uF
C297
0.1uF
C317
0.1uF
C738
0.1uF
C278
0.1uF
C363
0.1uF
EVM_1V5
C256
0.1uF
C258
0.1uF
C259
0.1uF
C273
0.1uF
C299
0.1uF
C335
0.1uF
C316
0.1uF
C344
0.1uF
C345
0.1uF
C346
0.1uF
C347
0.1uF
C265
0.1uF
C267
0.1uF
C269
0.1uF
C271
0.1uF
EVM_1V5
EVM_DDR_REF_OUT
EVM_DDR_REF_OUT
C734
0.1uF
C248
0.1uF
C266
0.1uF
C238
0.1uF
C298
0.1uF
C337
0.1uF
C291
0.1uF
C246
0.1uF
C332
0.1uF
C301
0.1uF
C338
0.1uF
C292
0.1uF
C247
0.1uF
C228
0.1uF
C754
0.1uF
C763
0.1uF
C226
0.1uF
EVM_1V5
B
EVM_1V5
EVM_1V5
C216
0.1uF
EVM_1V5
C222
0.1uF
C227
0.1uF
C318
0.1uF
C325
0.1uF
C235
0.1uF
C737
0.1uF
C366
0.1uF
C272
0.1uF
C359
0.1uF
EVM_1V5
C744
0.1uF
B
C729
0.1uF
C279
0.1uF
C340
0.1uF
C747
0.1uF
C780
0.1uF
C773
0.1uF
C356
0.1uF
C769
0.1uF
C215
0.1uF
EVM_1V5
C717
0.1uF
C364
0.1uF
C280
0.1uF
C365
0.1uF
C726
0.1uF
C257
0.1uF
C341
0.1uF
C313
0.1uF
C229
0.1uF
C217
0.1uF
C221
0.1uF
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
DDR MEMORY CAPS DDR1 INTERFACE
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
27 o f
58
5
4
3
2
1
EVM_3V3
EVM_5V0
EVM_12V
EVM_3V3
EVM_3V3
C710
0.1uF
R221
1K 1%
D
C758
5
SENSE1
VDD
6
4
CT
RESET
1
3
MR
GND
2
0.1uF
5
C707
.1uF
U44
R201
10K
1
32 PCI_SW_RESETn
4
2
4
2
U43
D
SN74LVC1G08DCKRG4
TPS3808G09DBVRG4
1
3
10K
0.1uF
3
R222
R220
10K
5
C752
U46
EVM_3V3
74CBTLV1G125CRG4
EVM_3V3
Reset Threhold 0.84 Volts
EVM_5V0
EVM_3V3
R195
10K
PCI_3V3
C725
U45
R218
1K
R219
1K 1%
C739
5
SENSE1
4
6
CT
RESET
1
3
MR
GND
2
0.1uF
R217
10K
0.1uF
VDD
R197
10K
SW5
1
2
OPT_SW1
OPT_SW2
4
3
OPT_SW2 14
SW DIP-2
OPT_SW1
OPT_SW2
TPS3808G09DBVRG4
PCI RESET MODE IN OR OUT
WDOG RESET ENABLED
C
C
Reset Threhold 0.84 Volts
EVM_3V3
EVM_3V3
PCI_3V3
EVM_12V
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
PCI_3V3
R440
10K
B
+12V.1
+12V.2
+12V.3
GND.1
SMCLK
SMDAT
GND.2
+3.3V.1
TRSTn
3.3VAUX
WAKEn
PRSNT1
+12V.4
+12V.5
GND.12
TCK
TDI
TDO
TMS
+3.3V.2
+3.3V.3
PERSTn
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
R456
10K
2
R451
10K
R443
10K
12 CON.PCIE_TXP1
12 CON.PCIE_TXN1
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
CON.PCIE_TXP0
CON.PCIE_TXN0
CON.PCIE_TXP1
CON.PCIE_TXN1
A
RSVD.1
GND.3
PETp0
PETn0
GND.4
PRSNT2
GND.5
PETp1
PETn1
GND.6
GND.7
PETp2
PETn2
GND.8
GND.9
PETp3
PETn3
GND.10
RSVD.2
PRSNT2.2
GND.11
GND.13
REFCLK+
REFCLKGND.14
PERp0
PERn0
GND.15
RSVD.3
GND.16
PERp1
PERn1
GND.17
GND.18
PERp2
PERn2
GND.19
GND.20
PERp3
PERn3
GND.21
RSVD.4
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
R203
NO-POP
.1uF
C210
PCI_CONN_REFP
.1uF
C209
PCI_CONN_REFN
REFCLKp
REFCLKn
CON.PCIE_RXP0
CON.PCIE_RXN0
CON.PCIE_RXP1
CON.PCIE_RXN1
PCI_3V3
PCI_3V3 29
SPECTRUM DIGITAL INCORPORATED
EVM_5V0 11,30,44,46,48,49,51,54,55,56
A
NETRA EVM
Title:
Connector must be less than 2.25 inches
to board edge from key to board edge
Page Contents:
PCIe INTERFACE
Size:B
DWG NO
EVM_12V
EVM_3V3 2,3,5,6,11,13,14,15,18,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
EVM_12V 29,44,46,48,51,52,56
4
PCI_CONN_REFN 13
CON.PCIE_RXP1 12
CON.PCIE_RXN1 12
EVM_5V0
5
B
PCI_CONN_REFP 13
CON.PCIE_RXP0 12
CON.PCIE_RXN0 12
PCIe 4X Connector
EVM_3V3
PCI_PORz 14
U41
74LV1G126CRG4
PCI_3V3
KEY
12 CON.PCIE_TXP0
12 CON.PCIE_TXN0
4
1
3
P8
R200
10K
C694
0.1uF
5
EVM_12V
3
2
Date:
Revision:
C
512872-0001
Thursday, April 28, 2011
Sheet
1
28 o f
58
5
4
3
2
1
CHECKED VALUES - COMPLETE
D
D
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
PCI_3V3
L15
1
R231
2
0.025
PCMB104T-3R3MS-(3.3uH)
C
1206
U56
EVM_12V
C377
10uF
C378
10uF
C353
10uF
C352
4.7uF
RT/CLK
2
GND.1
BOOT
13
3
GND.2
PH.2
12
4
PVIN.1
PH.1
11
5
PVIN.2
6
VIN
7
VSENSE
TPS54620
PWRGD
EN
C369
100uF
14
C376
R233
10.0K
10
SS/TR
9
COMP
8
C355
NO-POP
0.1uF
TP22
1
R234
3.16K
TEST POINT
R236
1.78K
C339
0.022uF
B
C
+
1
PWRPAD
100K
15
R239
C343
820pF
C342
0.018uF
B
TP21
1
TEST POINT
EVM_3V3
R476
0
EVM_12V
EVM_12V 28,44,46,48,51,52,56
SPECTRUM DIGITAL INCORPORATED
A
PCI_3V3
Title:
PCI_3V3 28
Page Contents:
POWER SUPPLY PCI3V3
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
29 o f
58
5
4
3
2
1
USB0_VBUS
EVM_5V0
U28
IN1
IN2
1
GND
BLM21PG221SN1
R412
100K
OCn
4
TPS2065D
L18
USB0_VBUS
8
7
6
OUT1
OUT2
OUT3
EN
+
C60
100uF
2
3
5
5 USB0_VBUS
D
D
+
5 USBB0_DRV_VBUS
USBB0_DRV_VBUS
C110
100uF
DIFFERENTIAL PAIR
90 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
R360
10K
HOST CONNECTOR
J13-1
SHIELD_USB0
MHX1
A1
A2
A3
A4
VBUS
DD+
GND
USB0_VBUS_CONN
USB0_DM
USB0_DP
USB0_DM
USB0_DP
C616
0.1uF
1
5 USB0_DM
5 USB0_DP
MH1
VCC
3
IO1
2
NC.2
IO2
MHX2
USB-A connector
L19
5
SHIELD_USB0
C
BLM21PG221SN1
4
GND
C
MH2
U65
EVM_5V0
IN1
IN2
1
GND
4
TPS2065D
L21
USB1_VBUS
8
7
6
BLM21PG221SN1
R437
100K
OCn
OUT1
OUT2
OUT3
EN
+
C152
100uF
U40
2
3
5
5 USB1_VBUS
TPD2E001DRL
USB1_VBUS
+
B
5 USBB1_DRV_VBUS
USBB1_DRV_VBUS
C218
100uF
R433
10K
HOST CONNECTOR
J13-2
SHIELD_USB1 MH3
USB1_VBUS_CONN
USB1_DM
USB1_DP
USB1_DM
USB1_DP
C588
0.1uF
1
5 USB1_DM
5 USB1_DP
IO1
2
NC.2
MH4
5
BLM21PG221SN1
SPECTRUM DIGITAL INCORPORATED
4
3
A
NETRA EVM
Title:
TPD2E001DRL
Page Contents:
USB INTERFACE CONNECTORS
Size:B
DWG NO
Date:
5
MHX2
USB-A connector
SHIELD_USB1
IO2
4
EVM_5V0 11,28,44,46,48,49,51,54,55,56
VBUS
DD+
GND
L20
VCC
3
MHX1
B1
B2
B3
B4
U64
GND
EVM_5V0
A
B
DIFFERENTIAL PAIR
90 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
30 o f
58
5
4
3
2
1
D
D
EVM_3V3
EVM_3V3
C469
.1uF
R59
NO-POP
R58
NO-POP
R57
NO-POP
R291
0
R292
0
R293
0
U12
I2C0_SCL
I2C0_SDA
3,32,41,48,50 IIC0_SCL
3,32,41,48,50 IIC0_SDA
C
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
VSS
1
2
3
4
CAT24C256WI-G
C
B
B
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
I2C EEPROMS
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
31 o f
58
5
4
3
2
1
EVM_3V3
EVM_3V3
EVM_3V3
C470
.1uF
R49
NO-POP
1
INT
3,31,41,48,50 IIC0_SDA
3,31,41,48,50 IIC0_SCL
23
22
SDA
SCL
33 UART2_OFF
34 IR_REMOTE_OFF
2 AIC_EXPANSION
28 PCI_SW_RESETn
20
19
18
17
16
15
14
13
P17
P16
P15
P14
P13
P12
P11
P10
24
A0
A1
A2
21
2
3
P0
P1
P2
P3
P4
P5
P6
P7
GND
4
5
6
7
8
9
10
11
12
R60
NO-POP
R61
NO-POP
D
RN2
RPACK4-10K
USER_SW1
USER_SW2
USER_SW3
USER_SW4
USER_LED1
USER_LED2
USER_LED3
USER_LED4
R290
10K
R295
10K
5
6
7
8
D
VDD
4
3
2
1
U13
R294
10K
SW2
USER_SW1
USER_SW2
USER_SW3
USER_SW4
1
2
3
4
RN1
8
7
6
5
5
6
7
8
LOW PROFILE DIP-4
SILKSCREEN:
USER SWITCHES
PCF8575
4
3
2
1
RPACK4-1K
EVM_3V3
C
C
R299
330
R298
330
R297
330
R296
330
DS2
LED_GRN
DS3
LED_GRN
DS4
LED_GRN
DS5
LED_GRN
USER_LED1
USER_LED2
USER_LED3
USER_LED4
EVM_3V3
EVM_3V3
C468
.1uF
R278
NO-POP
U9
B
1
INT
3,48 IIC1_SDA
3,48 IIC1_SCL
23
22
SDA
SCL
43 THS7375_DISABLE
43 THS7375_BYPASS
20
19
18
17
16
15
14
13
P17
P16
P15
P14
P13
P12
P11
P10
VDD
24
A0
A1
A2
21
2
3
P0
P1
P2
P3
P4
P5
P6
P7
GND
4
5
6
7
8
9
10
11
12
R277
NO-POP
R276
NO-POP
B
R282
10K
R281
10K
R280
10K
THS7360_FILTER2 42
PCF8575
THS7360_FILTER1 42
THS7360_BYP_SD 42
THS7360_BYP_SF 42
THS7360_DIS_SF 42
A
SPECTRUM DIGITAL INCORPORATED
A
THS7360_DIS_SD 42
NETRA EVM
Title:
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
Page Contents:
I2C EXPANDER
Size:B
DWG NO
Date:
5
4
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
32 o f
58
5
4
3
2
1
EVM_3V3
EVM_3V3
+
C792
1uF
C367
10uF
R238
10K
EVM_3V3
R240
10K
D
D
U57
3,47 UART2_TXD
3,46 UART2_RXD
FORCEOFF
16
FORCEON
12
T_OUT
13
UART2_TXD
11
UART2_RXD
9
R_OUT
1
EN
2
C1+
C2+
5
4
C1-
C2-
6
V+
3
V-
7
32 UART2_OFF
T_IN
R_IN
INVALID
DB9M
10
VCC
5
9
4
8
3
7
2
6
1
8
P10
10
11
15
R460
10K
C
C373
1uF
14
GND
MAX3221CPWRG4
C
C379
1uF
C794
1uF
C793
1uF
B
B
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
RS232 INTERFACE
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
33 o f
58
5
4
3
2
1
D
D
EVM_3V3
EVM_3V3
R474
10K
5
4
SN74LVC1G125
U60
C
U61
3
1
2
2
C
3
1
3,46 UART1_RXD
R473
100
C796
0.1uF
C386
10uF 6.3V
+
TSOP34840
IR_REMOTE_OFF 32
R245
10K
B
B
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
INFRA-RED RECIEVER
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
34 o f
58
5
4
3
2
1
C790
NO-POP
EVM_3V3
U66
D
3 MMC_POW
R459
51K
R458
51K
4
VIN
VOUT2
3
5
ON_OFF VOUT1
2
6
R1_C1
1
R2
FDC6331L
D
R457
0
R466
R462
51K
R464
51K
R467
51K
R469
51K
R470
51K
R461
51K
+
0
C787
10UF
SD/MMC Connector 6 in 1
MMC+, MMCMobile, SD,
MMC, miniSD, RS-MMC
C791
0.1uF
P9
C
MMC_DAT3
MMC_CMD
3 MMC_DAT3
3 MMC_CMD
MMC_CLK
3 MMC_CLK
MMC_DAT0
MMC_DAT1
MMC_DAT2
3 MMC_DAT0
3 MMC_DAT1
3 MMC_DAT2
R463
NO-POP
R465
NO-POP
R468
NO-POP
EVM_3V3
B
R471
10K
3 MMC_SD_WP
3 MMC_SD_CD
R472
10K
MMC_SD_WP
MMC_SD_CD
MHC-W21-601
1
2
3
4
5
6
7
8
9
10
11
12
13
#1_MMC+/MMCM/RSMMC/MMC/SD
#2_MMC+/MMCM/RSMMC/MMC/SD
#3_MMC+/MMCM/RSMMC/MMC/SD
#4_MMC+/MMCM/RSMMC/MMC/SD
#5_MMC+/MMCM/RSMMC/MMC/SD
#6_MMC+/MMCM/RSMMC/MMC/SD
#7_MMC+/MMCM/RSMMC/MMC/SD
#8_MMC+/MMCM/SD
#9_MMC+/MMCM/SD
#10_MMC+/MMCM
#11_MMC+/MMCM
#12_MMC+/MMCM
#13_MMC+/MMCM
16
17
18
19
20
21
22
23
24
25
26
27
28
#1_miniSD
#2_miniSD
#3_miniSD
#4_miniSD
#5_miniSD
#6_miniSD
#7_miniSD
#8_miniSD
#9_miniSD
#10_miniSD
#11_miniSD
GND1
GND2
14
15
SD_WP
CD
C
B
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
SD/MMC INTERFACE
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
35 o f
58
5
4
3
2
1
D
D
EVM_3V3
R345
10K
EVM_3V3
C509
U20
0.1uF
EVM_3V3
EVM_3V3
EVM_3V3
R344
10K
C511
.1uF
R348
10K
HOLD
SCLK
16
2
VCC
DIO
15
3
NC.3
NC.14
14
4
NC.4
NC.13
13
5
NC.5
NC.12
12
6
NC.6
NC.11
11
7
CS
GND
10
8
DO
WP
SPI_SCLK
SPI_MOSI
SPI_SCLK 3,46
SPI_MOSI 3,46
C
5
C
1
SPI_CS0
3,46 SPI_CS0
2
4
U21
3,46 SPI_MISO
SPI_MISO
R307
NO-POP
9
1
3
74CBTLV1G125CRG4
W25X32VSFIG
R306
10K
6 SPI_BOOTn
SPI_BOOTn
EVM_3V3
B
B
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
SPI EEPROM
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
36 o f
58
5
4
3
2
1
EVM_3V3
D
D
EVM_3V3
C527
.1uF
C517
.1uF
C522
.1uF
EVM_3V3
EVM_3V3
U24
C528
.1uF
5
GPMC_CS0
2
4
1
3
C
NAND_BOOTn
6,46 GPMC_WAIT
6,46 GPMC_OEN_REN
GPMC_WAIT
GPMC_OEN_REN
U25
74CBTLV1G125CRG4
6,46 GPMC_BE0N_CLE
6,46 GPMC_ADVN_ALE
6,46 GPMC_WEN
6,46 GPMC_WPN
GPMC_BE0N_CLE
GPMC_ADVN_ALE
GPMC_WEN
GPMC_WPN
NC-1
NC-2
NC-3
NC-4
NC-5
NC-6
R/B
RE
CE
NC-7
NC-8
VCC
GND1
NC-9
NC-10
CLE
ALE
WE
WP
NC-11
NC-12
NC-13
NC-14
NC-15
MH2
MH1
6 NAND_BOOTn
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MH2
MH1
EVM_3V3
6,46 GPMC_CS0
R359
10K
R358
10K
GND4
I/O15
I/O14
I/O13
I/O7
I/O6
I/O5
I/O4
I/O12
VCC4
23-NC
VCC3
GND3
22-NC
VCC2
I/O11
I/O3
I/O2
I/O1
I/O0
I/O10
I/O9
I/O8
GND2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GPMC_D15
GPMC_D14
GPMC_D13
GPMC_D7
GPMC_D6
GPMC_D5
GPMC_D4
GPMC_D12
GPMC_D15 6,46
GPMC_D14 6,46
GPMC_D13 6,46
GPMC_D7 6,46
GPMC_D6 6,46
GPMC_D5 6,46
GPMC_D4 6,46
GPMC_D12 6,46
C
GPMC_D11
GPMC_D3
GPMC_D2
GPMC_D1
GPMC_D0
GPMC_D10
GPMC_D9
GPMC_D8
GPMC_D11 6,46
GPMC_D3 6,46
GPMC_D2 6,46
GPMC_D1 6,46
GPMC_D0 6,46
GPMC_D10 6,46
GPMC_D9 6,46
GPMC_D8 6,46
ONFI
Micron NAND
B
B
EVM IS SUPPORTED WITH MICRON MT29F2G16AADWP:D
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
NAND FLASH
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
37 o f
58
5
4
3
2
1
U19A
GMII0_TCLK
GMII0_GMTCLK
GMII0_TXEN
4 GMII0_TCLK
4 GMII0_GMTCLK
4 GMII0_TXEN
D
4
4
4
4
4
4
4
4
R319
R314
R313
GMII0_TXD7
GMII0_TXD6
GMII0_TXD5
GMII0_TXD4
GMII0_TXD3
GMII0_TXD2
GMII0_TXD1
GMII0_TXD0
GMII0_TXD7
GMII0_TXD6
GMII0_TXD5
GMII0_TXD4
GMII0_TXD3
GMII0_TXD2
GMII0_TXD1
GMII0_TXD0
GMII0_RCLK
GMII0_RXDV
GMII0_RXER
4 GMII0_RCLK
4 GMII0_RXDV
4 GMII0_RXER
R324
R338
R333
RN11
4
4
4
4
4
4
4
4
C
PHY.MTCLK
PHY.GMTCLK
22
0
GMII0_RXD7
GMII0_RXD6
GMII0_RXD5
GMII0_RXD4
GMII0_RXD3
GMII0_RXD2
GMII0_RXD1
GMII0_RXD0
GMII0_RXD7
GMII0_RXD6
GMII0_RXD5
GMII0_RXD4
GMII0_RXD3
GMII0_RXD2
GMII0_RXD1
GMII0_RXD0
16
15
14
13
12
11
10
9
22
22
22
PHY.MRCLK
PHY.MRXDV
PHY.MRXER
10K
75
77
79
78
TXCLK
GTX_CLK/PMA_TX_CLK/TXC
TX_EN/TXD[8]/TX_CTL/TXD[4]
TX_ER/TXD[9]
57
SYS_CLK
3
2
1
84
83
82
81
80
TXD[7]
TXD[6]
TXD[5]
TXD[4]
TXD[3]
TXD[2]
TXD[1]
TXD[0]
72
69
70
RXCLK/PMA_RX_CLK[0]/RXC
RX_DV/RXD[8]/RX_CTL/RXD[4]
RX_ER/RX[9]
59
60
61
62
65
66
67
68
RXD[7]
RXD[6]
RXD[5]
RXD[4]
RXD[3]
RXD[2]
RXD[1]
RXD[0]
INPUTS
CLK_IN/XTAL1
22
XTAL2
23
TRD[0]P
TRD[0]N
TRD[1]P
TRD[1]N
TRD[2]P
TRD[2]N
TRD[3]P
TRD[3]N
25
26
28
29
34
35
37
38
LED_1000/SPEED_1000
49
LED_LNK/PAUSE
50
PRES
51
C476
18 pF
C477
18 pF
Y1
25MHz
TRD[0]P
TRD[0]N
TRD[1]P
TRD[1]N
TRD[2]P
TRD[2]N
TRD[3]P
TRD[3]N
40
40
40
40
40
40
40
40
D
RPACK8-22
PHY.MRXD7
PHY.MRXD6
PHY.MRXD5
PHY.MRXD4
PHY.MRXD3
PHY.MRXD2
PHY.MRXD1
PHY.MRXD0
1
2
3
4
5
6
7
8
OUTPUTS
ENET_LED_LINK 40
R334
C
1K 1%
GMII0_CRS
GMII0_COL
4 GMII0_CRS
4 GMII0_COL
4,48 MDIO_MDCLK
4,48 MDIO_MDIO
14 ENET_INTn
R325
R329
22
22
P HY.MCRS
PHY.MCOL
74
73
CRS/COMMA
COL/PMA_RX_CLK[1]
R354
R355
22
22
PHY.MDCLK
P HY.MDIO
55
54
53
MDC
MDIO
MDINTn
24
13,14,41,47 RSTOUTn
R477
10K
R478
10K
40
41
42
43
44
MAC_IF_SEL[2]
MAC_IF_SEL[1]
MAC_IF_SEL[0]
18
17
16
6.34K 1%
PHYA[4]
PHYA[3]
PHYA[2]
PHYAD[1]/LED_100
PHYAD[0]/LED_TXRX
EVM_3V3
TMS/SYS_CLK_ENn
TCK
TDO
TDI/LPED_ENn
TRSTz
EVM_3V3
R342
32
RESETn
R479
10K
EVM_3V3
B
R318
RSET
10K
13
5
15
14
12
R301
0
R302
0
R303
0
R310
10K
B
ET1011C
R343
R315
NO-POP
NO-POP
ENET_LED_RX 40
SPECTRUM DIGITAL INCORPORATED
A
EVM_3V3
Title:
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,39,40,41,42,43,44,46,48,49,50,51,53,54,55,56
Page Contents:
ETHERNET INTERFACE
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
38 o f
58
5
4
3
2
1
EVM_3V3
PHY_VDD_1V0
U19B
C485
0.1uF
C484
0.1uF
C500
0.1uF
C502
0.1uF
C508
0.1uF
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
DVDDIO.1
DVDDIO.2
DVDDIO.3
DVDDIO.4
DVDDIO.5
DVDDIO.6
4
52
58
64
71
76
7
8
9
10
11
NC.7
NC.8
NC.9
NC.10
NC.11
VDD_REG
45
CTRL_1V0
47
CTRL_2V5
46
PHY_AVDD_1V0
C501
0.1uF
C507
0.1uF
C498
0.1uF
C504
0.1uF
C482
0.1uF
C492
0.1uF
POWER_PAD
C499
0.1uF
85
C490
0.1uF
AVDDL.1
AVDDL.2
AVDDL.3
AVDDL.4
AVDDL.5
AVDDL.6
C493
0.1uF
C483
0.1uF
D
EVM_3V3
EVM_3V3
1
B
3
E
C519
0.1uF
2
4
U27
20
27
30
33
36
39
C506
0.1uF
C
TAB
D
6
19
48
56
63
C524
33uF
BCP69T1
PHY_VDD_2V5
PHY_AVDD_1V0
PHY_1V0
AVDDH.1
AVDDH.2
21
31
L9
BLM41P750SPT
ET1011C
C
C494
0.1uF
C518
0.1uF
C487
0.1uF
C523
33uF
C513
0.1uF
C512
33uF
C
PHY_VDD_1V0
L10
BLM41P750SPT
C479
0.1uF
C36
33uF
EVM_3V3
C521
0.1uF
B
1
B
E
2
4
U26
PHY_VDD_2V5 40
B
3
C
TAB
PHY_VDD_2V5
C526
33uF
PHY_VDD_2V5
PHY_2V5
L11
BCP69T1
BLM41P750SPT
C520
0.1uF
C525
33uF
C475
0.1uF
C32
33uF
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,40,41,42,43,44,46,48,49,50,51,53,54,55,56
A
SPECTRUM DIGITAL INCORPORATED
Title:
Page Contents:
ETHERNET - POWER
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
39 o f
58
5
4
3
2
1
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,41,42,43,44,46,48,49,50,51,53,54,55,56
D
PHY_VDD_2V5
D
PHY_VDD_2V5 39
PHY_VDD_2V5
J10
L16
TRD[0]P
38 TRD[0]P
2
VCC
9
T0+
1
10
7
T0T1+
2
3
8
T1-
6
5
T2+
4
6
3
T2T3+
5
7
4
T3-
TRD[0]N
38 TRD[0]N
TRD[1]P
38 TRD[1]P
TRD[1]N
38 TRD[1]N
TRD[2]P
38 TRD[2]P
TRD[2]N
38 TRD[2]N
C
TRD[3]P
38 TRD[3]P
C
TRD[3]N
R351
49.9 1%
R356
49.9 1%
R339
49.9 1%
C510
0.01uF
R346
49.9 1%
R330
49.9 1%
C505
0.01uF
R335
49.9 1%
C503
0.01uF
R320
49.9 1%
R326
49.9 1%
R321
GND
6605814_6
R357
75 75
75
SHLD2
LED2-AK
LED2-KA
75
12
D3
D4
1
0ohm 1/4W
C496
0.01uF
B
R492
NO-POP
38 ENET_LED_LINK
LED1-A
LED1-K
SHLD1
DIFFERENTIAL PAIR
100 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
8
D1
D2
11
38 TRD[3]N
B
BLM18AG601SN1
R493
0
EVM_3V3
221
EVM_3V3
5
C801
0.1uF
U68
SPECTRUM DIGITAL INCORPORATED
1
38 ENET_LED_RX
R347
4
NETRA EVM
Title:
74LVC1G08
Page Contents:
ETHERNET - OUTPUT CONNECTOR
Size:B
DWG NO
Date:
5
A
221
2
3
A
4
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
40 o f
58
EVM_3V3
EVM_3V3
L3
+
C12
.1uF
U3
C13
10uF
C9
1uF
Line In
3
L1
1
IN
2
GND
3
ENn
NC/FB
C457
.1uF
C10
5
OUT
C11
4.7uF
BLM21PG221SN1D
+
C456
.1uF
C458
.1uF
C3
.1uF
C2
10uF
.1uF
EVM_3V3
GND_AIC
4
L2
TPS77018DBVT
4
2
1
BLM21PG221SN1D
+
RF1 = ( Vout/Vref - 1) * RF2
RF1 = ( 1.8/1.224 - 1) * 169K
C8
.1uF
C6
10uF
C7
.1uF
C5
.1uF
DVDD.1
42
DVSS
44
IOVDD
P5
GND_AIC
R257
330
C455
.1uF
C443 .1uF
R255
NO-POP
C452
.1uF
GND_AIC
R258
2.2K
R259
0
GND_AIC
LINE1L-
5
LINE1R+
6
LINE1R-
7
LINE2L+
8
LINE2L-
9
LINE2R+
14
13,14,38,47 RSTOUTn
2 B_AIC_BCLK
2 B_AIC_WCLK
2 B_AIC_DIN
2 B_AIC_DOUT
B_AIC_BCLK
B_AIC_WCLK
B_AIC_DIN
B_AIC_DOUT
R22
R23
R24
R25
10
10
10
10
AIC_BCLK
AIC_WCLK
AIC_DIN
AIC_DOUT
MIC3L
MICDET
26
15
HPLOUT
HPLCOM
18
19
HPROUT
HPRCOM
23
22
RESET
38
39
40
41
BCLK
WCLK
DIN
DOUT
33uF,6.3V
C445
33uF,6.3V
Headphone Out
1
2
4
3
R254
20K
GND_AIC
R247
20K
MONO_LO+
MONO_LO-
27
28
LEFT_LO+
29
LEFT_LO-
30
RIGHT_LO+
31
RIGHT_LO-
32
GPIO1
GPIO2
35
34
MFP0
MFP1
MFP2
MFP3
45
46
47
48
MCLK
37
GND_AIC
SCART_AUDIO_OUT_R 43
1
1
TP3
TEST POINT
TP4
TEST POINT
SCART_AUDIO_OUT_L 43
P3
GND_AIC
R256
R248
100
C448
.047uF
1
2
4
100
C444
.047uF
3
R246
20K
GND_AIC
EVM_3V3
R253
20K
Line Out
GND_AIC
SDA
SCL
SELECT
R265
NO-POP
R266
NO-POP
R267
NO-POP
R16
NO-POP
R19
NO-POP
R18
NO-POP
R17
2K
R268
2K
49
EVM_3V3
R271
20K
AVSS_DAC
AVSS_ADC
MICBIAS
33
43
25
MIC3R
12
2
1
3,31,32,48,50 IIC0_SDA
3,31,32,48,50 IIC0_SCL
AVDD_DAC
P2
GND_AIC
C451
GND_AIC
LINE2R-
11
13
20
21
LINE1L+
4
10
DRVSS.1
DRVSS.2
GND_AIC
GND_AIC
C450 .1uF
3
DRVDD.1
DRVDD.2
DRVDD.3
6
5
36
16
17
24
+
4
2
1
C449
NO-POP
TLV320AIC3106
+
U2
Mic In GND_AIC
3
TPAD
5
6
P4
6
5
5
6
C15
.1uF
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,42,43,44,46,48,49,50,51,53,54,55,56
EVM_3V3
BLM21PG221SN1D
R270
20K
R26
NO-POP
EVM_3V3
C14
U6
R269
2K
.1uF
1
EN
VCC
4
2
GND
OUT
3
24.576 MHz
2 B_AIC_MCLK
R29
R21
22
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
SPECTRUM DIGITAL INCORPORATED
NETRA EVM
Title:
Page Contents:
AIC3106 AUDIO INTERFACE
Size:B
DWG NO
22
Revision:
A
512872-0001
GND_AIC
Date:
Thursday, April 28, 2011
Sheet
41 o f
58
5
4
3
2
1
J4
C1
330uF
1
5
4
3
2
75
R275
9
R41
IOUTD
0
F TYPE
5-1814400-1
101515-0001R
ALT_IOUTD 43
R264
0
S-VIDEO_LUMA
R288
COMPOSITE
749181-1
P1
3
4
1
2
D
37.4
R274
R42
IOUTE
SCART_COMPOSITE 43
0
D
9
COMPOSITE
4
1
3
R6
RFOUT
+
J3
9
RCA JACK
2
0
5
ALT_IOUTE 43
7
6
EVM_3V3
0
R287
37.4
S-VIDEO Y
C459
0.1uF
C460
0.01uF
J2
C461
1uF
R
1
11
6
2
12
7
3
13
8
4
14
9
5
15
10
G
R273
C
9
R43
IOUTF
U4
0
ALT_IOUTF 43
0
R286
37.4
S-VIDEO C
32 THS7360_FILTER2
32 THS7360_FILTER1
R44
IOUTA
0
37.4
B
20
R7
75
75
75
B
2
SD2_IN
SD2_OUT
19
R8
3
SD3_IN
SD3_OUT
18
R9
4
FILTER2
DIS_SD
17
5
VS+
GND
16
6
FILTER1
DIS_SF
15
C
HD15
7
SF1_IN
SF1_OUT
14
8
SF2_IN
SF2_OUT
13
9
SF3_IN
SF3_OUT
12
10
R45
R10
75
R263
75
R11
75
J5
RCA JACK(GREEN)
2
BYP_SD
BYP_SF
11
R262
B
J6
RCA JACK(BLUE)
2
75
0
4
1
3
IOUOTB
SD1_OUT
R285
G/Y
9
SD1_IN
4
1
3
9
1
R
NC.11
Gnd.6
G
NC.12
Gnd.7
B
H_Sync
Gnd.8
NC.4
V_Sync
NC.9
Gnd.5
NC.15
Gnd.10
B/Pb
R46
IOUTC
R/Pr
R12
75
R261
75
J7
RCA JACK(RED)
2
0
4
1
3
9
THS7360
R284
37.4
R283
37.4
JACK ORDER MUST BE RED,BLUE, GREEN FOR COMPONENT CABLING
SPECTRUM DIGITAL INCORPORATED
A
A
32 THS7360_BYP_SD
Title:
32 THS7360_BYP_SF
32 THS7360_DIS_SF
EVM_3V3
32 THS7360_DIS_SD
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,43,44,46,48,49,50,51,53,54,55,56
5
NETRA EVM
4
Page Contents:
ANALOG VIDEO OUT
Size:B
DWG NO
Date:
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
42 o f
58
5
4
3
2
1
J9
41 SCART_AUDIO_OUT_R
1
AUDIO_OUT(R)
41 SCART_AUDIO_OUT_L
3
AUDIO_OUT(L/MONO)
5
BLUE_GND
7
BLUE_UP
9
GRN_GND
AUDIO_IN(R)
D
U8
42 ALT_IOUTD
ALT_IOUTE
42 ALT_IOUTE
42 ALT_IOUTF
9
IOUTG
SCART_GRN
ALT_IOUTD
ALT_IOUTF
IOUTG
R38
SCART_BLUE
SCART_RED/SVIDEO_C
0
CH1_IN
CH1_OUT
14
2
CH2_IN
CH2_OUT
13
R33
75
3
CH3_IN
CH3_OUT
12
R31
75
4
R272
37.4
C
1
R39
CH4_IN
CH4_OUT
5
GND
6
DISABLE
7
NC.7
VS+
11
R28
75
BYPASS
9
NC.8
8
AUDIO_GND
4
AUDIO_IN(L/MONO)
6
STATUS
8
75
EVM_3V3
10
C464
0.1uF
C463
0.01uF
C465
1uF
CLK/DATA
10
RESV
12
GND_12_16
14
SEL_RGB_COMPOSITE
16
11
GRN_UP
13
RED_GND
15
RED_UP
17
CV_GND_19_20
BLNK_GND_16
COMPOSITE_VIDEO_OUT
18
19
COMPOSITE_VIDEO_IN
GND_8_10
20
21
THS7375
42 SCART_COMPOSITE
2
D
C
SCART21
B
B
32 THS7375_DISABLE
32 THS7375_BYPASS
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,44,46,48,49,50,51,53,54,55,56
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
ANALOG VIDEO OUT SCART
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
43 o f
58
5
4
3
2
1
J17
D
10
VIN0_D0
VIN0_D0
10
10
VIN0_D2
VIN0_D9
VIN0_D2
VIN0_D9
10 VOUT_YC2
10 VOUT_YC6
VOUT0_G_Y_YC2
VOUT0_G_Y_YC6
10 VOUT_CR4
10 VIN0_D6
VOUT0_R_CR4
VIN0_D6
10
10
EVM_12V
C
B
VIN0_D8
VIN0_D3
VIN0_D8
VIN0_D3
10 VIN0_D7
10 VOUT_YC4
VIN0_D7
VOUT0_G_Y_YC4
10 VOUT_C8
10 VOUT_YC5
VOUT0_B_CB_C8
VOUT0_G_Y_YC5
10 VOUT_C6
10 VOUT_C5
VOUT0_B_CB_C6
VOUT0_B_CB_C5
10 VOUT_C3
VOUT0_B_CB_C3
10 VOUT_C7
VOUT0_B_CB_C7
10 VOUT_YC3
10 VOUT_YC9
VOUT0_G_Y_YC3
VOUT0_G_Y_YC9
10 VIN0_CLK0
10 VOUT_C4
VIN0_CLK0
VOUT0_B_CB_C4
10 VOUT_C2
10 VOUT_CR3
VOUT0_B_CB_C2
VOUT0_R_CR3
10 TSI5_DATA
10 TSI5_PACVAL
TSI5_DATA
TSI5_PACVAL
10 TSI1_PACVAL
10 TSI7_DATA
TSI1_PACVAL
TSI7_DATA
10 TSI5_DCLK
10 VOUT_CR7
TSI5_DCLK
VOUT0_R_CR7
10 VOUT_CR8
10 TSI7_BYTSTRT
VOUT0_R_CR8
TSI7_BYTSTRT
10 TSI1_BYTSTRT
10 TSI7_DCLK
TSI1_BYTSTRT
TSI7_DCLK
10 TSI1_DCLK
10 TSI1_DATA
10 TSO1_BYTSTRT
TSI1_DCLK
TSI1_DATA
TSO1_BYTSTRT
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
122
124
126
128
G2
G4
G6
G8
G1
G3
G5
G7
121
123
125
127
VIN0_CLK1
VIN0_CLK1 10
VIN0_D1
VIN0_D4
VIN0_D1
VIN0_D4
VIN0_D11
VIN0_D5
VIN0_D11 10
VIN0_D5 10
VIN0_D12
VIN0_D10
VIN0_D12 10
VIN0_D10 10
VIN0_D14
VIN0_D13
VIN0_D14 10
VIN0_D13 10
VIN0_D15
VOUT0_CLK
VIN0_D15 10
VOUT0_CLK 10
VOUT0_G_Y_YC8
VOUT0_G_Y_YC7
VOUT_YC8 10 EVM_3V3
VOUT_YC7 10
10
10
D
EVM_5V0
EVM_5V0 11,28,30,46,48,49,51,54,55,56
EVM_5V0
EVM_12V
VOUT0_B_CB_C9
VOUT_C9 10
VOUT0_R_CR2
VOUT_CR2 10
VOUT0_R_CR6
VOUT0_R_CR5
VOUT_CR6 10
VOUT_CR5 10
VOUT0_R_CR9
TSI5_BYTSTRT
VOUT_CR9 10
TSI5_BYTSTRT 10
TSI5_PACERR
TSI7_PACERR
TSI5_PACERR 10
TSI7_PACERR 10
TSO1_DATA
TSI7_PACVAL
TSO1_DATA 10
TSI7_PACVAL 10
TSO1_PACVAL
TSO1_DCLK
TSO1_PACVAL 10
TSO1_DCLK 10
TSI6_DATA
TSI3_BYTSTRT
TSI6_DATA 10
TSI3_BYTSTRT 10
TSI2_BYTSTRT
TSI4_DATA
TSI2_BYTSTRT 10
TSI4_DATA 10
TSI0_DATA
TSI6_DCLK
TSI0_DATA 10
TSI6_DCLK 10
MSP430_SCL
MSP430_SDA
EVM_12V 28,29,46,48,51,52,56
C
B
PM_I2C_SCL 46,48,49,50
PM_I2C_SDA 46,48,49,50
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,46,48,49,50,51,53,54,55,56
QSH-060-01-x-D-A
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
VIDEO/TRANSPORT STREAMS
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
44 o f
58
5
4
3
2
1
D
D
J16
10 TSI3_PACVAL
10 TSI4_DCLK
10 TSI3_DATA
TSI4_DCLK
TSI3_DATA
10 TSI2_DCLK
10 TSI2_DATA
TSI2_DCLK
TSI2_DATA
10 TSI6_BYTSTRT
10 TSI6_PACVAL
TSI6_BYTSTRT
TSI6_PACVAL
10 TSI4_PACERR
10 TSI4_BYTSTRT
TSI4_PACERR
TSI4_BYTSTRT
10 TSI3_PACERR
6 VLYNQ_RXD1
TSI3_PACERR
VLYNQ_RXD1
6 VLYNQ_TXD1
10 TSO1_PACERR
C
TSI3_PACVAL
6 VLYNQ_TXD3
6 VLYNQ_RXD2
10 TSI4_PACVAL
6 VLYNQ_RXD3
6 VLYNQ_TXD0
VLYNQ_TXD1
TSO1_PACERR
VLYNQ_TXD3
VLYNQ_RXD2
TSI4_PACVAL
VLYNQ_RXD3
VLYNQ_TXD0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
62
64
G2
G4
G1
G3
61
63
TSI6_PACERR
TSI6_PACERR 10
TSI2_PACERR
TSI0_PACVAL
TSI2_PACERR 10
TSI0_PACVAL 10
TSI2_PACVAL
TSI0_PACERR
TSI2_PACVAL 10
TSI0_PACERR 10
TSI0_DCLK
TSO0_DCLK
TSI0_DCLK 10
TSO0_DCLK 10
TSI0_BYTSTRT
TSO0_DATA
TSI0_BYTSTRT 10
TSO0_DATA 10
TSO0_BYTSTRT
TSO0_PACERR
TSO0_BYTSTRT 10
TSO0_PACERR 10
VLYNQ_SCRUN
TSO0_PACVAL
VLYNQ_SCRUN 6
TSO0_PACVAL 10
VLYNQ_TXD2
VLYNQ_CLOCK
VLYNQ_TXD2 6
VLYNQ_CLOCK 6
TSI1_PACERR
TSI3_DCLK
TSI1_PACERR 10
TSI3_DCLK 10
VLYNQ_RXD0
C
VLYNQ_RXD0 6
QSH-030-01-x-D-A
B
B
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
VLYNQ/TRANSPORT STREAMS
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
45 o f
58
5
4
3
2
1
J18
44,48,49,50 PM_I2C_SCL
MSP430_SCL
44,48,49,50 PM_I2C_SDA
MSP430_SDA
D
6 GPMC_CS4
6 GPMC_A8
6
6
6
6
GPMC_A7
GPMC_A3
GPMC_A2
GPMC_A1
6 GPMC_A0
6 GPMC_DIR
EVM_12V
6,37 GPMC_WAIT
6,37 GPMC_WPN
C
6
GPMC_A6
6,37 GPMC_BE0N_CLE
6,37 GPMC_D4
6,37 GPMC_D3
6,37 GPMC_D1
6 GPMC_A27
6,37 GPMC_ADVN_ALE
6,37 GPMC_D6
6,37 GPMC_D8
6,37 GPMC_D13
B
6,37 GPMC_D14
GPMC_CS4
GPMC_A8
GPMC_A7
GPMC_A3
GPMC_A2
GPMC_A1
GPMC_A0
GPMC_DIR
GPMC_WAIT
GPMC_WPN
GPMC_A6
GPMC_BE0N_CLE
GPMC_D4
GPMC_D3
GPMC_D1
GPMC_A27
GPMC_ADVN_ALE
GPMC_D6
GPMC_D8
GPMC_D13
GPMC_D14
3,36 SPI_MOSI
3,36 SPI_MISO
3 UART0_RXD
3 UART0_RTSN
3 UART0_TXD
UART0_RXD
UART0_RTSN
UART0_TXD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
122
124
126
128
G2
G4
G6
G8
G1
G3
G5
G7
121
123
125
127
GPMC_CS3
GPMC_CS0
GPMC_CS2
GPMC_CS1
GPMC_WEN
GPMC_CS5
GPMC_OEN_REN
GPMC_BE1N
GPMC_A5
GPMC_A4
GPMC_A9
GPMC_A10
GPMC_A11
GPMC_D0
GPMC_CS3 6
GPMC_CS0 6,37
D
GPMC_CS2 6
GPMC_CS1 6
GPMC_WEN 6,37
GPMC_CS5 6
GPMC_OEN_REN 6,37
GPMC_BE1N 6
GPMC_A5 6
GPMC_A4 6
GPMC_A9 6
GPMC_A10 6
GPMC_A11 6
GPMC_D0 6,37
EVM_3V3
EVM_5V0
GPMC_D2
GPMC_D5
GPMC_D7
GPMC_D9
GPMC_D12
GPMC_D11
GPMC_D10
GPMC_CLK
GPMC_D15
SPI_CS0
SPI_SCLK
SPI_CS3
SPI_CS1
UART1_RXD
UART1_TXD
UART2_RXD
C
GPMC_D2 6,37
GPMC_D5 6,37
GPMC_D7 6,37
GPMC_D9 6,37
GPMC_D12 6,37
GPMC_D11 6,37
GPMC_D10 6,37
GPMC_CLK 6
GPMC_D15 6,37
B
SPI_CS0 3,36
SPI_SCLK 3,36
SPI_CS3 3
SPI_CS1 3
UART1_RXD 3,34
UART1_TXD 3
UART2_RXD 3,33
EVM_5V0
QSH-060-01-x-D-A
EVM_5V0 11,28,30,44,48,49,51,54,55,56
EVM_3V3
A
SPECTRUM DIGITAL INCORPORATED
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,48,49,50,51,53,54,55,56
A
NETRA EVM
Title:
Page Contents:
GPMC EXPANSION CONNECTOR
Size:B
DWG NO
EVM_12V
EVM_12V 28,29,44,48,51,52,56
5
4
3
Date:
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
46 o f
58
5
4
3
2
1
D
D
J20
3 UART0_CTSN
3 UART0_DTRN
3 UART0_DCDN
3 UART0_DSRN
3 UART0_RIN
3 SPI_CS2
3 UART1_CTSN
3 SC0_VPPEN
3 SC0_VCCEN
3
3
SC1_CLK
SC0_C4
3 UART2_RTSN
3 UART2_CTSN
C
3
SC0_DET
13,14,38,41 RSTOUTn
3
3
SC0_CLK
SC1_C4
UART0_CTSN
UART0_DTRN
UART0_DCDN
UART0_DSRN
UART0_RIN
SPI_SCS2
UART1_CTSN
SC0_VPPEN
SC0_VCCEN
SC1_CLK
SC0_C4
UART2_RTSN
UART2_CTSN
SC0_DET
SC0_CLK
SC1_C4
3 SC0_DATA
3 SC1_DATA
SC0_DATA
SC1_DATA
14
GP0_IO6
GP0_IO6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
62
64
G2
G4
G1
G3
61
63
UART1_RTSN
UART1_RTSN 3
UART2_TXD
SC0_RST
UART2_TXD 3,33
SC0_RST 3
SC1_RST
SC1_DET
SC1_RST
SC1_DET
TIM6_OUT
SC1_VPPEN
TIM6_OUT 3
SC1_VPPEN 3
TIM7_OUT
SC1_VCCEN
TIM7_OUT 3
SC1_VCCEN 3
CLKOUT
GP0_IO5
CLKOUT 3
GP0_IO5 14
TIM4_OUT
3
3
TIM4_OUT 3
C
GP0_IO7
GP0_IO7
GP0_IO4
EXP_WARM_RESET
GP0_IO4 14
EXP_WARM_RESET 14
TIM5_OUT
14
TIM5_OUT 3
QSH-030-01-x-D-A
B
B
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
SERIAL I/O EXPANSION CONNECTOR
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
47 o f
58
5
4
3
2
1
J19
D
3,32 IIC1_SDA
IIC1_SDA
3,32 IIC1_SCL
3,31,32,41,50 IIC0_SDA
IIC1_SCL
IIC0_SDA
3,31,32,41,50 IIC0_SCL
IIC0_SCL
2 MCA0_AMUTE
2 MCA0_AXR3
MCA0_AMUTE
MCA0_AXR3
2 MCA0_AXR2
2 MCA1_AMUTE
MCA0_AXR2
MCA1_AMUTE
2 MCA0_AHCLKX
2 MCA0_AFSR
MCA0_ACLKHX
MCA0_AFSR
2 MCA0_ACLKX
2 MCA0_AFSX
EVM_12V 2 MCA1_AFSX
2 MCA0_AXR1
MCA0_ACLKX
MCA0_AFSX
MCA1_AFSX
MCA0_AXR1
C
2 MTSI_DATA7
MTSI_DATA7
2 MCA0_AXR5
MCA0_AXR5
2 MCA0_AXR4
2 MCA0_AXR0
MCA0_AXR4
MCA0_AXR0
2 MCA1_ACLKR
2 MCA1_AHCLKR
MCA1_ACLKR
MCA1_AHCLKR
2 MCA1_AFSR
2 MTSO_DATA0
MCA1_AFSR
MTSO_DATA0
2 MTSO_DATA6
2 MCTL_SDI
MTSO_DATA6
MCTL_SDI
2 MTSO_DATA7
2 MCARD_MDET
MTSO_DATA7
MCARD_MDET
B
2 MCTL_SCTL
2 MCARD_CD2
MCTL_SCTL
MCARD_CD2
2 MCARD_CD1
2 MCA0_ACLKR
MCARD_CD1
MCA0_ACLKR
2 MCA0_AHCLKR
2 MCARD_VS1
MCA0_AHCLKR
MCARD_VS1
2 MCTL_SDO
2 MCARD_VCCEN
MCTL_SDO
MCARD_VCCEN
2 MCARD_VS2
MCARD_VS2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
PM_I2C_SCL
PM_I2C_SCL 44,46,49,50
PM_I2C_SDA
EXP_MCA2_AXR0
PM_I2C_SDA 44,46,49,50
EXP_MCA2_AXR0 2
EXP_MCA2_AMUTE
EXP_MCA2_AXR1
EXP_MCA2_AMUTE 2
EXP_MCA2_AXR1 2
EXP_MCA2_ACLKHX
EXP_MCA2_ACLKX
EXP_MCA2_ACLKHX 2
EXP_MCA2_ACLKX 2
EXP_MCA2_AFSR
EXP_MCA2_AFSX
EXP_MCA2_AFSR 2
EXP_MCA2_AFSX 2
EXP_MCA2_AHCLKR
EXP_MCA2_ACLKR
EXP_MCA2_AHCLKR 2
EXP_MCA2_ACLKR 2
MCA1_AXR1
MCA1_AXR0
MCA1_AXR1 2
MCA1_AXR0 2
MTSO_DATA1
MTSI_DATA5
MTSO_DATA1 2
MTSI_DATA5 2
MCA1_ACLKHX
MCA1_AHCLKX 2
MDIO_MDIO
MDIO_MDIO 4,38
MDIO_MDCLK
MCA1_ACLKX
MDIO_MDCLK 4,38
MCA1_ACLKX 2
MTSI_DCLK
MTSI_DATA0
MTSI_DCLK 2
MTSI_DATA0 2
MTSI_DATA2
MTSI_DATA1
MTSI_DATA2 2
MTSI_DATA1 2
MTSI_DATA4
MTSI_DATA3
MTSI_DATA4 2
MTSI_DATA3 2
MTSI_DATA6
MTSI_BYTSTRT
MTSI_DATA6 2
MTSI_BYTSTRT 2
MTSO_DCLK
MTSO_DATA2
MTSO_DCLK 2
MTSO_DATA2 2
MTSO_DATA3
MTSO_DATA5
MTSO_DATA3 2
MTSO_DATA5 2
MTSO_DATA4
MCTL_SCLK
MTSO_DATA4 2
MCTL_SCLK 2
MTSO_BYTSTRT
MCARD_VPPEN
MTSO_BYTSTRT 2
MCARD_VPPEN 2
MCARD_RESET
MCARD_RESET 2
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
122
124
126
128
G2
G4
G6
G8
G1
G3
G5
G7
121
123
125
127
EVM_5V0
EVM_5V0 11,28,30,44,46,49,51,54,55,56
EVM_12V
EVM_12V 28,29,44,46,51,52,56
EVM_3V3
EVM_5V0
C
B
QSH-060-01-x-D-A
A
SPECTRUM DIGITAL INCORPORATED
EVM_3V3
Page Contents:
MCASP/XXX EXPANSION
Size:B
DWG NO
Date:
4
3
2
A
NETRA EVM
Title:
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,49,50,51,53,54,55,56
5
D
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
48 o f
58
5
4
3
2
1
EVM_3V3
EVM_3V3
ADDRESS 1000100
ADDRESS 1000000
U14
55 I_MON_0V9_HIGH
10
VIN+
EVM_0V9
D
SCL
SDA
5
4
9
VIN-
NC.3
A0
A1
3
2
1
8
VBUS GND
7
U22
C471
0.1uF
6
VS
51 I_MON_3V3_HIGH
PM_I2C_SCL
PM_I2C_SDA
9
VIN-
NC.3
A0
A1
3
2
1
8
VBUS GND
7
VS
6
SCL
SDA
5
4
VIN+
EVM_1V8_A
9
VIN-
NC.3
A0
A1
3
2
1
8
VBUS GND
7
24,53 EVM_DDR_VTT
EVM_0V9
6
SCL
SDA
5
4
VIN+
10
SCL
SDA
5
4
NC.3
A0
A1
3
2
1
8
VBUS GND
7
10
C480
0.1uF
PM_I2C_SCL
PM_I2C_SDA
EVM_3V3
EVM_3V3
VS
6
SCL
SDA
5
4
VIN+
EVM_1V5
9
VIN-
NC.3
A0
A1
3
2
1
8
VBUS GND
7
C
C704
0.1uF
PM_I2C_SCL
PM_I2C_SDA
EVM_3V3
EVM_3V3
INA220IDCN
ADDRESS 1000111
U23
C795
0.1uF
PM_I2C_SCL
PM_I2C_SDA
54 I_MON_1V0_AVS_HIGH
10
VS
6
SCL
SDA
5
4
VIN+
EVM_1V0_AVS
C516
0.1uF
PM_I2C_SCL
PM_I2C_SDA
B
9
VIN-
NC.3
A0
A1
3
2
1
9
VIN-
NC.3
A0
A1
3
2
1
8
VBUS GND
7
8
VBUS GND
7
EVM_3V3
EVM_3V3
INA220IDCN
5,55
ADDRESS 1001000
EVM_1V8_A
U18
EVM_1V0_CON
EVM_1V8_A 9,55
51 I_MON_1V0_CONN_HIGH
EVM_1V8_D
10
EVM_1V0_CON 9,11,15,16,17,20,51,55
EVM_1V8_D 5,15,16,52,55
6
VIN-
INA220IDCN
EVM_0V9
VS
VIN+
9
EVM_3V3
VS
EVM_3V3
U42
52 I_MON_1V5_HIGH
PM_I2C_SCL
PM_I2C_SDA
U59
B
7
INA220IDCN
ADDRESS 1000011
10
VBUS GND
C466
0.1uF
INA220IDCN
53 I_MON_VTT_HIGH
8
D
EVM_3V3
ADDRESS 1000110
U7
10
3
2
1
EVM_3V3
ADDRESS 1000010
55 I_MON_1V8ANALOG_HIGH
NC.3
A0
A1
EVM_5V0
EVM_3V3
INA220IDCN
C
VIN-
PM_I2C_SCL
PM_I2C_SDA
U17
51 I_MON_5V0_HIGH
PM_I2C_SCL
PM_I2C_SDA
5
4
SCL
SDA
EVM_1V8_D
5
4
9
C467
0.1uF
6
VIN+
SCL
SDA
C514
0.1uF
ADDRESS 1000101
U11
55 I_MON_1V8DIGITAL_HIGH
6
INA220IDCN
ADDRESS 1000001
VS
VS
VIN+
EVM_3V3
EVM_3V3
INA220IDCN
10
10
EVM_1V0_CON
EVM_1V0_AVS
EVM_1V0_AVS 18,20,54
EVM_1V5
6
SCL
SDA
5
4
9
VIN-
NC.3
A0
A1
3
2
1
8
VBUS GND
7
EVM_DDR_VTT
EVM_DDR_VTT 24,53
VS
VIN+
C495
0.1uF
PM_I2C_SCL
PM_I2C_SDA
PM_I2C_SCL 44,46,48,50
PM_I2C_SDA 44,46,48,50
INA220IDCN
A
EVM_1V5
SPECTRUM DIGITAL INCORPORATED
A
7,8,16,17,21,23,24,25,27,52,53,55,56
EVM_5V0
NETRA EVM
Title:
EVM_5V0 11,28,30,44,46,48,51,54,55,56
Page Contents:
POWER MONITOR
Size:B
DWG NO
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,50,51,53,54,55,56
5
4
3
Date:
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
49 o f
58
5
4
3
EVM_3V3
2
1
EVM_3V3
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,51,53,54,55,56
R426
47K
HEADER 7X2
430_TDO/TDI
D
R186
330
C607
EVM_3V3
1
3
5
7
9
11
13
TDO/TDI
TDI/VPP
TMS
TCK
GND
RST/NMI
NC1
0.001uF
VCC_TOOL
VCC_MSP
XOUT
TEST/VPP
ACLK
ACLKEN
TCLKEN
2
4
6
8
10
12
14
R432
10K
J14
SPY-BY-WIRE INTERFACE
C653
1uF
D
EVM_3V3
14 MSP430_INT
C657
0.1uF
MSP430_TCK
U38
100K
C162
4
10pF
32.768KHz
MSP430_TDO/TDI
Y3
3
2
DVCC.1
3
P2.5/ROSC/CA5
4
DVSS.1
5
6
P1.7/TA0.2/TDO/TDI
28
P1.6/TA0.1/TDI/TCLK
27
P1.5/TA0.0/TMS
26
P1.4/SMCLK/TCK
25
XOUT/P2.7/CA7
P1.3/TA0.2
24
XIN/P2.6/CA6
P1.2/TA0.1
23
7
RST/NMI/SBWTDIO
8
P2.0/ACLK/A0/CA2
9
1
C161
TEST/SBWTCK
2
P2.1/TAINCLK/SMCLK/A1/CA3
P1.1/TA0.0/TA1.0
22
P1.0/TACLK/ADC10CLK/CAOUT
21
P2.4/TA0.2/A4/VREF+/VEREF+/CA1
20
P2.3/TA0.1/A3/VREF-/VEFEF-/CA0
19
P3.7/TA1.1/A7
18
EVM_3V3
EVM_3V3
P2.2/TA0.0/A2/CA4/CAOUT
P3.0/UCB0STE/UCA0CLK/A5
3,31,32,41,48 IIC0_SDA
12
P3.1/UCB0SIMO/UCB0SDA
P3.6/TA1.0/A6
17
3,31,32,41,48 IIC0_SCL
13
P3.2/UCB0SOMI/UCB0SCL
P3.5/UCA0RXD/UCA0SOMI
16
MSP430_RXD
P3.4/UCA0TXD/UCA0SIMO
15
MSP430_TXD
14
EVM_3V3
B
R434
2K
EVM_3V3
P3.3/UCB0CLK/UCA0STE
+
C666
1uF
11
44,46,48,49 PM_I2C_SCL
R183
10K
C171
10uF
15
11
MSP430F2132IPWR
R436
2K
R184
10K
U39
10
44,46,48,49 PM_I2C_SDA
10pF
C
EVM_3V3
VCC
T_IN
FORCEOFF
16
FORCEON
12
T_OUT
13
9
R_OUT
1
EN
2
C1+
C2+
5
4
C1-
C2-
6
V+
3
V-
7
R_IN
INVALID
DB9M
10
R431
C
1
5
9
4
8
3
7
2
6
1
8
P7
10
11
EVM_3V3
B
R435
10K
C212
1uF
14
GND
MAX3221CPWRG4
C213
1uF
C692
1uF
C693
1uF
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
POW ER MONITOR CPU
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
50 o f
58
5
4
3
2
1
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,53,54,55,56
EVM_12V
EVM_1V0_AVS
C486
1uF
EVM_5V0
C491
1uF
EVM_1V0_AVS 18,20,49,54
EVM_12V
+
C47
100uF,16V
D
+
C41
100uF,16V
EVM_5V0
C39
0.1uF
EVM_5V0
EVM_5V0
C43
6.98K
R80
R76
22.1K
C48
1000pF
1
BG
AGND.13
48
2
VINBQ
AGND.12
47
3
V6V
AGND.11
46
4
VIN
AGND.10
45
5
FB2
AGND.9
44
6
CMP2
AGND.8
43
7
EN_BCK2
AGND.7
42
AGND.6
41
Rbottom = VFBxRtop/(VOUT-VFB)
Rbottom = 0.8xRtop/(2.5)
49 I_MON_3V3_HIGH
EVM_3V3
CURRENT MONITOR
C
EVM_3V3
C387
1000pF
8
9
L8
C49
22uF
C50
22uF
R81
0.025
2
C33
0.1uF
C478
EVM_12V
49 I_MON_5V0_HIGH
11
PH2.2
VINB3.1
38
PH3.2
37
12
VINB2.1
13
VINB2.2
14
BST2
LDRV
EN_BCK3
33
17
HDRV
CMP3
32
18
PH1
FB3
31
19
BST1
AGND.5
30
2 R70
0
C474
0.22uF
1
C473
3300pF
6
5
4.7uH-74477004
36
35
16
20
EN_BCK1
AGND.4
29
21
CMP1
AGND.3
28
22
FB1
AGND.2
27
23
SS
AGND.1
26
24
TRIP
V3P3
25
2
D
C34
22uF
PH3.1
PGND3.2
D
L6
C35
22uF
39
PGND3.1
G
1
VINB3.2
DGND
S
0.025
40
PH2.1
PGND2.2
34
EVM_5V0
R69
BST3
10
15
Q1A
FDS6982
CURRENT EVM_5V0
MONITOR
0.1uF
PGND2.1
8
7
C38
47uF
B
1
2.2uH-HCP0805-2R2-R
EVM_5V0
C40
47uF
U16
20K
TPS65232
Q1B
FDS6982
G
4 R72
PWR PAD
R79
1000pF
11,28,30,44,46,48,49,54,55,56
EVM_1V0_CON
100pF
49
C46
D
EVM_12V 28,29,44,46,48,52,56
C488
1uF
C37
0.1uF
EVM_1V0_CON 9,11,15,16,17,20,49,55
EVM_12V
EVM_12V 28,29,44,46,48,52,56
I_MON_1V0_CONN_HIGH 49
CURRENT MONITOR
C
C481
0.1uF
EVM_1V0_CON 9,11,15,16,17,20,49,55
EVM_1V0_CON
L7
1
R75
2
0.025
2.2uH-HCP0805-2R2-R
R77
22.1K
C45
1000pF
C42
22uF
C44
22uF
R78
88.7K
R71
20K
B
C31
100pF
C30
1000pF
Rbottom = VFBxRtop/(VOUT-VFB)
Rbottom = 0.8xRtop/(.2)
C472
1uF
0
S
R67
22.1K
R62
20K
3
C29
1000pF
C27
100pF
R65
215K
C28
1000pF
C25
1000pF
A
R66
4.22K
SPECTRUM DIGITAL INCORPORATED
C97
1000pF
Title:
C99
1000pF
A
NETRA EVM
Page Contents:
POW ER SUPPLY III
Size:B
DWG NO
Rbottom = VFBxRtop/(VOUT-VFB)
Rbottom = 0.8xRtop/(4.2)
Date:
5
4
3
2
Revision:
A
512872-0001
Tuesday, June 14, 2011
Sheet
1
51 o f
58
5
4
3
2
1
CHECKED VALUES - COMPLETE for feedback
maybe tweak 0402 and 0603
D
D
I_MON_1V5_HIGH 49
CURRENT MONITOR
EVM_1V5
L14
EVM_1V5
TP19
1
1
R202
2
0.025
1.8uH-7447715001
TEST POINT
C
R196
0
U33
C119
10uF
C127
10uF
C118
10uF
C126
4.7uF
RT/CLK
2
GND.1
BOOT
13
3
GND.2
PH.2
12
4
PVIN.1
PH.1
11
5
PVIN.2
6
VIN
7
VSENSE
TPS54620
PWRGD
EN
C220
100uF
14
C148
C225
100uF
C
0.1uF
R194
10.0K
10
SS/TR
9
COMP
8
R174
3.83K
C136
0.018uF
B
R187
11.0K
1
EVM_12V
1
PWRPAD
100K
15
R170
7,8,16,17,21,23,24,25,27,49,53,55,56
C132
56pF
TP20
C143 TEST POINT
.018uF
B
TP13
1
TEST POINT
EVM_1V8_D
EVM_1V8_D
R64
1K
EVM_1V8_D 5,15,16,49,55
EVM_1V5
R73
10K
EVM_1V5
C153
0.1uF
7,8,16,17,21,23,24,25,27,49,53,55,56
SPECTRUM DIGITAL INCORPORATED
A
A
EVM_12V
NETRA EVM
Title:
EVM_12V 28,29,44,46,48,51,56
Page Contents:
POWER SUPPLY 1V5
Size:B
DWG NO
Date:
5
4
3
2
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
52 o f
58
5
4
3
2
1
EVM_3V3
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,54,55,56
EVM_1V5
EVM_1V5
7,8,16,17,21,23,24,25,27,49,52,55,56
D
D
EVM_DDR_VTT
EVM_DDR_VTT 24,49
EVM_1V5
R244
10.0K
EVM_3V3
C381
0.001uF
EVM_3V3
C384
10uF
NO-POP
Q9
D
S
2
10K
10
IRLML6401
R499
1K
R74
10K
1
VLDOIN
2
GND
7
VO
3
PGND
4
EN
6
REFOUT
VOSNS
5
C380
0.1uF
C383
10uF
C382
10uF
EVM_DDR_VTT
VTT
R242
R237
10
C370
10uF
C371
10uF
C372
10uF
0.025
EVM_DDR_VTT 24,49
C374
0.1uF
CURRENT MONITOR
I_MON_VTT_HIGH 49
Q10
FJV3109R
1
R232
NO-POP
PGOOD
8
C375
0.1uF
REFIN
VIN
9
C385
1000pF
C362
10pF
B
TP24
TEST POINT
1
2
B
R235
10K
3
EVM_1V5
R243
10.0K
U58
TPS51200
3
1
G
R498
R241
100K
C
PWRPAD
R497
11
C
EVM_DDR_REF_OUT
EVM_DDR_REF_OUT
SPECTRUM DIGITAL INCORPORATED
A
A
EVM_DDR_REF_OUT 7,8,21,23,25,27
NETRA EVM
Title:
Page Contents:
POWER SUPPLY VTT
Size:B
DWG NO
Date:
5
4
3
2
Revision:
C
512872-0001
Thursday, April 28, 2011
Sheet
1
53 o f
58
5
4
3
EVM_3V3
2
EVM_1V0_AVS
1
SUPPORT OUTPUT VOLTAGES OF 0.75 TO 1.2 VOLTS
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,55,56
EVM_1V0_AVS 18,20,49
EVM_5V0
EVM_5V0 11,28,30,44,46,48,49,51,55,56
EVM_5V0
D
D
+
+
C103
100uF
I_MON_1V0_AVS_HIGH 49
7
8
C102
100uF
D
R92
1
CURRENT MONITOR
Q4A
IRF7910pbf
2
G
S
U29
EVM_3V3
4
S
G
COMP
VDD
PAD
1K
Q7
BSS138
FB
3
PAD
D
C
ENn
2
C94
1uF
HDRV
8
SW
7
BOOT
6
LDRV
L12
1
C100
0.22uF
5
5
6
1
R145
EVM_1V0_AVS 18,20,49
1
R146
10K
EVM_1V0_AVS
R84
2
1.2uH-74470001
0.025
C
1206
D
C58
100uF
TPS40041
Q4B
IRF7910pbf
4
C57
100uF
C54
NO-POP
G
3
S
17.8K C104
560pF
R86
590
C59
R87
R85
0
10.0K
33pF
1
C101
820pF
1
R121
TP12
TEST POINT
TP14
TEST POINT
B
1
B
R134
NO-POP
R133
30.1K
TP18
TEST POINT
R126
49.9K
R105
100K
R93
200K
R89
402K
EVM_3V3
3
10K
2
3
3
S
2
D
GPIO3 MUST BE PULLED LOW
TO ENABLE TIMER USED IN
BOOTLOADER
Q2
NTA4153NT1G
1
S
R91
NO-POP
A
G
G
R106
NO-POP
10K
R90
Q3
NTA4153NT1G
1
S
10K
R94
Q5
NTA4153NT1G
1
R488
NO-POP
D
D
S
R127
NO-POP
G
G
10K
R119
Q6
NTA4153NT1G
1
EVM_3V3
R487
10K
2
3
R486
10K
D
R130
EVM_3V3
2
EVM_3V3
R485
10K
R88
10K
SPECTRUM DIGITAL INCORPORATED
14
GP0_IO0
Title:
14
GP0_IO1
Page Contents:
POWER SUPPLY 1V0_AVS
14
GP0_IO2
Size:B
DWG NO
14
GP0_IO3
5
Date:
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Sunday, June 05, 2011
Sheet
1
54 o f
58
5
4
3
CHECKED VALUES - COMPLETE for feedback
2
1
EVM_5V0
EVM_5V0
+
CT1
33uF
R48
10K
U10
8
VINDCDC
PGn
5
10
EN_DCDC
SW
7
VDCDC = VFB_DCDC x (( Rtop + Rbottom)/Rbottom )
1
VDCDC = 0.6 x (( Rtop + Rbottom)/Rbottom )
TP9
NO-POP
1V8_DIGITAL
TP8
NO-POP
1
D
L4
D
2.2uH
+
C17
9
MODE
FB_DCDC
11
1V8_ANALOG 1
EVM_3V3
15
VINLDO1
VLDO1
14
3
EN_LDO1
FB_LDO1
13
CT2
33uF
18
VINLDO2
VLDO2
17
4
EN_LDO2
FB_LDO2
16
1
MRn
1
R53
80.6K 1%
C18
0.1uF
TP10
NO-POP
R37
100K 1%
R51
261K 1%
0V9_A
+
C19
33uF
R36
200K 1%
22pF
+ C20
33uF
C21
0.1uF
TP11
NO-POP
+
C24
33uF
R40
100K 1%
C23
0.1uF
VLDO1 = VFB_LDO x (( Rtop + Rbottom)/Rbottom )
C
R54
10K
C
VLDO1 = 0.5 x (( Rtop + Rbottom)/Rbottom )
R52
100K 1%
2
C22
0.1uF
VLDO2 = VFB_LDO x (( Rtop + Rbottom)/Rbottom )
10K
R484
100K
C797
.1uF
EVM_5V0
19
RSTSNS
12
AGND
PWR_PAD
R55
TRST
TPS65001
RSTn
20
PGND
6
VLDO2 = 0.5 x (( Rtop + Rbottom)/Rbottom )
0V9_A
21
EVM_1V0_CON
EVM_0V9
R56
0.02
EVM_0V9
R50
100K
5,49
CURRENT MONITOR
B
B
I_MON_0V9_HIGH 49
1V8_ANALOG
EVM_1V8_A
R47
0.02
EVM_1V8_A 9,49
CURRENT MONITOR
EVM_3V3
EVM_3V3
C462
EVM_1V5
U5
R35
4.99K
R34
10K 1%
EVM_5V0
C16
0.1uF
0.1uF
5
SENSE1
VDD
6
4
CT
RESET
1
3
MR
GND
2
I_MON_1V8ANALOG_HIGH 49
1V8_DIGITAL
R30
10K
EVM_1V8_D
R32
0.02
EVM_1V8_D 5,15,16,49,52
1
CURRENT MONITOR
TP7
TPS3808G09DBVRG4
I_MON_1V8DIGITAL_HIGH 49
Reset Threhold 0.84 Volts
EVM_1V8_A
EVM_5V0 11,28,30,44,46,48,49,51,54,56
A
SPECTRUM DIGITAL INCORPORATED
A
EVM_1V8_A 9,49
EVM_1V0_CON
EVM_1V8_D
EVM_1V0_CON 9,11,15,16,17,20,49,51
Title:
EVM_1V8_D 5,15,16,49,52
EVM_3V3
NETRA EVM
Page Contents:
POWER SUPPLY 0V9/1V8_A/1V8B
Size:B
DWG NO
EVM_1V5
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,56
5
4
EVM_1V5
7,8,16,17,21,23,24,25,27,49,52,53,56
3
Date:
2
Revision:
B
512872-0001
Thursday, April 28, 2011
Sheet
1
55 o f
58
5
4
3
2
1
TP2
TP-30
EVM_12V
SW1
SWITCH
2
5
7
8
4
6
1
3
+
R5
2k
D
C4
100uF,16V
SILKSCREEN:
12V IN
J1
F1
CENTER
SHUNT
SLEEVE
1
2
DS1
LED GRN
F_4.0A
POWER DOMAINS
EVM_12V
EVM_5V0
EVM_3V3
EVM_1V8_A
EVM_1V8_D
EVM_1V5
EVM_1V0_AVS
EVM_1V0_CONN
EVM_0V9
EVM_DDR_VTT
12 VOLT INPUT FROM EXTERNAL POWER SUPPLY
5.0 VOLT OUTPUT FROM TPS65232
3.3 VOLT OUTPUT FROM TPS65232
1.8 VOLT ANALOG LDO OUTPUT FROM TPS65001
1.8 VOLT DIGITAL OUTPUT FROM TPS65001
1.5 VOLT OUTPUT FROM TPS54620
1.0 VOLT CORE FROM TPS40041
1.0 VOLT NON-CORE FROM TPS65232
0.9 VOLT OUTPUT FROM TPS65001
0.75 VOLT TERMINATOR DDR3
D
2.5 MM JACK
RASM712
D1
SMCJ14A-13-F
EVM_3V3
EVM_1V5
Left most for Drive Cable
C633
PCB EDGE
U32
C
R179
4.99K
R178
10K 1%
1) 12V
C635
0.22uF
DRIVE CONN
EVM_12V
MH1
6
9
MP2
1
2
3
4
8
+12
GND2
GND1
+5
MP1
MH2
7
EVM_3V3
EVM_5V0
R167
10K
0.1uF
5
SENSE1
4
CT
RESET
1
3
MR
GND
2
VDD
C
6
CPU_PORz 14
TPS3808G09DBVRG4
EVM_3V3
P11
EVM_12V
Reset Threhold 0.84 Volts
1
2
3
TACH
R166
10K
FAN CONNECTOR
SW6
A
A1
HEADER 3
B
B1
PUSHBUTTON SW
J8
EVM_3V3
B
B
EVM_3V3 2,3,5,6,11,13,14,15,18,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,48,49,50,51,53,54,55
BOARD MOUNTING HOLES - ONE IN EACH CORNER
BOARD MOUNTING HOLES - FOR EXPANSION CONNECTORS
EVM_5V0
Mounting holes 0.250 pad 0.125 drill
EVM_5V0 11,28,30,44,46,48,49,51,54,55
MH6
MH3
EVM_12V
MH7
1
1
MH4
1
1
MH8
1
MH9
1
EVM_12V 28,29,44,46,48,51,52
MH5
EVM_1V5
MH1
1
1
MH2
EVM_1V5
1
7,8,16,17,21,23,24,25,27,49,52,53,55
SPECTRUM DIGITAL INCORPORATED
A
Title:
1
TP1
TEST POINT
1
TP6
TEST POINT
1
TP5
TEST POINT
1
TP26
TEST POINT
1
TP17
TEST POINT
1
TP25
TEST POINT
1
TP16
TEST POINT
1
TP23
TEST POINT
Page Contents:
POW ER INPUT
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
A
512872-0001
Thursday, April 28, 2011
Sheet
1
56 o f
58
5
4
3
2
1
3.5
D
D
EVM_3V3
3.0
C
C
EVM_1V8_D
EVM_1V8_A
2.0
VOLTS
EVM_1V5
EVM_1V0_CON
EVM_1V0_AVS
EVM_0V9
1.0
B
10
20
30
40
50
60
70
80
90
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
POW ER SEQUENCE
Size:B
DWG NO
Date:
4
3
2
A
NETRA EVM
Title:
MILLISECONDS
5
B
Revision:
B
512872-0001
Thursday, April 28, 2011
Sheet
1
57 o f
58
5
REVISION A
4
3
2
1
- ASSY 512870
BUILT ON PWB 512871 REVISION A
BUILT ON LOGIC 512872 REVISION A
D
D
ENGINEERING UNITS ONLY
REVISION B
- ASSY 512870
BUILT ON PWB 512871 REVISION B
BUILT ON LOGIC 512872 REVISION B
UPDATED POWER SEQUENCING FROM REVISION A
C
REVISION C
- ASSY 512870
C
BUILT ON PWB 512871 REVISION B
BUILT ON LOGIC 512872 REVISION B
INCREASED C635 TO .22uF FOR LONGER POWER ON RESET FIXED USB ISSUE
CHANGED R218 TO 1K TO FIX PCI RESET
REMOVED R232 AND CHANGED R74 TO 0 , TO HELP RAISE VT ENABLE VOLTAGE ( STILL A
BIT OUT OF SPEC, WILL FIX IN NEXT BOARD REVISION)
REVISION D
B
- ASSY 512870
BUILT ON PWB 512871 REVISION B
B
BUILT ON LOGIC 512872 REVISION B
CHANGED AVS CIRCUITRY AND CPU HAS AVS ENABLED
REVISION E
- ASSY 512870
BUILT ON PWB 512871 REVISION C
BUILT ON LOGIC 512872 REVISION C
UPDATED CAPS AROUND TPS65232 TO HELP WITH OVERVOLTAGE ON SWITCH OUTPUTS OF THE PART LAYOUT IMPROVEMENT
UPDATED VTT ENABLE TO RAISE ENABLE VOLTAGE PAST 1.7V MIN
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
REVISION HISTORY
Size:B
DWG NO
Date:
5
4
3
2
A
NETRA EVM
Revision:
C
512872-0001
Tuesday, June 14, 2011
Sheet
1
58 o f
58