DATASHEET

IGNS
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RECO
ISL78201
2.5A Regulator with Integrated High-Side MOSFET for
Synchronous Buck or Boost Buck Converter
ISL78200
Features
The ISL78200 is a synchronous buck controller with a 90mΩ
high-side MOSFET and low-side driver integrated. The ISL78200
supports wide input range of 3V to 40V in buck mode. It supports
2.5A continuous load under conditions of 5V VOUT, VIN range of
8V to 36V, 500kHz and +85°C ambient temperature with still air.
For any specific application, the actual maximum output current
depends upon the die temperature not exceeding +125°C with
the power dissipated in the IC, which is related to input voltage,
output voltage, duty cycle, switching frequency, ambient
temperature and board layout, etc. Refer to section “Output
Current” on page 14 for more details.
• Buck Mode: Input Voltage Range 3V to 40V (Refer to “Input
Voltage” on page 14 for more details)
The ISL78200 has flexible selection of operation modes of forced
PWM mode and PFM mode. In PFM mode, the quiescent input
current is as low as 300µA and can be further reduced to 180µA
with AUXVCC connected to VOUT under 12V VIN and 5V VOUT
application. The load boundary between PFM and PWM can be
programmed to cover wide applications.
The low-side driver can be either used to drive an external low-side
MOSFET for a synchronous buck, or left unused for a standard
non-synchronous buck. The low-side driver can also be used to
drive a boost converter as a pre-regulator that greatly expands the
operating input voltage range down to 2.5V or lower (refer to
“Typical Application Schematic III - Boost Buck Converters” on
page 5).
The ISL78200 offers the most robust current protections. It uses
peak current mode control with cycle-by-cycle current limiting. It is
implemented with frequency foldback under current limit
condition; in addition, the hiccup overcurrent mode is also
implemented to guarantee reliable operations under harsh short
conditions.
The ISL78200 has comprehensive protections against various faults
including overvoltage and over-temperature protections, etc.
• Boost Mode Expands Operating Input Voltage Lower Than
2.5V (Refer to “Input Voltage” on page 14 for more details)
• Selectable Forced PWM Mode or PFM Mode
• 300µA IC Quiescent Current (PFM, No Load); 180µA Input
Quiescent Current (PFM, No Load, VOUT Connected to AUXVCC)
• Less than 3µA Shut Down Input Current (IC Disabled)
• Operational Topologies
- Synchronous Buck
- Non-Synchronous Buck
- Two Stage Boost Buck
• Programmable Frequency from 200kHz - 2.2MHz and
Frequency Synchronization Capability
• ±1% Tight Voltage Regulation Accuracy
• Reliable Cycle-by-Cycle Overcurrent Protection
- Temperature Compensated Current Sense
- Frequency Foldback
- Programmable OC Limit
- Hiccup Mode Protection in Worst Case Short Condition
• 20 Ld HTSSOP Package
• AEC Q100 Qualified
• Pb-Free (RoHS Compliant)
Applications
•
•
•
•
•
Automotive Applications
General Purpose Power Regulator
24V Bus Power
Battery Power
Embedded Processor and I/O Supplies
100
95
VIN
SYNC
AUXVCC
VCC
BOOT
ISL78200
ILIMIT
PHASE
LGATE
SS
PGND
EXT_BOOST
FS
SGND
FB
COMP
6V VIN
90
VIN
VOUT
EFFICIENCY (%)
PGOOD
EN
MODE
85
12V VIN
80
40V VIN
75
24V VIN
70
65
60
55
50
0.1m
1m
10m
100m
1
2.5
LOAD CURRENT (A)
FIGURE 1. TYPICAL APPLICATION
December 24, 2013
FN7641.2
1
FIGURE 2. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 5V, TA = +25°C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78200
Pin Configuration
ISL78200
(20 LD HTSSOP)
TOP VIEW
PGND 1
20 LGATE
BOOT 2
19 SYNC
VIN 3
18 EXT_BOOST
VIN 4
SGND 5
VCC 6
17 PHASE
21
PAD
16 PHASE
15 PGOOD
AUXVCC 7
14 MODE
EN 8
13 ILIMIT
FS 9
12 COMP
SS 10
11 FB
Functional Pin Description
PIN NAME
PIN #
PGND
1
This pin is used as the ground connection of the power flow including driver.
DESCRIPTION
BOOT
2
This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive
the internal N-channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed. A
1µF ceramic capacitor is recommended to be used between BOOT and PHASE pin.
VIN
3, 4
Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET, as well as the source
for the internal linear regulator that provides the bias of the IC. Range: 3V to 40V.
With the part switching, the operating input voltage applied to the VIN pins must be under 40V. This recommendation allows
for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding Absolute Maximum
Ratings.
SGND
5
This pin provides the return path for the control and monitor portions of the IC.
VCC
6
This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF
decoupling ceramic capacitor is recommended between VCC to ground.
AUXVCC
7
This pin is the input of the auxiliary internal linear regulator which can be supplied by the regulator output after power-up. With
such a configuration, the power dissipation inside the IC is reduced. The input range for this LDO is 3V to 20V.
In boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a resistor
divider. When voltage on this pin is above 0.8V, the boost PWM is disabled; and when voltage on this pin is below 0.8V minus
the hysteresis, the boost PWM is enabled. Range: 3V to 20V.
EN
8
The controller is enabled when this pin is pulled HIGH or left floating. The IC is disabled when this pin is pulled LOW.
Range: 0V to 5.5V.
FS
9
To connect this pin to VCC, or GND, or left open will force the IC to have 500kHz switching frequency. The oscillator switching
frequency can also be programmed by adjusting the resistor from this pin to GND.
SS
10
Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start
interval of the converter. Also this pin can be used to track a ramp on this pin.
FB
11
This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from
VOUT to FB, the output voltage can be set to any voltage between the input rail (reduced by maximum duty cycle and voltage
drop) and the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin
is also monitored for overvoltage events.
COMP
12
Output of the voltage feedback error amplifier.
ILIMIT
13
Programmable current limit pin. With this pin connected to VCC pin, or to GND, or left open, the current limit threshold is set
to default 3.6A; the current limit threshold can be programmed with a resistor from this pin to GND.
MODE
14
Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM mode
when the peak inductor current is below the default threshold of 700mA. The current boundary threshold between PFM and
PWM can also be programmed with a resistor at this pin to ground. For more details on PFM Mode Operation refer to the
“Functional Description” on page 13.
PGOOD
15
PGOOD is an open drain output that will be pulled low immediately under the events when the output is out of regulation (OV
or UV) or EN pin pulled low. PGOOD is equipped with a fixed delay of 1000 cycles upon output power-up (VO > 90%).
2
FN7641.2
December 24, 2013
ISL78200
Functional Pin Description (Continued)
PIN NAME
PIN #
DESCRIPTION
PHASE
16, 17
These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source of
the high-side N channel MOSFET.
EXT_BOOST
18
This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR, the
controller will detect the voltage on this pin, if voltage on this pin is below 200mV, the controller is set in
synchronous/non-synchronous buck mode and latch in this state unless VCC is below the POR falling threshold; if the voltage
on this pin after VCC POR is above 200mV, the controller is set in boost mode and latch in this state.
In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high
threshold and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost
converter is disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled.
In boost mode operation, PFM is disabled when boost PWM is enabled. Check Boost Mode Operation in the “Functional
Description” on page 13 for more details.
SYNC
19
This pin can be used to synchronize two or more ISL78200 controllers. Multiple ISL78200 can be synchronized with their SYNC
pins connected together. 180 degree phase shift is automatically generated between the master and slave ICs.
The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with
frequency 10% higher than the IC’s local frequency, and pulse width higher than 150ns).
This pin should be left floating if not used. Range: 0V to 5.5V.
LGATE
20
In synchronous buck mode, this pin is used to drive the lower side MOSFET to improve efficiency.
In non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to VCC before
VCC start-up to have low-side driver (LGATE) disabled.
In boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is the same with the buck control PWM.
PAD
21
Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground
copper plane with an area as large as possible to effectively reduce the thermal impedance.
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL78200AVEZ
ISL78200 AVEZ
ISL78200EVAL1Z
Evaluation Board
TEMP.
RANGE
(°C)
-40 to +105
PACKAGE
(Pb-Free)
20 Ld HTSSOP
PKG.
DWG. #
MDP0048
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78200. For more information on MSL please see techbrief TB363.
3
FN7641.2
December 24, 2013
Block Diagram
AUXVCC
VCC
PGOOD
VIN (x2)
VIN
4
CURRENT
MONITOR
AUXILARY LDO
BIAS LDO
ILIMIT
POWER-ON
RESET
SGND
VCC
BOOT
EXT_BOOST
MODE
PFM/FPWM
PHASE (x2)
GATE DRIVE
VOLTAGE
MONITOR
SYNC
FS
SLOPE
COMPENSATION
OSCILLATOR
+
SOFT-START
LOGIC
VCC
5 µA
BOOT REFRESH
0.8V
REFERENCE
EA
SS
+
LGATE
FB
COMPARATOR
COMP
PGND
ISL78200
OCP, OVP, OTP
PFM LOGIC
BOOST MODE CONTROL
EN
FN7641.2
December 24, 2013
ISL78200
Typical Application Schematic I
PGOOD
EN
MODE
SYNC
AUXVCC
VCC
PGOOD
EN
MODE
VIN
VIN
SYNC
AUXVCC
BOOT
ISL78200
ILIMIT
V OUT
PHASE
VCC
EXT_BOOST
FS
SGND
ISL78200
LGATE
PGND
EXT_BOOST
FS
SGND
FB
COMP
V OUT
PHASE
SS
PGND
VIN
BOOT
ILIMIT
LGATE
SS
VIN
FIGURE 3A. SYNCHRONOUS BUCK
FB
COMP
FIGURE 3B. NON-SYNCHRONOUS BUCK
Typical Application Schematic II - VCC Switch Over to VOUT
PGOOD
EN
MODE
SYNC
AUXVCC
VCC
PGOOD
EN
MODE
VIN
VIN
SYNC
AUXVCC
BOOT
ISL78200
ILIMIT
VCC
VOUT
PHASE
EXT_BOOST
FS
SGND
ISL78200
PGND
EXT_BOOST
FS
SGND
FB
COMP
FIGURE 4A. SYNCHRONOUS BUCK
V OUT
PHASE
LGATE
SS
PGND
VIN
BOOT
ILIMIT
LGATE
SS
VIN
FB
COMP
FIGURE 4B. NON-SYNCHRONOUS BUCK
Typical Application Schematic III - Boost Buck Converters
Battery
+
+
R1
R2
PGOOD
EN
MODE
EXT_BOOST
LGATE
AUXVCC
SYNC
VCC
ILIMIT
SS
FS
SGND
5
R3
R4
VIN
ISL78200
BOOT
PHASE
V OUT
PGND
COMP
FB
FN7641.2
December 24, 2013
ISL78200
Absolute Maximum Ratings
Thermal Information
VIN, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +44V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.0V
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +22V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . +6.0V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1000V
Latchup Rating (Tested per JESD78B; Class II, Level A) . . . . . . . . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
HTSSOP Package (Notes 4, 5) . . . . . . . . . . . . . . .
35
3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage on VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20V
Ambient Temperature Range (Automotive). . . . . . . . . . . . . . .-40°C to +105°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Refer to the Block Diagram (page 4) and Typical Application Schematics (page 5). Operating conditions
unless otherwise noted: VIN = 12V, or VCC = 4.5V, TA = -40°C to +105°C. Typicals are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +105°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
VIN SUPPLY
VIN Pin Voltage Range
Operating Supply Current
IQ
ShutDown Supply Current
IIN_SD
VIN Pin
3.05
40
V
VIN connected to VCC
3.05
5.5
V
MODE = VCC/FLOATING (PFM), no load at the
output
300
µA
MODE = GND (Forced PWM), VIN = 12V, IC
Operating, Not Including Driving Current
1.2
mA
EN connected to GND, VIN = 12V
1.8
3
µA
4.5
4.8
V
VIN = 4.2V, IVCC = 35mA
0.3
0.5
V
VIN = 3V, IVCC = 25mA
0.25
0.3
V
INTERNAL MAIN LINEAR REGULATOR
MAIN LDO VCC Voltage
VCC
MAIN LDO Dropout Voltage
VDROPOUT_MAIN
VIN > 5V
4.2
VCC Current Limit of MAIN LDO
60
mA
INTERNAL AUXILIARY LINEAR REGULATOR
AUXVCC Input Voltage Range
VAUXVCC
AUX LDO VCC Voltage
VCC
LDO Dropout Voltage
VDROPOUT_AUX
3
20
V
4.5
4.8
V
VAUXVCC = 4.2V, IVCC = 35mA
0.3
0.5
V
VAUXVCC = 3V, IVCC = 25mA
0.25
0.3
V
VAUXVCC > 5V
4.2
Current Limit of AUX LDO
60
mA
AUX LDO Switch-over Rising Threshold
VAUXVCC_RISE
AUXVCC voltage rise, switch to auxiliary LDO
2.97
3.1
3.2
V
AUX LDO Switch-over Falling Threshold
VAUXVCC_FALL
AUXVCC voltage fall, switch back to main
BIAS LDO
2.73
2.87
2.97
V
AUX LDO Switch-over Hysteresis
VAUXVCC_HYS
AUXVCC switch-over hysteresis
6
0.2
V
FN7641.2
December 24, 2013
ISL78200
Electrical Specifications Refer to the Block Diagram (page 4) and Typical Application Schematics (page 5). Operating conditions
unless otherwise noted: VIN = 12V, or VCC = 4.5V, TA = -40°C to +105°C. Typicals are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
2.82
2.9
3.05
V
2.8
V
POWER-ON RESET
Rising VCC POR Threshold
VPORH_RISE
Falling VCC POR Threshold
VPORL_FALL
2.6
VCC POR Hysteresis
VPORL_HYS
0.3
V
ENABLE
Required Enable On Voltage
VENH
Required Enable Off Voltage
VENL
EN Pull Up Current
IEN_PULLUP
2
V
0.8
V
VIN =24V
0.8
µA
VIN =12V
0.5
µA
VIN =5V
0.25
µA
OSCILLATOR
PWM Frequency
FOSC
RT = 665kΩ
160
200
240
kHz
RT = 51.1kΩ
1950
2200
2450
kHz
FS pin connected to VCC or floating or GND
450
500
550
kHz
MIN ON Time
tMIN_ON
130
225
ns
MIN OFF Time
tMIN_OFF
210
325
ns
Input High Threshold
VIH
2
V
Input Low Threshold
VIL
0.5
V
Input Minimum Pulse Width
25
ns
Input Impedance
100
kΩ
Input Minimum Frequency Divided by Free
Running Frequency
1.1
Input Maximum Frequency Divided by Free
Running Frequency
1.6
SYNCHRONIZATION
Output Pulse Width
CSYNC=100pF
100
ns
RLOAD=1kΩ
VCC0.25
V
Output Pulse High
VOH
Output Pulse Low
VOL
GND
V
VREF
0.8
V
REFERENCE VOLTAGE
Reference Voltage
System Accuracy
-1.0
FB Pin Source Current
1.0
5
%
nA
SOFT-START
Soft-Start Current
ISS
3
5
7
µA
ERROR AMPLIFIER
Unity Gain-Bandwidth
CLOAD = 50pF
10
MHz
DC Gain
CLOAD = 50pF
88
dB
3.6
V
Maximum Output Voltage
7
FN7641.2
December 24, 2013
ISL78200
Electrical Specifications Refer to the Block Diagram (page 4) and Typical Application Schematics (page 5). Operating conditions
unless otherwise noted: VIN = 12V, or VCC = 4.5V, TA = -40°C to +105°C. Typicals are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
Minimum Output Voltage
TYP
MAX
(Note 6) UNITS
0.5
V
5
V/µs
MODE = VCC or floating
700
mA
(Note 7)
90
LGATE Source Resistance
100mA Source Current
3.5
Ω
LGATE Sink Resistance
100mA Sink Current
3.3
Ω
Slew Rate
SR
CLOAD = 50pF
PFM MODE CONTROL
Default PFM Current Threshold
INTERNAL HIGH-SIDE MOSFET
Upper MOSFET rDS(ON)
rDS(ON)_UP
150
mΩ
LOW-SIDE MOSFET GATE DRIVER
BOOST CONVERTER CONTROL
EXT_BOOST Boost_Turn-Off Threshold Voltage
EXT_BOOST Hysteresis Sink Current
IAUXVCC_HYS
AUXVCC Boost Turn-Off Threshold Voltage
AUXVCC Hysteresis Sink Current
IAUXVCC_HYS
0.74
0.8
0.86
V
2.4
3.2
3.8
µA
0.74
0.8
0.86
V
2.4
3.2
3.8
µA
104
110
116
%
POWER GOOD MONITOR
Overvoltage Rising Trip Point
VFB/VREF
Percentage of Reference Point
Overvoltage Rising Hysteresis
VFB/VOVTRIP
Percentage Below OV Trip Point
Undervoltage Falling Trip Point
VFB/VREF
Percentage of Reference Point
Undervoltage Falling Hysteresis
VFB/VUVTRIP
Percentage Above UV Trip Point
3
%
fOSC = 500kHz
2
ms
PGOOD HIGH, VPGOOD = 4.5V
10
nA
VPGOOD
PGOOD LOW, IPGOOD = 0.2mA
0.10
V
Default Cycle by Cycle Current Limit Threshold
IOC_1
ILIMIT = GND or VCC or Floating
Hiccup Current Limit Threshold
IOC_2
Hiccup, IOC_2/IOC_1
115
%
OV Latching-off Trip Point
Percentage of Reference Point
LG = UG = LATCH LOW
120
%
OV Non-Latching-off Trip Point
Percentage of Reference Point
LG = UG = LOW
110
%
OV Non-Latching-off Release Point
Percentage of Reference Point
102.5
%
Over-Temperature Trip Point
155
°C
Over-Temperature Recovery Threshold
140
°C
PGOOD Rising Delay
tPGOOD_DELAY
PGOOD Leakage Current
PGOOD Low Voltage
3
84
90
%
96
%
PROTECTION
3
3.6
4.2
A
OVERVOLTAGE PROTECTION
OVER-TEMPERATURE PROTECTION
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Wire bonds not included. The wire bond resistance between VIN and PHASE pin is 32mΩ typical.
8
FN7641.2
December 24, 2013
ISL78200
100
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
95
6V VIN
90
24V VIN
12V VIN
40V VIN
EFFICIENCY (%)
EFFICIENCY (%)
Performance Curves
6V VIN
12V VIN
85
80
40V VIN
75
24V VIN
70
65
60
55
0.5
1.0
1.5
50
0.1m
2.5
2.0
1m
FIGURE 5. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, VOUT 5V, TA = +25°C
4.970
4.968
4.968
4.966
4.966
4.964
4.960
VOUT (V)
VOUT (V)
1
2.5
4.964
IO = 0A
4.962
IO = 2A
4.958
4.956
4.962
4.954
4.952
4.952
10
40V VIN
4.956
IO = 1A
5
6V VIN
4.958
4.954
0
24V VIN
4.960
15
20
25
30
35
40
45
12V VIN
4.950
0.0
50
0.5
FIGURE 7. LINE REGULATION, VOUT 5V, TA = +25°C
1.5
2.0
2.5
FIGURE 8. LOAD REGULATION, VOUT 5V, TA = +25°C
100
95
90
12V VIN
85
24V VIN
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
1.0
LOAD CURRENT (A)
INPUT VOLTAGE (V)
EFFICIENCY (%)
100m
FIGURE 6. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 5V, TA = +25°C
4.970
4.950
10m
LOAD CURRENT (A)
LOAD CURRENT (A)
40V VIN
6V VIN
6V VIN
12V VIN
80
40V VIN
75
24V VIN
70
65
60
55
50
45
0.5
1.0
1.5
2.0
2.5
LOAD CURRENT (A)
FIGURE 9. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, VOUT 3.3V, TA = +25°C
9
40
0.1m
1m
10m
100m
LOAD CURRENT (A)
1
2.5
FIGURE 10. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 3.3V, TA = +25°C
FN7641.2
December 24, 2013
ISL78200
Performance Curves
(Continued)
150
200
180
IC DIE TEMPERATURE (°C)
INPUT CURRENT (µA)
145
VIN = 12V
160
140
120
VIN = 24V
100
80
VIN = 40V
60
40
140
135
130
125
120
115
110
20
0
-50
-25
0
25
50
75
100
105
0
125
5
10
15
20
25
85
85
80
80
75
75
70
60
55
VOUT = 9V
VOUT = 20V
VOUT = 12V
50
45
VOUT = 5V
40
35
30
25
0
5
10
15
20
25
30
35
35
40
45
50
FIGURE 12. IC DIE TEMPERATURE UNDER +105°C AMBIENT
TEMPERATURE, 100 CFM, 500kHz, VOUT = 5V, IO = 2A
IC DIE TEMPERATURE (°C)
IC DIE TEMPERATURE (°C)
FIGURE 11. INPUT QUIESCENT CURRENT UNDER NO LOAD,
PFM MODE, AUXVCC CONNECTED TO VOUT, VOUT = 5V
65
30
VIN (V)
AMBIENT TEMPERATURE (°C)
40
45
50
70
65
60
55
50
VIN = 40V
45
40
VIN = 24V
35
30
25
1.0
1.5
2.0
VIN (V)
FIGURE 13. IC DIE TEMPERATURE UNDER +25°C AMBIENT
TEMPERATURE, STILL AIR, 500kHz, IO = 2A
VIN = 12V
2.5
IOUT (A)
FIGURE 14. IC DIE TEMPERATURE UNDER +25°C AMBIENT
TEMPERATURE, STILL AIR, 500kHz, VOUT = 9V
VOUT 2V/DIV
VOUT 2V/DIV
PHASE 20V/DIV
PHASE 20V/DIV
2ms/DIV
FIGURE 15. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A,
ENABLE ON
10
2ms/DIV
FIGURE 16. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A,
ENABLE OFF
FN7641.2
December 24, 2013
ISL78200
Performance Curves
(Continued)
VOUT 20mV/DIV (5V OFFSET)
VOUT 2V/DIV
PHASE 20V/DIV
PHASE 20V/DIV
5µs/DIV
2ms/DIV
FIGURE 17. VIN 36V, PREBIASED START-UP
VOUT 100mV/DIV (5V OFFSET)
FIGURE 18. SYNCHRONOUS BUCK WITH FORCE PWM MODE,
VIN 36V, IO 2A
VOUT 70mV/DIV (5V OFFSET)
VOUT 1V/DIV
LGATE 5V/DIV
IOUT 1A/DIV
PHASE 20V/DIV
PHASE 20V/DIV
1ms/DIV
100µs/DIV
FIGURE 19. VIN 24V, 0 TO 2A STEP LOAD, FORCE PWM MODE
FIGURE 20. V IN 24V, 80mA LOAD, PFM MODE
VOUT 200mV/DIV (5V OFFSET)
LGATE 5V/DIV
IOUT 1A/DIV
VOUT 10mV/DIV (5V OFFSET)
PHASE 5V/DIV
PHASE 20V/DIV
1ms/DIV
FIGURE 21. VIN 24V, 0 TO 2A STEP LOAD, PFM MODE
11
20µs/DIV
FIGURE 22. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
VIN 12V, NO LOAD
FN7641.2
December 24, 2013
ISL78200
Performance Curves
(Continued)
VOUT 1V/DIV
VOUT 10mV/DIV (5V OFFSET)
PHASE 10V/DIV
VIN_BOOST 5V/DIV
20ms/DIV
5µs/DIV
FIGURE 23. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
VIN 12V, 2A
FIGURE 24. BOOST BUCK MODE, BOOST INPUT STEP FROM
40V TO 3V
VOUT 5V/DIV
VOUT 1V/DIV
IL_BOOST 2A/DIV
PHASE_BOOST 20V/DIV
PHASE_BUCK 20V/DIV
VIN_BOOST 5V/DIV
20ms/DIV
10ms/DIV
FIGURE 25. BOOST BUCK MODE, BOOST INPUT STEP FROM
3V TO 40V
FIGURE 26. BOOST BUCK MODE, VO = 9V, IO = 1.8A, BOOST INPUT
DROPS FROM 16V TO 9V DC
95
90
15V VIN
EFFICIENCY (%)
85
80
6V VIN
75
9V VIN
70
5V VIN
65
30V VIN
60
BOOST BUCK, VO = 12V
55
50
0.0 0.2
0.4
0.6 0.8
1.0
1.2 1.4 1.6
1.8
2.0 2.2
2.4
LOAD CURRENT (A)
FIGURE 27. EFFICIENCY, BOOST BUCK, 500kHz, VOUT 12V, TA = +25°C
12
FN7641.2
December 24, 2013
ISL78200
Functional Description
Initialization
PFM Mode Operation
Initially, the ISL78200 continually monitors the voltage at EN pin.
When the voltage on EN pin exceeds its rising threshold, the
internal LDO will start-up to build up VCC. After Power-On Reset
(POR) circuits detect that VCC voltage has exceeded the POR
threshold, the soft-start will be initiated.
Soft-Start
The soft-start (SS) ramp is built up in the external capacitor on
the SS pin that is charged by an internal 5µA current source.
C SS  F  = 6.5  t SS  S 
(EQ. 1)
To pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating
will set the IC to have PFM (Pulse Frequency Modulation)
operation in light load. In PFM mode, the switching frequency is
dramatically reduced to minimize the switching loss. The
ISL78200 enters PFM mode when the MOSFET peak current is
lower than the PWM/PFM boundary current threshold. This
threshold is 700mA as default when there is no programming
resistor at MODE pin. It can also be programmed by a resistor at
the MODE pin to ground (see Equation 2).
118500
R MODE = ----------------------------IPFM + 0.2
where IPFM is the desired PWM/PFM boundary current threshold
and RMODE is the programming resistor.
The SS ramp starts from 0V to a voltage above 0.8V. Once SS
reaches 0.8V, the bandgap reference takes over and the IC goes
into steady state operation.
500
400
RMODE (kΩ)
The SS plays a vital role in the hiccup mode of operation. The IC
works as cycle-by-cycle peak current limiting at overload
condition. When a harsh condition occurs and the current in the
upper side MOSFET reaches the second overcurrent threshold,
the SS pin is pulled to ground and a dummy soft-start cycle is
initiated. At the dummy SS cycle, the current to charge the
soft-start cap is cut down to 1/5 of its normal value. Therefore, a
dummy SS cycle takes 5 times that of the regular SS cycle.
During the dummy SS period, the control loop is disabled and no
PWM output. At the end of this cycle, it will start the normal SS.
The hiccup mode persists until the second overcurrent threshold
is no longer reached.
(EQ. 2)
300
200
100
0
0.0
0.2
0.4
0.6
0.8
IPFM (A)
1.0
1.2
1.4
FIGURE 28. RMODE vs IPFM
The ISL78200 is capable of start-up with prebiased output.
PWM Control
Pulling the MODE pin to GND will set the IC in forced PWM mode.
The ISL78200 employs the peak current mode PWM control for
fast transient response and cycle-by-cycle current limiting. See
“Block Diagram” on page 4.
The PWM operation is initialized by the clock from the oscillator.
The upper MOSFET is turned on by the clock at the beginning of a
PWM cycle and the current in the MOSFET starts to ramp up.
When the sum of the current sense signal and the slope
compensation signal reaches the error amplifier output voltage
level, the PWM comparator is triggered to shut down the PWM
logic to turn off the high-side MOSFET. The high-side MOSFET
stays off until the next clock signal comes for the next cycle.
The output voltage is sensed by a resistor divider from VOUT to the
FB pin. The difference between the FB voltage and 0.8V
reference is amplified and compensated to generate the error
voltage signal at the COMP pin. Then the COMP pin signal is
compared with the current ramp signal to shut down the PWM.
Synchronous and
Non-Synchronous Buck
The ISL78200 supports both synchronous and non-synchronous
buck operations. For a non-synchronous buck operation when a
power diode is used as the low-side power device, the LGATE
driver can be disabled with LGATE connected to VCC (before IC
start-up).
AUXVCC Switch-Over
The ISL78200 has an auxiliary LDO integrated as shown in the
block diagram. It is used to replace the internal MAIN LDO
function after the IC start-up. “Typical Application Schematic II VCC Switch Over to VOUT” on page 5 shows its basic application
setup with output voltage connected to AUXVCC. After IC
soft-start done and the output voltage is built up to steady state,
once the AUXVCC pin voltage is over the AUX LDO Switch-over
Rising Threshold, the MAIN LDO is shut off and the AUXILIARY
LDO is activated to bias VCC. Since the AUXVCC pin voltage is
lower than input voltage VIN, the internal LDO dropout voltage
and the consequent power loss is reduced. This feature brings
substantial efficiency improvements in light load range
especially at high input voltage applications.
When the voltage at AUXVCC falls below the AUX LDO Switch-over
Falling Threshold, the AUXILIARY LDO is shut off and the MAIN LDO
13
FN7641.2
December 24, 2013
ISL78200
is re-activated to bias VCC. At the OV/UV fault events, the IC also
switch over back from AUXILIARY LDO to MAIN LDO.
The AUXVCC switchover function is offered in buck configuration.
It is not offered in boost configuration when the AUXVCC pin is
used to monitor the boost output voltage for OVP.
Input Voltage
With the part switching, the operating ISL78200 input voltage
must be under 40V. This recommendation allows for short
voltage ringing spikes (within a couple of ns time range) due to
part switching while not exceeding 44V as Absolute Maximum
Ratings.
The lowest IC operating input voltage (VIN pin) depends on VCC
voltage and the Rising and Falling VCC POR Threshold in
Electrical Specifications table. At IC start-up when VCC is just
over rising POR threshold, there is no switching yet before the
soft-start starts. So the IC minimum start-up voltage on VIN pin is
3.05V (MAX of Rising VCC POR). When the soft-start is initiated,
the regulator is switching and the dropout voltage across the
internal LDO increases due to driving current. Thus the IC VIN pin
shutdown voltage is related to driving current and VCC POR
falling threshold. The internal upper side MOSFET has typical
10nC gate drive. For a typical example of synchronous buck with
4nC lower MOSFET gate drive and 500kHz switching frequency,
the driving current is 7mA total causing 70mV drop across
internal LDO under 3V Vin. Then the IC shut down voltage on VIN
pin is 2.87V (2.8V+0.07V). In practical design, extra room should
be taken into account with concerns of voltage spikes at VIN.
With boost buck configuration, the input voltage range can be
expanded further down to 2.5V or lower depending on the boost
stage voltage drop upon maximum duty cycle. Since the boost
output voltage is connected to VIN pin as the buck inputs, after
the IC starts up, the IC will keep operating and switching as long
as the boost output voltage can keep the VCC voltage higher than
falling threshold. Refer to “Boost Converter Operation” on page 14 for
more details.
Output Voltage
The ISL78200 output voltage can be programmed down to 0.8V
by a resistor divider from VOUT to FB. The maximum achievable
voltage is (VIN * DMAX - VDROP), where VDROP is the voltage drop
in the power path including mainly the MOSFET rDS(ON) and
inductor DCR. The maximum duty cycle DMAX is decided by (1 - Fs
* tMIN(OFF)).
Output Current
With the high-side MOSFET integrated, the maximum current
ISL78200 can support is decided by the package and many
operating conditions including input voltage, output voltage, duty
cycle, switching frequency and temperature, etc.
First: The maximum output current is limited by the maximum
OC threshold that is 4.18A (TYP).
Second: From the thermal perspective, the die temperature
shouldn’t be above +125°C with the power loss dissipated inside
of the IC. Figures 12 through 14 show the thermal performance
of this part operating at different conditions. The part can output
14
2.5A under typical application condition VIN 8~36V, VO 5V,
500kHz, still air and +85°C ambient conditions. The output
current should be derated under any conditions causing the die
temperature to exceed +125°C.
Figure 12 shows a 5V, 2A output application over VIN range under
+105°C ambient temperature with 100 CFM air flow.
Figure 13 shows 2A applications under +25°C still air conditions.
Different VOUT (5V, 9V, 12V, 20V) applications thermal data are
shown over VIN range at +25°C and still air. The temperature rise
data in this figure can be used to estimate the die temperature at
different ambient temperatures under various operating
conditions. Note: More temperature rise is expected at higher
ambient temperatures due to more conduction loss caused by
rDS(ON) increase.
Figure 14 shows thermal performance under various output
currents and input voltages. It shows the temperature rise trend
with load and VIN changes.
Basically, the die temperature equals the sum of ambient
temperature and the temperature rise resulting from power
dissipated from the IC package with a certain junction to
ambient thermal impedance JA. The power dissipated in the IC
is related to the MOSFET switching loss, conduction loss and the
internal LDO loss. Besides the load, these losses are also related
to input voltage, output voltage, duty cycle, switching frequency
and temperature. With the exposed pad at the bottom, the heat
of the IC mainly goes through the bottom pad and JA is greatly
reduced. The JA is highly related to layout and air flow
conditions. In layout, multiple vias (20) are strongly
recommended in the IC bottom pad. In addition, the bottom pad
with its vias should be placed in ground copper plane with an
area as large as possible connected through multiple layers.
The JA can be reduced further with air flow. Refer to Figure 12
for the thermal performance with 100 CFM air flow.
Boost Converter Operation
The Typical Application Schematic III on page 5 shows the
circuits where the boost works as a pre-stage to provide input to
the following Buck stage. This is for applications when the input
voltage could drop to a very low voltage in some constants (in
some battery powered systems as an example), causing the
output voltage drops out of regulation. The boost converter can
be enabled to boost the input voltage up to keep the output
voltage in regulation. When the system input voltage recovers
back to normal, the boost stage is disabled while only the buck
stage is switching.
EXT_BOOST pin is used to set boost mode and monitor the boost
input voltage. At IC start-up before soft-start, the controller will
latch in boost mode when the voltage on this pin is above
200mV; it will latch in synchronous buck mode if voltage on this
pin is below 200mV. In boost mode, the low-side driver output
PWM has the same PWM signal with the buck regulator.
In boost mode, the EXT_BOOST pin is used to monitor boost input
voltage to turn on and turn off the boost PWM. The AUXVCC pin is
used to monitor the boost output voltage to turn on and turn off
the boost PWM.
FN7641.2
December 24, 2013
ISL78200
BATTERY
VOUT_BST
+
+
R1
EXT_BOOST
0.8V
R2
I_HYS = 3µA
R3
LOGIC
LGATE
AUXVCC
R4
PWM
0.8V
LGATE
DRIVE
I_HYS = 3µA
FIGURE 29. BOOST CONVERTER CONTROL
Referring to Figure 29, a resistor divider from boost input voltage
to the EXT_BOOST pin is used to detect the boost input voltage.
When the voltage on the EXT_BOOST pin is below 0.8V, the boost
PWM is enabled with a fixed 500µs soft-start when the boost
duty cycle increases from tMINON*Fs to ~50% and a 3µA sinking
current is enabled at the EXT_BOOST pin for hysteresis purposes.
When the voltage on the EXT_BOOST pin recovers to above 0.8V,
the boost PWM is disabled immediately. Use Equation 3 to
calculate the upper resistor RUP (R1 in Figure 29) for a desired
hysteresis VHYS at boost input voltage
VHYS
R UP  M  = ---------------3  A 
(EQ. 3)
Use Equation 4 to calculate the lower resistor RLOW (R2 in
Figure 29) according to a desired boost enable threshold.
R UP  0.8
R LOW = ---------------------------VFTH – 0.8
(EQ. 4)
where VFTH is the desired falling threshold on boost input
voltage to turn on the boost, 3µA is the hysteresis current, and
0.8V is the reference voltage to be compared.
Note the boost start-up threshold has to be selected in a way that
the buck is operating well at close loop before boost start-up.
Otherwise, large inrush current at boost start-up could occur at
boost input due to the buck loop saturation.
Similarly, a resistor divider from boost output voltage to the
AUXVCC pin is used to detect the boost output voltage. When the
voltage on AUXVCC pin is below 0.8V, the boost PWM is enabled
with a fixed 500µs soft-start, and a 3µA sinking current is
enabled at AUXVCC pin for hysteresis purpose. When the voltage
on the AUXVCC pin recovers to above 0.8V, the boost PWM is
disabled immediately. Use Equation 3 to calculate the upper
resistor RUP (R3 in Figure 29) according to a desired hysteresis
VHY at boost output voltage. Use Equation 4 to calculate the
lower resistor RLOW (R4 in Figure 29) according to a desired
boost enable threshold at boost output.
15
Assuming VBAT is the boost input voltage, VOUTBST is the boost
output voltage and VOUT is the buck output voltage, the steady
state transfer functions are:
1
V OUTBST = -------------  VBAT
1–D
(EQ. 5)
D
V OUT = D  V OUTBST = -------------  VBAT
1–D
(EQ. 6)
From Equation 5 and Equation 6, Equation 7 can be derived to
estimate the steady state boost output voltage as a function of
VBAT and VOUT:
V OUTBST = VBAT + VOUT
(EQ. 7)
After the IC starts up, the boost buck converters can keep
working when the battery voltage drops extremely low because
the IC’s bias (VCC) LDO is powered by the boost output. For an
example of 3.3V output application, when the battery drops to
2V, the VIN pin voltage is powered by the boost output voltage
that is 5.2V (Equation 7), meaning the VIN pin (buck input) still
needs 5.2V to keep the IC working.
Note in the above mentioned case, the boost input current could
be high because the input voltage is very low
(VIN *IIN = VOUT * IOUT / Efficiency). If the design is to achieve the
low input operation with full load, the inductor and MOSFET have
to be selected to have enough current ratings to handle the high
current appearing at boost input. The boost inductor current are
the same with the boost input current, which can be estimated in
Equation 8, where POUT is the output power, VBAT is the boost
input voltage, and EFF is the estimated efficiency of the whole
boost and buck stages.
P OUT
IL IN = ----------------------------VBAT  EFF
(EQ. 8)
Based on the same concerns of boost input current, the start-up
sequence must follow the rule that the IC is enabled after the
boost input voltage rise above a certain level. The shutdown
sequence must follow the rule that the IC is disabled first before
FN7641.2
December 24, 2013
ISL78200
the boost input power source is turned off. At boost mode
applications where there is no external control signal to
enable/disable the IC, an external input UVLO circuit must be
implemented for the start-up and shutdown sequence.
ground. Use Equation 10 to calculate the resistor.
PFM is not available in boost mode.
Note that with the lower RLIM, IOC1 is higher. Considering the OC
programming circuit tolerances over temperature range -40°C to
+105°C, 71.5k is the lowest resistor value recommended to be
used for RLIM to achieve highest OC threshold. With 71.5k RLIM,
the OC limit is 4.18A (TYP). Resistor lower than 71.5k would
result in default 3.6A OC1 threshold.
Oscillator and Synchronization
The oscillator has a default frequency of 500kHz with the FS pin
connected to VCC, ground, or floating. The frequency can be
programmed to any frequency between 200kHz and 2.2MHz with
a resistor from the FS pin to GND.
145000 – 16  FS  kHz 
R FS  k  = -------------------------------------------------------------FS  kHz 
RLIM (kΩ)
270
220
170
120
1.0
2.0
3.0
IOC1 (A)
4.0
5.0
6.0
FIGURE 31. RLIM vs IOC1
With the SYNC pins simply connected together, multiple
ISL78200s can be synchronized. The slave ICs automatically
have 180° phase shift respect to the master IC.
1200
1000
800
RFS (kΩ)
320
70
0.0
When the part enters PFM pulse skipping mode, the
synchronization function is shut off and also no clock signal
output in SYNC pin.
(EQ. 10)
370
(EQ. 9)
The SYNC pin is bi-directional and it outputs the IC’s default or
programmed local clock signal when it’s free running. The IC
locks to an external clock injected to SYNC pin (external clock
frequency recommended to be 10% higher than the free running
frequency). The delay from the rising edge of the external clock
signal to the PHASE rising edge is half of the free running switching
period pulse 220ns, (0.5Tsw+220ns). The maximum external clock
frequency is recommended to be 1.6 of the free running frequency.
The second current protection threshold, IOC2, is 15% higher
than IOC1 mentioned above. At the instant the high-side MOSFET
current reaches IOC2, the PWM shuts off after a 2 cycle delay and
the IC enters hiccup mode. In hiccup mode, the PWM is disabled
for a dummy soft-start duration equal to 5 regular soft-start
periods. After this dummy soft-start cycle, the true soft-start cycle
is attempted again. The IOC2 offers a robust and reliable
protection against worst case conditions.
The frequency fold back is implemented for the ISL78200. When
overcurrent limiting, the switching frequency is reduced to
proportional to the output voltage in order to keep the inductor
current under the limit threshold during overload condition. The
low limit of frequency under frequency foldback is 40kHz.
600
400
200
0
300000
R LIM = --------------------------------------I OC  A  + 0.018
Overvoltage Protection
0
500
1000
1500
2000
2500
FS (kHz)
FIGURE 30. RFS vs FREQUENCY
Fault Protection
Overcurrent Protection
The overcurrent function protects against any overload condition
and output shorts at worst case, by monitoring the current
flowing through the upper MOSFET.
There are 2 current limiting thresholds. The first one, IOC1, is to
limit the high-side MOSFET peak current cycle-by-cycle. The
current limit threshold is set to default at 3.6A with the ILIMIT pin
connected to GND or VCC, or left open. The current limit threshold
can also be programmed by a resistor, RLIM, at the ILIMIT pin to
16
If the voltage detected on the FB pin is over 110% of reference,
the high-side and low-side drivers shut down immediately and
won’t be allowed on until the FB voltage falls down to 0.8V. When
the FB voltage drops to 0.8V, the drivers are released on. If the
120% overvoltage threshold is reached, the high-side and
low-side driver shut down immediately and the IC is latched off.
The IC has to be reset for restart.
Thermal Protection
The ISL78200 PWM will be disabled if the junction temperature
reaches +155°C. A +15°C hysteresis insures that the device will
not restart until the junction temperature drops below +140°C.
Component Selections
ISL78200 iSim model available in internet can be used to
simulate the operating behaviors to assist the design.
FN7641.2
December 24, 2013
ISL78200
Output Capacitors
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are 2 critical factors
when considering output capacitance choice. The current mode
control loop allows the usage of low ESR ceramic capacitors and
thus smaller board layout. Electrolytic and polymer capacitors
may also be used.
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings and with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturers data sheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
For the ceramic capacitors (low ESR):
I
V OUTripple = ----------------------------------8 F SW C OUT
(EQ. 11)
where I is the inductor’s peak to peak ripple current, FSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = I*ESR
(EQ. 12)
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in VOUT if the load is suddenly
removed. In this case, energy stored in the inductor will be
transferred to COUT causing its voltage to rise. After calculating
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. The following equation
determines the required output capacitor value in order to
achieve a desired overshoot relative to the regulated voltage.
I OUT 2 * L
C OUT = ------------------------------------------------------------------------------------V OUT 2 *  V OUTMAX  V OUT  2 – 1 
(EQ. 13)
Ceramic capacitors must be used at the VIN pin of the IC and
multiple capacitors including 1µF and 0.1µF are recommended.
Place these capacitors as closely as possible to the IC.
Output Inductor
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% to
40% of total load current. The inductor value can then be
calculated using Equation:
V IN – V OUT V OUT
L = ----------------------------  ------------V IN
Fs  I
(EQ. 14)
Increasing the value of inductance reduces the ripple current and
thus ripple voltage. However, the larger inductance value may
reduce the converter’s response time to a load transient. The
inductor current rating should be such that it will not saturate in
overcurrent conditions.
Low-Side Power MOSFET
In synchronous buck application, a power N MOSFET is needed
as the synchronous low-side MOSFET and a good one should
have low Qgd, low rDS(ON) and small Rg (Rg_typ < 1.5Ω
recommended). Vgth_min is recommended to be higher than 1.2V.
A good example is SQS462EN.
Output Voltage Feedback Resistor Divider
The output voltage can be programmed down to 0.8V by a
resistor divider from VOUT to FB according to Equation 15.
R UP 

V OUT = 0.8   1 + ---------------
R LOW

(EQ. 15)
In applications requiring the least input quiescent current, large
resistors should be used for the divider to keep its leakage
current low. 232k is a recommended for the upper resistor.
Loop Compensation Design
The ISL78200 uses constant frequency peak current mode
control architecture to achieve fast loop transient response. An
accurate current sensing pilot device in parallel with the upper
MOSFET is used for peak current control signal and overcurrent
protection. The inductor is not considered as a state variable
since its peak current is constant, and the system becomes
single order system. It is much easier to design the compensator
to stabilize the loop compared with voltage mode control. Peak
current mode control has inherent input voltage feed-forward
function to achieve good line regulation. Figure 32 shows the
small signal model of a buck regulator.
where VOUTMAX/VOUT is the relative maximum overshoot
allowed during the removal of the load.
Input Capacitors
Depending upon the system input power rail conditions, the
aluminum electrolytic type capacitor is normally needed to
provide the stable input voltage and restrict the switching
frequency pulse current in small areas over the input traces for
better EMC performance. The input capacitor should be able to
handle the RMS current from the switching power devices.
17
FN7641.2
December 24, 2013
ISL78200
^
iL
+
^
i in
^
Vin
ILd^
1:D
LP
RLP
Vin d^
+
RT
GAIN (VLOOP (S(fi))
S
1 + -----V in
z
Î o
F 2  S  = ---- = ----------------------- -------------------------------------R o + R LP 2
d̂
S
S
------- + -------------- + 1
2  Q
o p
o
^
vo
Rc
Ro
Co
T v  S  = KF m F 1  S A v  S 
(EQ. 22)
The Voltage loop gain with current loop closed is given by
Equation 23:
Tv (S)
He(S)
v^comp
(EQ. 21)
The voltage loop gain with open current loop is Equation 22:
Fm
+
Current loop gain Ti(S) is expressed as Equation 21:
T i  S  = R t F m F 2  S H e  S 
T i(S)
d^
(EQ. 20)
-Av(S)
FIGURE 32. SMALL SIGNAL MODEL OF BUCK REGULATOR
Tv  S 
L v  S  = ----------------------1 + Ti  S 
(EQ. 23)
If Ti(S)>>1, then Equation 23 can be simplified as Equation 24:
PWM Comparator Gain Fm:
The PWM comparator gain Fm for peak current mode control is
given by Equation 16:
1
d̂
F m = ---------------- = ----------------------------- S e + S n T s
v̂ comp
S
1 + -----------R o + R LP
 esr A v  S 
1
L v  S  = ----------------------- ---------------------- --------------- ,  p  ------------Rt
Ro C o
S H S
1 + ------- e
p
(EQ. 24)
(EQ. 16)
Where, Se is the slew rate of the slope compensation and Sn is
given by Equation 17
V in – V o
S n = R t -------------------L
Equation 24 shows that the system is a single order system.
Therefore, a simple type II compensator can be easily used to
stabilize the system. While type III compensator is needed to
expand the bandwidth for current mode control in some cases.
(EQ. 17)
P
CURRENT SAMPLING TRANSFER FUNCTION HE(S):
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function in Equation 18:
2
C1
R2
where, Rt is the gain of the current amplifier.
R3
C3
VO
VCOMP
VREF
R1
RBIAS
(EQ. 18)
S
S
H e  S  = ------- + -------------- + 1
2  Q
n n
n
where, Qn and n are given by
FIGURE 33. TYPE III COMPENSATOR
2
Q n = – ---  n = f s

A compensator with 2 zeros and 1 pole is recommended for this
part as shown in Figure 33. Its transfer function is expressed as
Equation 25:
Power Stage Transfer Functions
Transfer function F1(S) from control to output voltage is:
S
1 + ----------- esr
v̂ o
F 1  S  = ------ = V in -------------------------------------2
d̂
S
S
------- + -------------- + 1
2  Q
o p
o
(EQ. 19)
Where,
C
1
1
 esr = ------------- ,Q p  R o -----o- , o = ----------------Rc Co
LP
LP Co
Transfer function F2(S) from control to inductor current is given
by Equation 20:
1
S
S 
 1 + -----------1 + ------------

 cz2
 cz1 
v̂ comp
1
A v  S  = ---------------- = ------------------ --------------------------------------------------------SR 1 C
S 
v̂ O
 1 + --------1

 
(EQ. 25)
cp
where,
1
1
1
 cz1 = -------------- ,  cz2 = --------------------------------  cp = ------------- R 1 + R 3 C 3
R2 C1
R3 C3
Compensator design goal:
1
1
- f
Loop bandwidth fc:  --4- to -----10 s
Gain margin: >10dB
where  z = ------------Ro Co .
18
FN7641.2
December 24, 2013
ISL78200
Phase margin: 45°
The compensator design procedure is as follows:
80
1. Position CZ2 and CP to derive R3 and C3.
60
Put the compensator zero CZ2 at (1 to 3)/(RoCo)
40
(EQ. 26)
20
dB
3
 cz2 = ------------Ro Co
LOOP GAIN
0
Put the compensator pole CP at ESR zero or 0.35 to 0.5 times
of switching frequency, whichever is lower. In all-ceramic-cap
design, the ESR zero is normally higher than half of the switching
frequency. R3 and C3 can be derived as following:
-20
-40
1
Case A: ESR zero --------------------- less than (0.35 to 0.5)fs
2R c C o
R o C o – 3R c C o
C 3 = ------------------------------------3R 1
-60
100
1k
10k
100k
FREQUENCY (Hz)
1M
(EQ. 27)
PHASE MARGIN
180
3R c R 1
R 3 = ----------------------R o – 3R c
(EQ. 28)
160
140
2R c C o
0.33R o C o f s – 0.46
C 3 = ------------------------------------------------fs R
(EQ. 29)
R1
R 3 = ---------------------------------------0.73R o C o f s – 1
(EQ. 30)
1
DEGREE (°)
1
Case B: ESR zero --------------------- larger than (0.35 to 0.5)fs
120
100
80
60
40
20
Case C: Derive at R2 and C1.
0
100
The loop gain Lv(S) at cross over frequency of fc has unity gain.
Therefore, C1 is determined by Equation 31.
 R 1 + R 3 C3
C 1 = --------------------------------2f c R t R 1 C
(EQ. 31)
o
The compensator zero CZ1 can boost the phase margin and
bandwidth. To put CZ1 at 2 times of cross cover frequency fc is a
good start point. It can be adjusted according to specific design.
R1 can be derived from Equation 32.
(EQ. 32)
1
R 2 = ------------------4f c C 1
Example: VIN = 12V, Vo = 5V, Io = 2A, fs = 500kHz,
Co = 60µF/3m, L = 10µH, Rt = 0.20V/A, fc = 50kHz,
R1 = 105k, RBIAS = 20k.
Select the crossover frequency to be 35kHz. Since the output
capacitors are all ceramics, use Equation 29 and 30 to derive R3
to be 20k and C3 to be 470pF.
Then use Equation 31 and 32 to calculate C1 to be 180pF and
R2 to be 12.7k. Select 150pF for C1 and 15k for R2.
There is approximately 30pF parasitic capacitance between
COMP to FB pins that contributes to a high frequency pole.
Figure 34 shows the simulated bode plot of the loop. It is shown
that it has 26kHz loop bandwidth with 70° phase margin and
-28dB gain margin.
19
1k
10k
100k
FREQUENCY (Hz)
1M
FIGURE 34. SIMULATED LOOP BODE PLOT
Note in applications where the PFM mode is desired especially
when type III compensation network is used, the value of the
capacitor between the COMP pin and the FB pin (not the
capacitor in series with the resistor between COMP and FB)
should be minimal to reduce the noise coupling for proper PFM
operation. No external capacitor between COMP and FB is
recommended at PFM applications.
Boost Inductor
Besides the need to sustain the current ripple to be within a
certain range (30% to 50%), the boost inductor current at its
soft-start is a more important perspective to be considered in
selection of the boost inductor. Each time the boost starts up,
there is a fixed 500µs soft-start time when the duty cycle
increase linearly from tMINON to ~50%. Before and after boost
start-up, the boost output voltage will jump from VIN_boost to
voltage (VIN_boost+VOUT_buck). The design target in boost
soft-start is to ensure the boost input current is sustained to a
minimum but capable of charging the boost output voltage to
have a voltage step equaling to VOUT_buck. A big inductor will
block the inductor current increase and not high enough to be
able to charge the output capacitor to the final steady state value
(VIN_boost+VOUT_buck) within 500µs. A 6.8µH inductor is a good
starting point for its selection in design. The boost inductor
current at start-up must be checked by an oscilloscope to ensure
FN7641.2
December 24, 2013
ISL78200
it is under the acceptable range. Suggest to run the iSim model
simulation to select the proper inductor value.
Boost Output Capacitor
Based on the same theory in boost start-up described above in
boost inductor selection, a large capacitor at boost output will
cause high inrush current at boost PWM start-up. 22µF is a good
choice for applications with buck output voltage less than 10V.
Also, some minimum amount of capacitance has to be used in
boost output to keep the system stable. Suggest to run the iSim
model simulation to select the proper inductor value.
Layout Suggestions
1. Put the input ceramic capacitors as close to the IC VIN pin and
power ground connecting to the power MOSFET or diode.
Keep this loop (input ceramic capacitor, IC VIN pin and
MOSFET/diode) as tiny as possible to achieve the least
voltage spikes induced by the trace parasitic inductance.
2. Put the input aluminum capacitors close to IC VIN pin.
3. Keep the phase node copper area small but large enough to
handle the load current.
4. Put the output ceramic and aluminum capacitors also close
to the power stage components.
5. Put vias (20 recommended) in the bottom pad of the IC. The
bottom pad should be placed in the ground copper plane with
an area as large as possible in multiple layers to effectively
reduce the thermal impedance.
6. Place the 4.7µF ceramic decoupling capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias (≥3) close
to the ground pad of this capacitor.
7. Keep the bootstrap capacitor close to the IC.
8. Keep the LGATE drive trace as short as possible and try to
avoid using a via in the LGATE drive path to achieve the lowest
impedance.
9. Place the positive voltage sense trace close to the load for
tighter regulation.
10. Place all the peripheral control components close to the IC.
.
FIGURE 35. PCB VIA PATTERN
20
FN7641.2
December 24, 2013
ISL78200
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to
make sure you have the latest Rev.
DATE
REVISION
December 24, 2013
FN7641.2
Page 21
- 2nd line of the disclaimer changed from:
"Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted"
to:
"Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality
systems as noted"
May 17, 2012
FN7641.1
On page 6 - Electrical Spec Table VIN SUPPLY, changed "Standby Supply Current" to "ShutDown Supply Current"
and changed Symbol "IQ_SBY" to IIN_SD
On page 7 - Electrical Spec Table SYNCHRONIZATION, changed Symbol "VOH" to "VIL"
On page 12 - Added Efficiency Boost Buck performance Curve
Updated Equation 31 on page 19 by adding C3 to the equation, which was missing.
Deleted following sentence from last paragraph of “Power Stage Transfer Functions” on page 19: “A capacitor
(<1nF) at the FB pin to ground also helps proper PFM mode operation".
April 26, 2012
September 22, 2011
CHANGE
Added typical electrical specification of EN pull-up current and Synchronization on page 7.
Added boost-buck efficiency curve and “AUXVCC Switch-Over” on page 13.
Under “Output Voltage” on page 14 description, changed “(1/Fs tMINOFF)” To “ (1 - Fs * tMIN(OFF))”.
Under “Boost Converter Operation” on page 14, changed "(VIN*IIN = VOUT*IOUT*Efficiency)" to "(VIN*IIN =
VOUT*IOUT/Efficiency)".
Added recommendation of the maximum programmable OC threshold to be 4.18A(TYP) with 71.5k RLIM on
page 16.
Added to “Component Selections” on page 16 application design guides for selection of inductor and capacitor
and loop compensation.
FN7641.0
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN7641.2
December 24, 2013
ISL78200
HTSSOP (Heat-Sink TSSOP) Family
MDP0048
0.25 M C A B
D
HTSSOP (HEAT-SINK TSSOP) FAMILY
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE
PIN #1 I.D.
E
E1
0.20 C B A
1
2X
N/2 LEAD TIPS
(N/2)
TOP VIEW
B
D1
EXPOSED
THERMAL PAD
E2
1.20
1.20
1.20
1.20
Max
0.075
0.075
0.075
0.075
±0.075
A2
0.90
0.90
0.90
0.90
0.90
+0.15/-0.10
b
0.25
0.25
0.25
0.25
0.22
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
6.50
7.80
9.70
9.70
±0.10
D1
3.2
4.2
4.3
5.0
7.25
Reference
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
E2
3.0
3.0
3.0
3.0
3.0
Reference
e
0.65
0.65
0.65
0.65
0.50
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
N
14
20
24
28
38
Reference
NOTES:
0.05
e
1.20
0.075
Rev. 3 2/07
BOTTOM VIEW
C
A
A1
H
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEATING
PLANE
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
SEE DETAIL “X”
c
END VIEW
L1
A A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
22
FN7641.2
December 24, 2013