HC55171B Data Sheet July 1998 Low Cost 5 REN Ringing SLIC for ISDN Modem/TA and WL File Number 4422.1 Features • Load Drive Capability . . . . . . . . . . . . . . . . . . . . . . . 5 REN The HC55171B low cost, 5 REN ringing SLIC is designed to accommodate a wide variety of short loop applications and provides the same degree of flexibility as the high performance HC55171. The flexible features include open circuit tip to ring DC voltages, user defined ringing waveforms, ring trip detection thresholds, and loop current limits that can be tailored for many applications. Additional features of the HC55171B are complex impedance matching, pulse metering, and transhybrid balance. The HC55171B is designed for use in short loop, low cost systems where traditional ring generation is not economically feasible. • Trapezoidal, Square or Sine Wave Capability • Ringing from -80V Battery . . . . . . . . . . . . . . . . . . . 75VP-P • Ringing from -75V Battery . . . . . . . . . . . . . . . . . . . 70VP-P • Ringing Current Independent of Loop Current Setting • Ringing Crest Factor Independent of REN Loading • Latchup Immune to Inductive Kick Back and Hot Plug • Fax, Answering Machine and MTU Compatible • Resistive and Complex Impedance Matching • Programmable Loop Current Limit The device is manufactured in a high voltage Dielectric Isolation (DI) process. The DI process provides substrate latch up immunity, resulting in a robust system design. A thermal shutdown with an alarm output and line fault protection are also included for operation in harsh environments. • Switch Hook, Ring Trip and Ground Key Detection • Single Low Voltage +5V Supply Applications • Solid State Line Interface Circuit for Hybrid Fiber Coax, Set Top Box, Voice/Data Modems Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE • Related Literature - AN9607, Impedance Matching Design Equations - AN9628, AC Voltage Gain - AN9636, Implementing an Analog Port for ISDN - AN549, The HC-5502/4X Telephone SLIC PKG. NO. HC55171BIM -40 to 85 28 Ld PLCC N28.45 HC55171BIB -40 to 85 28 Ld SOIC M28.3 Block Diagram TIP FEED TIP SENSE RING FEED VRX 4-WIRE INTERFACE 2-WIRE INTERFACE LOOP CURRENT DETECTOR RING SENSE 1 VTX VRING - - IN 1 + FAULT DETECTOR RING SENSE 2 VREF OUT 1 CURRENT LIMIT RTI VBAT SHD ALM ILIMIT RING TRIP DETECTOR VCC BIAS RTD AGND IIL LOGIC INTERFACE BGND F1 63 F0 RS TST RELAY DRIVER RDO RDI CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HC55171B Absolute Maximum Ratings TA = 25oC Thermal Information Maximum Supply Voltages (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V (VCC)-(VBAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90V Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +15V Operating Conditions Temperature Range HC55171BIM, HC55171BIB . . . . . . . . . . . . . . . . . . -40oC to 85oC Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +12V Positive Power Supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Negative Power Supply (VBAT). . . . . . . . . . . . . . . . . . . -16V to -80V Thermal Resistance (Typical, Note 1) θJA (oC/W) PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature, Plastic Packages . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC, PLCC - Lead Tips Only) Die Characteristics Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Diode Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 x 144 Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBAT Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTES: 1. θJA is measured with the component mounted on an evaluation board PC board in free air. 2. All grounds (AGND, BGND) must be applied before VCC or VBAT . Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AGND must be applied first. Electrical Specifications Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600Ω 2-Wire terminating impedance. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS RINGING TRANSMISSION PARAMETERS VRING Input Impedance (Note 3) - 5.4 - kΩ 4-Wire to 2-Wire Gain VRING to VT-R (Note 3) - 40 - V/V RX Input Impedance 300Hz to 3.4kHz (Note 3) - 108 - kΩ OUT1 Positive Output Voltage Swing RL = 10kΩ (Note 3) +2.5 - - V OUT1 Negative Output Voltage Swing RL = 10kΩ (Note 3) -4.5 - - V 4-Wire Input Overload Level 300Hz to 3.4kHz RL = 1200Ω, 600Ω Reference (Note 3) - +3.1 - VPEAK 2-Wire Return Loss Matched for 600Ω, f = 300Hz (Note 3) 37 - - dB Matched for 600Ω, f = 1000Hz (Note 3) 40 - - dB Matched for 600Ω, f = 3400Hz (Note 3) 30 - - dB 2-Wire Longitudinal to Metallic Balance Off Hook Per ANSI/IEEE STD 455-1976 300Hz to 3400Hz (Note 3) 40 - - dB 4-Wire Longitudinal Balance Off Hook 300Hz to 3400Hz (Note 3) 40 - - dB Longitudinal Current Capability ILINE = 40mA, TA = 25oC (Note 3) - 40 - mARMS Insertion Loss, 2-Wire to 4-Wire 0dBmO, 1kHz, Includes Transhybrid Amp Gain = 3 - ±0.05 ±0.2 dB Insertion Loss, 4-Wire to 2-Wire 0dBmO,1kHz - ±0.05 ±0.2 dB Insertion Loss, 4-Wire to 4-Wire 0dBmO, 1kHz, Includes Transhybrid Amp Gain = 3 - - ±0.35 dB Frequency Response 300Hz to 3400Hz Referenced to Absolute Level at 1kHz, 0dBm Referenced 600Ω - ±0.02 ±0.06 dB AC TRANSMISSION PARAMETERS 64 HC55171B Electrical Specifications Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600Ω 2-Wire terminating impedance. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS +3 to 0dBm, Referenced to -10dBm (Note 3) - - ±0.10 dB 0 to -40dBm, Referenced to -10dBm (Note 3) - - ±0.12 dB -40 to -55dBm, Referenced to -10dBm (Note 3) - - ±0.30 dB Absolute Delay, 2-Wire to 4-Wire 300Hz to 3400Hz (Note 3) - - 1.0 µs Absolute Delay, 4-Wire to 2-Wire 300Hz to 3400Hz (Note 3) - - 1.0 µs Absolute Delay, 4-Wire to 4-Wire 300Hz to 3400Hz (Note 3) - 0.95 - µs Transhybrid Loss VIN = 1VP-P at 1kH (Note 3) 36 40 - dB Total Harmonic Distortion 2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire Reference Level 0dBm at 600Ω 300Hz to 3400Hz (Note 3) - - -50 dB Idle Channel Noise 2-Wire and 4-Wire C-Message (Note 3) - 3 - dBrnC Psophometric (Note 3) - -87 - dBmp 30 35 - dB PSRR, VCC to 4-Wire 45 47 - dB PSRR, VBAT to 2-Wire 23 28 - dB PSRR, VBAT to 4-Wire 33 38 - dB 33 35 - dB PSRR, VCC to 4-Wire 44 46 - dB PSRR, VBAT to 2-Wire 40 50 - dB PSRR, VBAT to 4-Wire 50 60 - dB 30 34 - dB PSRR, VCC to 4-Wire 35 40 - dB PSRR, VBAT to 2-Wire 30 40 - dB PSRR, VBAT to 4-Wire 40 50 - dB 20 - 60 mA -15 - +15 % Level Linearity PSRR, VCC to 2-Wire 30Hz to 200Hz, RL = 600Ω (Note 3) PSRR, VCC to 2-Wire 200Hz to 3.4kHz, RL = 600Ω (Note 3) PSRR, VCC to 2-Wire 3.4kHz to 16kHz, RL = 600Ω (Note 3) DC PARAMETERS Loop Current Programming Range (Note 4) Loop Current Programming Accuracy Loop Current During Power Denial RL = 200Ω, VBAT = -48V - ±4 - mA Fault Current, Tip to Ground (Note 3) - 90 - mA - 100 - mA - 130 - mA 9 12 15 mA -0.28 -0.24 -0.22 V 140 - 160 oC - 0.1 0.5 ms Fault Current, Ring to Ground Fault Current, Tip and Ring to Ground (Note 3) Switch Hook Detection Threshold Ring Trip Comparator Voltage Threshold Thermal ALARM Output Safe Operating Die Temperature Exceeded (Note 3) Dial Pulse Distortion (Note 3) 65 HC55171B Electrical Specifications Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600Ω 2-Wire terminating impedance. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 0.2 0.5 V - ±10 ±100 µA Logic Low Input Voltage 0 - 0.8 V Logic High Input Voltage 2.0 - 5.5 V UNCOMMITTED RELAY DRIVER On Voltage, VOL IOL (RDO) = 30mA Off Leakage Current TTL/CMOS LOGIC INPUTS (F0, F1, RS, TST, RDI) Input Current IIH , 0V ≤ VIN ≤ 5V - - -1 µA Input Current IIL , 0V ≤ VIN ≤ 5V - - -100 µA Logic Low Output Voltage ILOAD = 800µA - 0.3 0.6 V Logic High Output Voltage ILOAD = 40µA 2.7 - 5.5 V - - - LOGIC OUTPUTS (SHD, RTD, ALM) POWER DISSIPATION Power Dissipation On Hook VCC = +5V, VBAT = -80V, RLOOP = ∞ - 300 - mW VCC = +5V, VBAT = -48V, RLOOP = ∞ - 150 - mW - 280 - mW Power Dissipation Off Hook VCC = +5V, VBAT = -24V, RLOOP = 600Ω, IL = 25mA ICC VCC = +5V, VBAT = -80V, RLOOP = ∞ - 3 6 mA VCC = +5V, VBAT = -48V, RLOOP = ∞ - 2 5 mA VCC = +5V, VBAT = -24V, RLOOP = ∞ - 1.9 5 mA IBAT VCC = +5V, VB- = -80V, RLOOP = ∞ - 3.6 7 mA VCC = +5V, VB- = -48V, RLOOP = ∞ - 2.6 6 mA VCC = +5V, VB- = -24V, RLOOP = ∞ - 2.3 4.5 mA NOTES: 3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. 4. This parameter directly affects device junction temperature. Refer to Power Dissipation discussion of data sheet for design information. 66 HC55171B R TF 25 TF VRX 17 R + OUT 1 -IN 1 12 R 13 + VRING VTX 24 VCC 19 AGND 1 2 BIAS NETWORK OP AMP R/2 22 27 +2V BGND VBAT R/20 R TIP SENSE - 5 TA R + R 2R SH SHD THERM LTD 4.5K 25K 100K RING SENSE 1 RING SENSE 2 100K 15 16 TSD + 100K 25K GK RTD RA 100K 6 IIL LOGIC INTERFACE R 14 4 2R 7 8 RFC 90K RF 26 10 - GM 90K + R = 108kΩ VB/2 REF 3 VREF 18 NU HC55171B DEVICE TRUTH TABLE F1 F0 STATE 0 0 Loop power Denial Active 0 1 Power Down Latch RESET, Power on RESET 1 0 RD Active (unbalanced ringing) 1 1 Normal Loop feed The truth table for the internal logic of the HC55171B is provided in the above table. This family of ringing SLICs can be configured to support traditional unbalanced ringing and through SLIC balanced ringing. The device operating states used by through SLIC ringing applications are loop power denial and normal feed. During loop power denial, the tip and ring amplifiers are disabled (high impedance) and the DC voltage of each amplifier approaches ground. The SLIC will not provide current to the subscriber loop during this mode and will not detect loop closure. Voice transmission occurs during the normal loop feed mode. During normal loop feed the SLIC is completely operational and performs all transmission and supervisory functions. 67 11 28 RTI 21 RF2 + ILIMIT RS TST 90K RF F0 9 FAULT DET 4.5K F1 SHD RTD ALM RDO 20 RDI Power Dissipation Careful thermal design is required to guarantee that the maximum junction temperature of 150oC of the device is not exceeded. The junction temperature of the SLIC can be calculated using: 2 T J = T A + θ JA ( I CC V CC + I BAT V BAT – ( ( I LOOP ) • R LOOP ) ) (EQ. 1) Where TA is maximum ambient temperature and θJA is junction to air thermal resistance (and is package dependent). The entire term in parentheses yields the SLIC power dissipation. The power dissipation of the subscriber loop does not contribute to device junction temperature and is subtracted from the power dissipation term. Operating at 85oC, the maximum PLCC SLIC power dissipation is 1.18W. Likewise, the maximum SOIC SLIC power dissipation is 0.92W. HC55171B Circuit Operation and Design Information SLIC DESIGN EQUATIONS FUNCTION EQUATION DEFINITION OF TERMS 2-Wire to 4-Wire Gain V OUT1 200 R ZO ------------------- = – ----------- ⋅ -----------Z R V 2W 2w RF 4-Wire To 2-wire Gain Z 2W V 2W ------------ = – 2 ⋅ ----------------------------------- Z V RX 2W + Z SLIC V2W = Voltage Across 2-Wire Load VRX = SLIC 4-Wire Input Z2W = 2-Wire Impedance ZSLIC = SLIC Synthesized Impedance Z 2W V OUT1 200 R ZO ------------------- = – 2 ⋅ ----------------------------------- ⋅ ------------ ⋅ -----------V RX Z 2W + Z SLIC Z 2W R RF VOUT1 = SLIC 4-Wire Output VRX = SLIC 4-Wire Input Z2W = 2-Wire Impedance ZSLIC = SLIC Synthesized Impedance 4-Wire To 4-wire Gain Loop Current Limit Programming Impedance Matching VOUT1 = SLIC 4-wire Output V2w = Voltage across 2-wire load Z2W = 2-Wire Impedance ( 0.6 ) ( R IL1 + R IL2 ) I LIMIT = -------------------------------------------------( 200xR IL2 ) ILIMIT = Programmed Loop Current Limit RIL1 = Programming Resistor RIL2 = Programming Resistor Z2W = 2-Wire Impedance K = 100 R ZO = K ⋅ ( Z 2W – 100 ) R RF = K ⋅ 200 ⋅ 2 Through SLIC Ringing Crest Factor Programming The HC55171B uses linear amplification to produce the ringing signal. As a result the ringing SLIC can produce sinusoid, trapezoid or square wave ringing signals. Regardless of the wave shape, the ringing signal is balanced. The balanced waveform is another way of saying that the tip and ring DC potentials are the same during ringing. As previously mentioned, a single resistor is required to set the crest factor of the trapezoidal waveform. The only design variable in determining the crest factor is the battery voltage. The battery voltage limits the peak signal swing and therefore directly determines the crest factor. Trapezoidal Ringing The trapezoidal ringing waveform provides a larger RMS voltage to the handset. Larger RMS voltages to the handset provide more power for ringing and also increase the loop length supported by the ringing SLIC. One set of component values will satisfy the entire ringing loop range of the SLIC. A single resistor sets the open circuit RMS ringing voltage, which will set the crest factor of the ringing waveform. The crest factor of the HC55171B ringing waveform is independent of the ringing load (REN) and the loop length. Another robust feature of the HC55171B ringing SLIC is the ring trip detector circuit. The suggested values for the ring trip detector circuit cover quite a large range of applications. The assumptions used to design the trapezoidal ringing application circuit are listed below: • Loop current limit set to 25mA. A set of tables will be provided to allow selection of the crest factor setting resistor. The tables will include crest factors below the Bellcore minimum of 1.2 since many ringing SLIC applications are not constrained by Bellcore requirements. TABLE 1. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -80V RTRAP CF RMS RTRAP CF RMS 0Ω 1.10 65.0 825Ω 1.25 57.6 389Ω 1.15 62.6 964Ω 1.30 55.4 640Ω 1.20 60.0 1095Ω 1.35 53.3 The RMS voltage listed in the table is the open circuit RMS voltage generated by the SLIC. TABLE 2. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -75V RTRAP CF RMS RTRAP CF RMS • 2-wire surge protection is not required. 0Ω 1.10 60.9 1010Ω 1.25 53.7 • System able to monitor RTD and SHD. 500Ω 1.15 58.3 1190Ω 1.30 51.6 Logic ringing signal is used to drive RC trapezoid network. 791Ω 1.20 55.9 1334Ω 1.35 49.7 • Impedance matching is set to 600Ω resistive. 68 HC55171B TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -65V RTRAP CF RMS RTRAP CF RMS 0Ω 1.10 52.5 1330Ω 1.25 45.9 660Ω 1.15 49.8 1600Ω 1.30 44.1 1040Ω 1.20 47.8 1800Ω 1.35 42.5 interface). Figure 2 shows the control interface for the dual detector interface and the single detector interface. HC55171B ADDITIONAL PULL UP RESISTOR VCC NU 23 RDI 20 RDO 21 TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -60V RTRAP CF RMS RTRAP CF RMS 0Ω 1.10 48.2 1460Ω 1.25 42.0 740Ω 1.15 45.6 1760Ω 1.30 40.4 1129Ω 1.20 43.7 2030Ω 1.35 38.8 The voltages listed in the tables are driven from a logic source that will not drive the ringing input negative. If the ringing input is driven negative by 200mV, the peak-to-peak ringing amplitudes can be increased. Ringing Voltage Limiting Factors As the load impedance decreases (increasing REN), the source impedance of the SLIC during ringing slightly attenuates the ringing signal. If additional surge protection resistance must be used with the trapezoidal circuit, the loop length performance of the circuit will decrease proportionally to the added resistance in the Tip and Ring leads. For example if 30Ω protection resistors is used in each of the Tip and Ring leads, the ringing loop length will decrease by a total of 60Ω. Low Level Ringing Interface RTRAP VRING VRING 24 DTRAP CTRAP FIGURE 1. APPLICATION CIRCUIT WIRING FOR SINGLE LOOP DETECTOR INTERFACE (DUAL DETECTOR INTERFACE) MODE ACTIVE ACTIVE RINGING (LOGIC HI) F1 (LOGIC HI) F0 VRING VALID DET SHD SHD RTD (SINGLE DETECTOR INTERFACE) MODE ACTIVE ACTIVE RINGING (LOGIC HI) F1 (LOGIC HI) F0 VRING The trapezoidal application circuit only requires a cadenced logic signal applied to the wave shaping RC network to achieve ringing. When not ringing, the logic signal should be held low. When the logic signal is low, Tip will be near ground and Ring will be near battery. When the logic signal is high, Tip will be near battery and Ring will be near ground. Additional Application Information Loop Detector Interface Transhybrid Balance The RTD output should be monitored for off hook detection during the ringing period. At all other times, the SHD should be monitored for off hook detection. The application circuit can be modified to redirect the ring trip information through the SHD interface. The change can be made by rewiring the application circuit, adding a pullup resistor to pin 23 and setting F0 low for the entire duration of the ringing period. The modifications to the application circuit for the single detector interface are shown in Figure 1. Since the receive signal and its echo are 180 degrees out of phase, the summing node of an operational amplifier can be used to cancel the echo. Nearly all CODECs have an internal amplifier for echo cancellation. The circuit in Figure 3 shows the cancellation amplifier circuit. VALID DET SHD FIGURE 2. DETECTOR LOGIC INTERFACES RA The SLIC control pin F1 should always be a logic high during ringing. The control pin F0 will either be a constant logic high (two detector interface) or a logic low (single detector 69 RF VRX RB VOUT1 SLIC Operating State During Ringing SHD SHD - + VO FIGURE 3. TRANSHYBRID AMPLIFIER CIRCUIT HC55171B When the SLIC is matched to a 600Ω load and only the sense resistors are used, the 4-wire to 4-wire gain is equal to 5/12 as predicted by the design equations. Therefore, by configuring the transhybrid amplifier with a gain of 2.4 in the echo path, cancellation can be achieved. The following equations: R F R F V O = – V RX -------- + V OUT1 -------- R A R B (EQ. 2) Layout Guidelines and Considerations Substituting the fact that VOUT1 is -5/12 of VRX: R F 5 R F V O = – V RX -------- – V RX – ------ -------- R 12 R A B (EQ. 3) Since cancellation implies that under these conditions, the output VO should be zero, set Equation 2 equal to zero and solve for RB . RA R B = -------2.4 (EQ. 4) Another outcome of the transhybrid gain selection is the 2-wire to 4-wire gain of the SLIC as seen by the CODEC. The 5/12 voltage gain in the transmit path is relevant to the receive input as well as any signals from the 2-wire side. Therefore by setting the VOUT1 gain to 2.4 in the previous analysis, the 2-wire to 4-wire gain was set to unity. Single Supply CODEC Interface The majority of CODECs that interface to the ringing SLIC operate from a single +5V supply and ground. Figure 4 shows the circuitry required to properly interface the ringing SLIC to the single supply CODEC. CODEC VRX RX OUT RA RF RB - + TX IN VOUT1 +2.5V HC5517B + - FIGURE 4. SINGLE SUPPLY CODEC INTERFACE 70 The CODEC signal names may vary from different manufacturers, but the function provided will be the same. The DC reference from the CODEC is used to bias the analog signals between +5V and ground. The capacitors are required so that the DC gain is unity for proper biasing from the CODEC reference. Also, the capacitors block DC signals that may interfere with SLIC or CODEC operation. The printed circuit board trace length to all high impedance nodes should be kept as short as possible. Minimizing length will reduce the risk of noise or other unwanted signal pickup. The short lead length also applies to all high gain inputs. The set of circuit nodes that can be categorized as such are: • • • • VRX pin 27, the 4-wire voice input (low gain input). -IN1 pin 13, the inverting input of the internal amplifier. VREF pin 3, the noninverting input to ring feed amplifier. VRING pin 24, the 20V/V input for the ringing signal. For multi layer boards, the traces connected to tip should not cross the traces connected to ring. Since they will be carrying high voltages, and could be subject to lightning or surge depending on the application, using a larger than minimum trace width is advised. The 4-wire transmit and receive signal paths should not cross. The receive path is any trace associated with the VRX input and the transmit path is any trace associated with VTX output. The physical distance between the two signal paths should be maximized to reduce crosstalk, or separated by a ground trace. The operating mode control signals and detector outputs should be routed away from the analog circuitry. Though the digital signals are nearly static, care should be taken to minimize coupling of the sharp digital edges to the analog signals. The part has two ground pins, one is labeled AGND and the other BGND. Both pins should be connected together as close as possible to the SLIC. If a ground plane is available, then both AGND and BGND should be connected directly to the ground plane. A ground plane that provides a low impedance return path for the supply currents should be used. A ground plane provides isolation between analog and digital signals. If the layout density does not accommodate a ground plane, a single point grounding scheme should be used. HC55171B Pin Descriptions PLCC SYMBOL DESCRIPTION 1 AGND 2 VCC Positive Voltage Source - Most Positive Supply. 3 VREF An external voltage connected to this pin will override the internal VBAT/2 reference. 4 F1 Power Denial - An active low TTL compatible logic control input. When enabled, the output of the ring amplifier will ramp close to the output voltage of the tip amplifier. 5 F0 TTL compatible logic control input that must be tied high for proper SLIC operation. 6 RS TTL compatible logic control input that must be tied high for proper SLIC operation. 7 SHD Switch Hook Detection - An active low TTL compatible logic output. Indicates an off-hook condition. 8 RTD Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the phone is ringing. 9 TST A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin in conjunction with the ALM pin can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a system controller that monitors the ALM pin. When the ALM pin is active (low) the system controller issues a command to the TST pin (low) to power down the SLIC. The timing of the thermal recovery is controlled by the system controller. 10 ALM A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die temperature has been exceeded. 11 ILMT Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions. 12 OUT1 The analog output of the spare operational amplifier. 13 -IN1 The inverting analog input of the spare operational amplifier. The non-inverting input is internally connected to AGND. 14 TIP SENSE An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor. Functions with the RING terminal to receive voice signals and for loop monitoring purpose. 15 RING SENSE 1 An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions with the TIP terminal to receive voice signals and for loop monitoring purposes. 16 RING SENSE 2 This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation. 17 VRX Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed and Ring Feed amplifiers deferentially. 18 NU Not used in this application. This pin should be left floating. 19 VTX Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP and RING. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is necessary. 20 RDI TTL compatible input to drive the uncommitted relay driver. 21 RDO This is the output of the uncommitted relay driver. 22 BGND 23 NU 24 VRING 25 TF This is the output of the tip amplifier. 26 RF This is the output of the ring amplifier. 27 VBAT 28 RTI Analog Ground - Serves as a reference for the transmit output and receive input terminals. Battery Ground - All loop current and some quiescent current flows into this terminal. Not used in this application. This pin should be either grounded or left floating. Ring signal input. The negative battery source. Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection. 71 HC55171B Pinouts 3 1 28 VBAT RTI AGND VCC 2 27 HC55171B (SOIC) TOP VIEW RF 4 VREF F1 HC55171B (PLCC) TOP VIEW AGND 1 26 VCC 2 26 RF F1 4 25 TF 24 VRING F0 5 24 VRING 7 23 NU RS 6 23 NU 8 22 BGND SHD 7 22 BGND 21 RDO RTD 8 21 RDO TST 9 20 RDI ALM 10 19 VTX ILIMIT 11 18 NU OUT 1 12 17 VRX 5 25 TF RS 6 SHD RTD ALM 27 VBAT VREF 3 F0 TST 28 RTI 9 20 RDI 10 ILIMIT 11 12 13 14 15 16 17 18 OUT 1 -IN 1 TIP SENSE RING SENSE 1 RING SENSE 2 VRX NU 19 VTX -IN 1 13 16 RING SENSE 2 TIP SENSE 14 15 RING SENSE 1 Trapezoidal Ringing Application Circuit U1 HC55171B 14 TIP RS1 25 26 16 TIP SENSE VRX CRX 17 V-REC TF ILIMIT RIL2 11 RF RING SENSE 2 VTX RIL1 19 RS2 CAC 15 RING RING SENSE 1 -IN1 2 VCC CPS1 CPS2 VBAT 15 OUT1 AGND RTI 4 5 F0 VCC TST 6 9 20 V-XMIT RRT2 28 RRT3 VBAT VRING F1 RZO 12 VCC 22 BGND 27 RRF 13 VREF RRT1 CRT RTRAP 24 3 VRING CIL DTRAP CTRAP F1 F0 SHD RS RTD TST ALM 7 8 10 RDI FIGURE 5. TRAPEZOIDAL RINGING APPLICATION CIRCUIT 72 DRT SHD RTD ALM HC55171B HC5517B Trapezoidal Ringing Application Circuit Parts List COMPONENT VALUE TOLERANCE RATING U1 - Ringing SLIC HC55171B N/A N/A RS1, RS2 49.9Ω 1% RZO , RIL1 56.2kΩ RRT1 RRT2 RRT3 RRF 49.9kΩ 1.5MΩ 51.1kΩ 45.3kΩ COMPONENT VALUE TOLERANCE RATING RIL2 7.68kΩ 1% 1/ W 8 1/ W 2 RTRAP User-Defined 1% 1/ W 8 1% 1/ W 8 CPS1 , CPS2 0.1µF 10% 100V 1% 1/ W 8 CIL , CRT , CAC , CRX 0.47µF 10% 50V 1% 1/ W 8 CTRAP 4.7µF 10% 10V 1% 1/ W 8 DRT , DTRAP 1N914 1% 1/ W 8 Generic Rectifier Diode All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. 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