LTC3769 60V Low IQ Synchronous Boost Controller FEATURES DESCRIPTION Synchronous Operation for Highest Efficiency and Reduced Heat Dissipation n Wide V Range: 4.5V to 60V (65V Abs Max); IN Operates Down to 2.3V After Start-Up n Output Voltage Up to 60V n ±1% 1.200V Reference Voltage n R SENSE or Inductor DCR Current Sensing n 100% Duty Cycle Capability for Synchronous MOSFET n Low Quiescent Current: 28μA n Phase-Lockable Frequency (75kHz to 850kHz) n Programmable Fixed Frequency (50kHz to 900kHz) n Power Good Output Voltage Monitor n Low Shutdown Current: 4µA n Internal LDO Powers Gate Drive from VBIAS or EXTV CC n Thermally Enhanced Low Profile 24-Pin 4mm × 4mm QFN Package and 20-Lead TSSOP Package The LTC®3769 is a high performance single output synchronous boost converter controller that drives an all N-channel power MOSFET stage. Synchronous rectification increases efficiency, reduces power losses and eases thermal requirements, simplifying high power boost applications. The 28µA no-load quiescent current extends operating run time in battery-powered systems. n APPLICATIONS A 4.5V to 60V input supply range encompasses a wide range of system architectures and battery chemistries. When biased from the output of the boost converter or another auxiliary supply, the LTC3769 can operate from an input supply as low as 2.3V after start-up. The operating frequency can be set within a 50kHz to 900kHz range or synchronized to an external clock using the internal PLL. The SS pin ramps the output voltage during start-up. The PLLIN/MODE pin selects Burst Mode® operation, pulseskipping mode or forced continuous mode at light loads. L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U. S. Patents, including 5408150, 5481178, 5705919, 5929620, 6177787, 6498466, 6580258, 6611131. Industrial nAutomotive nMedical nMilitary n TYPICAL APPLICATION 120W, 12V to 24V/5A Synchronous Boost Converter 4mΩ 22µF VBIAS 10nF 15nF 8.66K 220µF RUN SENSE+ SS SENSE– LTC3769 BG TG PLLIN/MODE FREQ 10 90 1 EFFICIENCY VOUT FOLLOWS VIN FOR VIN > 24V ITH 100pF 100 VOUT 24V/5A 80 70 POWER LOSS 0.1 60 POWER LOSS (W) DOWN TO 2.3V AFTER START-UP IF VBIAS IS POWERED FROM VOUT 3.3µH EFFICIENCY (%) VIN 4.5V TO 60V Efficiency and Power Loss vs Output Current 0.01 SW 50 0.1µF BOOST 40 0.0001 OVMODE INTVCC ILIM 4.7µF 232k 0.1 1 0.001 0.01 OUTPUT CURRENT (A) 10 0.001 3769 TA01b VFB PGOOD GND EXTVCC 12.1k 3769 TA01a 3769fa For more information www.linear.com/LTC3769 1 LTC3769 ABSOLUTE MAXIMUM RATINGS (Notes 1, 3) VBIAS......................................................... –0.3V to 65V BOOST.........................................................–0.3V to 71V SW................................................................. –5V to 65V RUN.............................................................. –0.3V to 8V Maximum Current Sourced into Pin From Source >8V...............................................100µA PGOOD, PLLIN/MODE .................................. –0.3V to 6V INTVCC, (BOOST - SW)...................................–0.3V to 6V EXTVCC....................................................... –0.3V to 14V SENSE+, SENSE–......................................... –0.3V to 65V (SENSE+ - SENSE–).............................................–0.3V to 0.3V ILIM, SS, ITH, FREQ, PHASMD, VFB...... –0.3V to INTVCC Operating Junction Temperature Range (Note 2).........................................–55°C to 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) SSOP......... 300°C PIN CONFIGURATION PLLIN/MODE 5 RUN 6 SS 7 14 TG SENSE– 8 13 SW SENSE+ 9 12 OVMODE 21 GND VFB 10 16 ITH 25 GND NC 4 15 VFB INTVCC 5 14 SENSE+ NC 6 13 SENSE– 11 ITH FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 38°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB 17 OVMODE ILIM 3 16 BG 15 BOOST TG 17 INTVCC BOOST 4 18 SW PGOOD 2 7 8 9 10 11 12 SS GND BG 18 EXTVCC RUN 3 INTVCC FREQ 24 23 22 21 20 19 VBIAS 1 GND 19 VBIAS PLLIN/MODE 20 PGOOD 2 GND 1 FREQ ILIM INTVCC GND TOP VIEW EXTVCC TOP VIEW UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 47°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3769EUF#PBF LTC3769EUF#TRPBF 3769 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C LTC3769IUF#PBF LTC3769IUF#TRPBF 3769 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C LTC3769HUF#PBF LTC3769HUF#TRPBF 3769 24-Lead (4mm × 4mm) Plastic QFN –40°C to 150°C LTC3769MPUF#PBF LTC3769MPUF#TRPBF 3769 24-Lead (4mm × 4mm) Plastic QFN –55°C to 150°C LTC3769EFE#PBF LTC3769EFE#TRPBF LTC3769FE 20-Lead Plastic SSOP –40°C to 125°C LTC3769IFE#PBF LTC3769IFE#TRPBF LTC3769FE 20-Lead Plastic SSOP –40°C to 125°C LTC3769HFE#PBF LTC3769HFE#TRPBF LTC3769FE 20-Lead Plastic SSOP –40°C to 150°C LTC3769MPFE#PBF LTC3769MPFE#TRPBF LTC3769FE 20-Lead Plastic SSOP –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3769fa 2 For more information www.linear.com/LTC3769 LTC3769 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = 12V, unless otherwise noted (Note 2). SYMBOL PARAMETER CONDITIONS Main Control Loop VBIAS Chip Bias Voltage Operating Range SENSE Pins Common Mode Range (BOOST VIN Converter Input Supply Voltage) Regulated Output Voltage Range VOUT Regulated Feedback Voltage VFB Feedback Current Reference Line Voltage Regulation Output Voltage Load Regulation (Note 4) IQ Error Amplifier Transconductance Input DC Supply Current (VBIAS Pin) Pulse-Skipping or Forced Continuous Mode Sleep Mode Shutdown SW Pin Current UVLO INTVCC Undervoltage Lockout Thresholds VRUN VSENSE(MAX) RUN Pin ON Threshold RUN Pin Hysteresis RUN Pin Hysteresis Current RUN Pin Current Soft-Start Charge Current Maximum Current Sense Threshold tON(MIN) SENSE+ Pin Current SENSE– Pin Current Top Gate Rise Time Top Gate Fall Time Bottom Gate Rise Time Bottom Gate Fall Time Top Gate Pull-Up Resistance Top Gate Pull-Down Resistance Bottom Gate Pull-Up Resistance Bottom Gate Pull-Down Resistance Top Gate Off to Bottom Gate On Switch-On Delay Time Bottom Gate Off to Top Gate On Switch-On Delay Time Maximum BG Duty Factor Minimum BG On-Time MIN TYP 4.5 2.3 ITH = 1.2V (Note 4) (Note 4) VBIAS = 6V to 60V Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ΔITH Voltage = 1.2V to 2V ITH = 1.2V (Note 5) RUN = 5V; VFB = 1.25V (No Load) RUN = 5V; VFB = 1.25V (No Load) RUN = 0V VSW = 12V; VBOOST = 16.5V; FREQ = 0V, Forced Continuous or Pulse-Skipping Mode VINTVCC Ramping Up VINTVCC Ramping Down VRUN Rising 60 60 UNITS V V l 1.200 ±5 0.002 0.01 60V 1.212 ±50 0.02 0.1 V V nA %/V % l –0.01 –0.1 % l VIN 1.188 MAX 2 0.9 28 4 700 45 10 CLOAD = 3300pF (Each Driver) 20 20 20 20 1.2 1.2 1.2 1.2 30 CLOAD = 3300pF (Each Driver) 30 ns (Note 7) 96 110 % ns VRUN > 1.28V VRUN < 1.28V VSS = GND VFB = 1.1V, ILIM = INTVCC VFB = 1.1V, ILIM = Float VFB = 1.1V, ILIM = GND VFB = 1.1V, ILIM = Float VFB = 1.1V, ILIM = Float CLOAD = 3300pF (Note 6) CLOAD = 3300pF (Note 6) CLOAD = 3300pF (Note 6) CLOAD = 3300pF (Note 6) l 3.6 1.18 l l l 7 90 68 42 4.3 mA µA µA µA V V V mV µA µA µA mV mV mV µA µA ns ns ns ns Ω Ω Ω Ω ns l l 4.1 3.8 1.28 100 4.5 0.5 10 100 75 50 200 mmho 1.38 13 110 82 56 300 ±1 3769fa For more information www.linear.com/LTC3769 3 LTC3769 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = 12V, unless otherwise noted (Note 2). SYMBOL PARAMETER INTVCC Linear Regulator Internal VCC Voltage INTVCC Load Regulation Internal VCC Voltage INTVCC Load Regulation EXTVCC Switchover Voltage CONDITIONS MIN TYP MAX 6V < VBIAS < 60V, VEXTVCC = 0 ICC = 0mA to 50mA 6V < VEXTVCC < 13V ICC = 0mA to 40mA, VEXTVCC = 8.5V EXTVCC Ramping Positive 5.2 5.4 0.5 5.4 0.5 4.8 5.6 2 5.6 2 5 5.2 l 4.5 EXTVCC Hysteresis 250 UNITS V % V % V mV Oscillator and Phase-Locked Loop Lowest Fixed Frequency RFREQ = 25k RFREQ = 60k RFREQ = 100k VFREQ = 0V Highest Fixed Frequency VFREQ = INTVCC Synchronizable Frequency PLLIN/MODE = External Clock PGOOD Voltage Low IPGOOD = 2mA PGOOD Leakage Current VPGOOD = 5V PGOOD Trip Level VFB with Respect to Set Regulated Voltage VFB Ramping Negative Hysteresis VFB Ramping Positive Hysteresis Programmable Frequency fLOW 320 105 400 760 350 488 535 335 l 75 380 kHz kHz kHz kHz 585 kHz 850 kHz 0.4 V ±1 µA –8 % % % % 465 PGOOD Output 0.2 PGOOD Delay PGOOD Going High to Low OV Protection Threshold VFB Ramping Positive, OVMODE = 0V –12 8 –10 2.5 10 2.5 12 45 1.296 1.32 µs 1.344 V BOOST Charge Pump BOOST Charge Pump Available Output Current VSW = 12V; VBOOST – VSW = 4.5V; FREQ = 0V, Forced Continuous or Pulse-Skipping Mode Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3769 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3769E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3769I is guaranteed over the –40°C to 125°C operating junction temperature range, the LTC3769H is guaranteed over the –40°C to 150°C operating temperature range and the LTC3769MP is tested and guaranteed over the full –55°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient 55 µA temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA), where θJA = 47°C/W for the QFN package and θJA = 38°C/W for the TSSOP package. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 4: The LTC3769 is tested in a feedback loop that servos VFB to the output of the error amplifier while maintaining ITH at the midpoint of the current limit range. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: See Minimum On-Time Considerations in the Applications Information section. 3769fa 4 For more information www.linear.com/LTC3769 LTC3769 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted. Efficiency and Power Loss vs Output Current Efficiency and Power Loss vs Output Current 100 100 10 10 90 80 VIN = 12V 0.01 VOUT = 24V FIGURE 8 CIRCUIT FCM EFFICIENCY 0.001 FCM LOSS PULSE-SKIPPING EFFICIENCY PULSE-SKIPPING LOSS 0.0001 0.1 1 10 OUTPUT CURRENT (A) 40 30 20 10 0 0.01 EFFICIENCY (%) 0.1 50 80 POWER LOSS 70 60 0.01 VIN = 12V VOUT = 24V FIGURE 8 CIRCUIT 50 40 0.0001 0.1 1 0.001 0.01 OUTPUT CURRENT (A) 3769 G01 100 ILOAD = 2A FIGURE 8 CIRCUIT 99 EFFICIENCY (%) 98 VOUT = 24V 97 96 95 93 INDUCTOR CURRENT 5A/DIV LOAD STEP 2A/DIV INDUCTOR CURRENT 5A/DIV VOUT 500mV/DIV VOUT 500mV/DIV VIN = 12V 200µs/DIV VOUT = 24V LOAD STEP FROM 200mA TO 2.5A FIGURE 8 CIRCUIT 94 0 5 10 15 20 0.001 Load Step Burst Mode Operation LOAD STEP 2A/DIV VOUT = 12V 10 3769 G02 Load Step Forced Continuous Mode Efficiency vs Input Voltage 0.1 POWER LOSS (W) 60 1 EFFICIENCY POWER LOSS (W) 70 EFFICIENCY (%) 90 1 3769 G04 VIN = 12V 200µs/DIV VOUT = 24V LOAD STEP FROM 200mA TO 2.5A FIGURE 8 CIRCUIT 3769 G05 25 INPUT VOLTAGE (V) 3769 G03 Load Step Pulse-Skipping Mode Inductor Currents at Light Load LOAD STEP 2A/DIV INDUCTOR CURRENT 5A/DIV Soft Start-Up FORCED CONTINUOUS MODE Burst Mode OPERATION 5A/DIV PULSESKIPPING MODE VOUT 500mV/DIV VIN = 12V 200µs/DIV VOUT = 24V LOAD STEP FROM 200mA TO 2.5A FIGURE 8 CIRCUIT 3769 G06 VOUT 5V/DIV VIN = 12V 5µs/DIV VOUT = 24V ILOAD = 200µA FIGURE 8 CIRCUIT 3769 G07 VRUN 5V/DIV 0V 20ms/DIV VIN = 12V VOUT = 24V FIGURE 8 CIRCUIT 3769 G08 3769fa For more information www.linear.com/LTC3769 5 LTC3769 TYPICAL PERFORMANCE CHARACTERISTICS Soft-Start Pull-Up Current vs Temperature Regulated Feedback Voltage vs Temperature 6.0 5.5 1.206 1.203 1.200 1.197 1.194 SHUTDOWN CURRENT (µA) 1.209 SOFT-START CURRENT (µA) 10.5 10.0 9.5 1.191 9.0 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3769 G09 4.5 4.0 3.5 3.0 2.5 2.0 Shutdown (RUN) Threshold vs Temperature 1.40 50 VIN = 12V 45 VFB = 1.25V RUN = GND QUIESCENT CURRENT (µA) 7.5 5.0 2.5 1.35 40 35 30 25 20 5 10 15 20 25 30 35 40 45 50 55 60 65 INPUT VOLTAGE (V) 3769 G12 10 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3769 G13 Undervoltage Lockout Threshold vs Temperature 1.20 RUN FALLING 1.10 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3769 G14 5.4 INTVCC RISING 5.3 INTVCC VOLTAGE (V) 4.1 4.0 3.8 1.25 5.5 4.3 3.9 RUN RISING INTVCC Line Regulation 4.4 4.2 1.30 1.15 15 INTVCC VOLTAGE (V) 3769 G11 Quiescent Current vs Temperature VIN = 12V 10.0 0 5.0 1.0 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3769 G10 Shutdown Current vs Input Voltage 12.5 VIN = 12V 1.5 1.188 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) RUN PIN VOLTAGE (V) REGULATED FEEDBACK VOLTAGE (V) Shutdown Current vs Temperature 11.0 1.212 SHUTDOWN CURRENT (µA) TA = 25°C unless otherwise noted. INTVCC FALLING 3.7 5.2 5.1 5.0 4.9 4.8 3.6 4.7 3.5 4.6 3.4 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3769 G15 4.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 INPUT VOLTAGE (V) 3769 G16 3769fa 6 For more information www.linear.com/LTC3769 LTC3769 TYPICAL PERFORMANCE CHARACTERISTICS EXTVCC Switchover and INTVCC Voltages vs Temperature INTVCC vs INTVCC Load Current 6.0 VIN = 12V EXTVCC = 0V 5.35 5.30 5.25 EXTVCC = 6V 5.15 5.10 5.05 5.00 0 FREQ = INTVCC 550 5.6 INTVCC 5.4 5.2 5.0 EXTVCC RISING 4.8 4.6 4.4 EXTVCC FALLING 4.2 MAXIMUM CURRENT SENSE VOLTAGE (mV) 356 354 352 350 348 346 344 342 5 10 15 20 25 30 35 40 45 50 55 60 65 INPUT VOLTAGE (V) 3769 G20 260 240 220 200 180 160 140 120 100 80 60 40 20 0 120 PULSE-SKIPPING MODE Burst Mode OPERATION 60 40 20 ILIM = GND ILIM = FLOAT ILIM = INTVCC 0 –20 FORCED CONTINUOUS MODE –40 –60 0 0.2 0.4 0.6 0.8 1.0 ITH VOLTAGE (V) SENSE Pin Input Current vs ITH Voltage VSENSE = 12V SENSE+ PIN SENSE – PIN 0 0.5 ILIM = INTVCC ILIM = FLOAT ILIM = GND ILIM = INTVCC ILIM = FLOAT ILIM = GND 2 1.5 1 ITH VOLTAGE (V) 2.5 3 3769 G23 FREQ = GND SENSE Pin Input Current vs Temperature 100 80 400 3769 G19 Maximum Current Sense Threshold vs ITH Voltage SENSE CURRENT (µA) 340 SENSE CURRENT (µA) OSCILLATOR FREQUENCY (kHz) 358 FREQ = GND 450 300 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3769 G18 Oscillator Frequency vs Input Voltage 500 350 4.0 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 20 40 60 80 100 120 140 160 180 200 INTVCC LOAD CURRENT (mA) 3769 G17 360 FREQUENCY (kHz) INTVCC VOLTAGE (V) 5.40 5.20 600 5.8 EXTVCC AND INTVCC VOLTAGE (V) 5.45 Oscillator Frequency vs Temperature SENSE CURRENT (µA) 5.50 TA = 25°C unless otherwise noted. 1.2 1.4 3769 G21 260 240 220 200 180 160 140 120 100 80 60 40 20 0 260 VSENSE = 12V 240 ILIM = FLOAT 220 SENSE+ PIN 200 180 160 140 120 100 80 60 40 20 SENSE – PIN 0 –60 –35 –10 15 40 65 90 115 140 TEMPERATURE (°C) 3769 G22 SENSE Pin Input Current vs VSENSE Voltage SENSE+ PIN ILIM = INTVCC ILIM = FLOAT ILIM = GND SENSE– PIN ILIM = INTVCC ILIM = FLOAT ILIM = GND 5 10 15 20 25 30 35 40 45 50 55 60 65 VSENSE COMMON MODE VOLTAGE (V) 3769 G24 3769fa For more information www.linear.com/LTC3769 7 LTC3769 TYPICAL PERFORMANCE CHARACTERISTICS Charge Pump Charging Current vs Operating Frequency 70 ILIM = FLOAT 80 60 ILIM = GND 40 20 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) T = –60°C 70 T = –45°C 60 50 T = 25°C 40 T = 130°C 30 T = 155°C 20 10 0 50 150 250 350 450 550 650 750 OPERATING FREQUENCY (kHz) 3769 G26 3769 G25 PIN FUNCTIONS CHARGE PUMP CHARGING CURRENT (µA) ILIM = INTVCC 100 0 Charge Pump Charging Current vs Switch Voltage 80 120 CHARGE PUMP CHARGING CURRENT (µA) MAXIMUM CURRENT SENSE VOLTAGE (mV) Maximum Current Sense Threshold vs Duty Cycle TA = 25°C unless otherwise noted. FREQ = GND 60 FREQ = INTVCC 50 40 30 20 10 0 5 15 25 35 45 SWITCH VOLTAGE (V) 55 65 3769 G27 (QFN/TSSOP) VBIAS (Pin 1/Pin 19): Main Supply Pin. It is normally tied to the input supply VIN or to the output of the boost converter. A bypass capacitor should be tied between this pin and the signal ground pin. The operating voltage range on this pin is 4.5V to 60V (65V abs max). PGOOD (Pin 2/Pin 20): Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is more than ±10% away from the regulated output voltage. To avoid false trips the output voltage must be outside the range for 45μs before this output is activated. ILIM (Pin 3/Pin 1): Current Comparator Sense Voltage Range Input. This pin is used to set the peak current sense voltage in the current comparator. Connect this pin to SGND, leave floating or connect to INTVCC to set the peak current sense voltage to 50mV, 75mV or 100mV, respectively. INTVCC (Pins 5, 22/Pins 2, 17): Output of Internal 5.4V LDO. Power supply for control circuits and gate drivers. Decouple pin 22/17 to GND with a minimum 4.7μF low ESR ceramic capacitor. Connect pin 5/2 to pin 22/17 with a trace on the printed circuit board. FREQ (Pin 7/Pin 3): Frequency Control Pin for the Internal VCO. Connecting the pin to GND forces the VCO to a fixed low frequency of 350kHz. Connecting the pin to INTVCC forces the VCO to a fixed high frequency of 535kHz. The frequency can be programmed from 50kHz to 900kHz by connecting a resistor from the FREQ pin to GND. The resistor and an internal 20μA source current create a voltage used by the internal oscillator to set the frequency. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. GND (Pin 8, 10, 24, Exposed Pad Pin 25/ Pin 4, Exposed Pad Pin 21): Ground. All ground pins must be connected and the exposed pad must be soldered to the PCB for rated electrical and thermal performance. PLLIN/MODE (Pin 9/Pin 5): External Synchronization Input to Phase Detector and Forced Continuous Mode Input. When an external clock is applied to this pin, the phase-locked loop will force the rising edge of BG to be synchronized with the rising edge of the external clock. When an external clock is applied to this pin, the OVMODE pin is used to determine how the LTC3769 operates at light load. When not synchronizing to an external clock, this 3769fa 8 For more information www.linear.com/LTC3769 LTC3769 PIN FUNCTIONS (QFN/TSSOP) input determines how the LTC3769 operates at light loads. Pulling this pin to ground selects Burst Mode operation. An internal 100k resistor to ground also invokes Burst Mode operation when the pin is floated. Tying this pin to INTVCC forces continuous inductor current operation. Tying this pin to a voltage greater than 1.2V and less than INTVCC – 1.3V selects pulse-skipping operation. This can be done by adding a 100k resistor between the PLLIN/ MODE pin and INTVCC. RUN (Pin 11/Pin 6): Run Control Input. Forcing this pin below 1.28V shuts down the controller. Forcing this pin below 0.7V shuts down the entire LTC3769, reducing quiescent current to approximately 4µA. An external resistor divider connected to VIN can set the threshold for converter operation. Once running, a 4.5µA current is sourced from the RUN pin allowing the user to program hysteresis using the resistor values. SS (Pin 12/Pin 7): Output Soft-Start Input. A capacitor to ground at this pin sets the ramp rate of the output voltage during start-up. SENSE– (Pin 13/Pin 8): Negative Current Sense Comparator Input. The (–) input to the current comparator is normally connected to the negative terminal of a current sense resistor connected in series with the inductor. SENSE+ (Pin 14/Pin 9): Positive Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the positive terminal of a current sense resistor. The current sense resistor is normally placed at the input of the boost controller in series with the inductor. This pin also supplies power to the current comparator. The common mode voltage range on SENSE+ and SENSE– pins is 2.3V to 60V (65V abs max). VFB (Pin 15/Pin 10): Error Amplifier Feedback Input. This pin receives the remotely sensed feedback voltage from an external resistive divider connected across the output. ITH (Pin 16/Pin 11): Current Control Threshold and Error Amplifier Compensation Point. The voltage on this pin sets the current trip threshold. OVMODE (Pin 17/Pin 12): Overvoltage Mode Selection Input. This pin is used to select how the LTC3769 operates when the output feedback voltage (VFB) is overvoltage (>110% of its normal regulated point of 1.2V). It is also used to determine the light-load mode of operation when the LTC3769 is synchronized to an external clock through the PLLIN/MODE pin. When OVMODE is tied to ground, overvoltage protection is enabled and the top MOSFET gate (TG) is turned on continuously until the overvoltage condition is cleared. When OVMODE is grounded, the LTC3769 operates in forced continuous mode when synchronized. There is an internal weak pull-down resistor that pulls the OVMODE pin to ground when it is left floating. When OVMODE is tied to INTVCC, overvoltage protection is disabled and TG is not forced on during an overvoltage event. Instead, the state of TG is determined by the mode of operation selected by the PLLIN/MODE pin and the inductor current. See the Operation section for more details. When OVMODE is tied to INTVCC, the LTC3769 operates in pulse-skipping mode when synchronized. SW (Pin 18/Pin 13): Switch Node. Connect to the source of the synchronous N-channel MOSFET, the drain of the main N-channel MOSFET and the inductor. TG (Pin 19/Pin 14): Top Gate. Connect to the gate of the synchronous N-channel MOSFET. BOOST (Pin 20/Pin 15): Floating power supply for the synchronous N-channel MOSFET. Bypass to SW with a capacitor and supply with a Schottky diode connected to INTVCC. BG (Pin 21/Pin 16): Bottom Gate. Connect to the gate of the main N-channel MOSFET. EXTVCC (Pin 23/Pin 18): External Power Input to an internal LDO Connected to INTVCC. This LDO supplies INTVCC power, bypassing the internal LDO powered from VBIAS whenever EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not float or exceed 14V on this pin. Connect to ground if not used. 3769fa For more information www.linear.com/LTC3769 9 LTC3769 BLOCK DIAGRAM INTVCC S Q R SHDN SWITCHING LOGIC AND CHARGE PUMP 20µA FREQ VCO CLK 0.425V + BOOST DB TG CB VOUT SW INTVCC COUT BG SLEEP PGND – PFD – ICMP + – + + IREV – + – 2mV OVMODE SENSE – 2.8V 0.7V 5M PLLIN/ MODE SYNC DET ILIM SENSE+ SLOPE COMP SENS LO 100k VIN – CIN 2.3V VFB CURRENT LIMIT – EA + + SHDN EXTVCC 5.4V LDO EN 5.4V LDO EN – OV + 3.8V 10µA INTVCC 1.32V 11V SGND RUN + – 1.32V CC + PGOOD CC2 RC – VFB SHDN 1.2V SS ITH 0.5µA/ 4.5µA + – RSENSE + VBIAS 4.8V L SENS LO SS 1.08V + – 3769 BD CSS 3769fa 10 For more information www.linear.com/LTC3769 LTC3769 OPERATION Main Control Loop The LTC3769 uses a constant-frequency, current mode step-up architecture. During normal operation, each external bottom MOSFET is turned on when the clock for that channel sets the RS latch, and is turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The error amplifier compares the output voltage feedback signal at the VFB pin (which is generated with an external resistor divider connected across the output voltage, VOUT , to ground), to the internal 1.200V reference voltage. In a boost converter, the required inductor current is determined by the load current, VIN and VOUT . When the load current increases, it causes a slight decrease in VFB relative to the reference, which causes the EA to increase the ITH voltage until the average inductor current in each channel matches the new requirement based on the new load current. After the bottom MOSFET is turned off each cycle, the top MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current comparator, IREV, or the beginning of the next clock cycle. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is tied to a voltage less than 4.8V, the VBIAS LDO (low dropout linear regulator) supplies 5.4V from VBIAS to INTVCC. If EXTVCC is taken above 4.8V, the VBIAS LDO is turned off and an EXTVCC LDO is turned on. Once enabled, the EXTVCC LDO supplies 5.4V from EXTVCC to INTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from an external source, thus removing the power dissipation of the VBIAS LDO. Shutdown and Start-Up (RUN and SS Pins) The LTC3769 can be shut down using the RUN pin. Pulling this pin below 1.28V shuts down the main control loops. Pulling this pin below 0.7V disables the controller and most internal circuits, including the INTVCC LDOs. In this state, the LTC3769 draws only 4μA of quiescent current. NOTE: Do not apply a heavy load to the boost converter for an extended time while the LTC3769 is in shutdown. The top MOSFET is turned off during shutdown and the output load may cause excessive dissipation in the body diode. The RUN pin may be externally pulled up or driven directly by logic. When driving the RUN pin with a low impedance source, do not exceed the absolute maximum rating of 8V. The RUN pin has an internal 11V voltage clamp that allows the RUN pin to be connected through a resistor to a higher voltage (for example, VIN), as long as the maximum current into the RUN pin does not exceed 100μA. An external resistor divider connected to VIN can set the threshold for converter operation. Once running, a 4.5μA current is sourced from the RUN pin allowing the user to program hysteresis using the resistor values. The start-up of the controller’s output voltage VOUT is controlled by the voltage on the SS pin. When the voltage on the SS pin is less than the 1.2V internal reference, the LTC3769 regulates the VFB voltage to the SS pin voltage instead of the 1.2V reference. This allows the SS pin to be used to program a soft-start by connecting an external capacitor from the SS pin to SGND. An internal 10μA pull‑up current charges this capacitor creating a voltage ramp on the SS pin. As the SS voltage rises linearly from 0V to 1.2V (and beyond up to INTVCC), the output voltage rises smoothly to its final value. Light Load Current Operation—Burst Mode Operation, Pulse-Skipping or Continuous Conduction (PLLIN/MODE Pin) The LTC3769 can be enabled to enter high efficiency Burst Mode operation, constant-frequency, pulse-skipping mode or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/MODE pin to ground (e.g., SGND). To select forced continuous operation, tie the PLLIN/MODE pin to INTVCC. To select pulse-skipping mode, tie the PLLIN/ MODE pin to a DC voltage greater than 1.2V and less than INTVCC – 1.3V. When the controller is enabled for Burst Mode operation, the minimum peak current in the inductor is set to 3769fa For more information www.linear.com/LTC3769 11 LTC3769 OPERATION approximately 30% of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the required current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.425V, the internal sleep signal goes high (enabling sleep mode) and both external MOSFETs are turned off. In sleep mode much of the internal circuitry is turned off and the LTC3769 draws only 28μA of quiescent current. In sleep mode the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low and the controller resumes normal operation by turning on the bottom external MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IREV) turns off the top external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous current operation. In forced continuous operation or when clocked by an external clock source to use the phase-locked loop (see the Frequency Selection and Phase-Locked Loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous operation has the advantages of lower output voltage ripple and less interference to audio circuitry, as it maintains constant-frequency operation independent of load current. When the PLLIN/MODE pin is connected for pulse-skipping mode, the LTC3769 operates in PWM pulse-skipping mode at light loads. In this mode, constant-frequency operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the current comparator ICMP may remain tripped for several cycles and force the external bottom MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ and PLLIN/MODE Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3769’s controllers can be selected using the FREQ pin. If the PLLIN/MODE pin is not being driven by an external clock source, the FREQ pin can be tied to SGND, tied to INTVCC, or programmed through an external resistor. Tying FREQ to SGND selects 350kHz while tying FREQ to INTVCC selects 535kHz. Placing a resistor between FREQ and SGND allows the frequency to be programmed between 50kHz and 900kHz, as shown in Figure 7. A phase-locked loop (PLL) is available on the LTC3769 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. The LTC3769’s phase detector adjusts the voltage (through an internal lowpass filter) of the VCO input so that the turn-on of the external bottom MOSFET is 180° out-of-phase to the rising edge of the external clock source. When synchronized, the LTC3769 will operate in forced continuous mode of operation if the OVMODE pin is grounded. If the OVMODE pin is tied to INTVCC, the LTC3769 will operate in pulse-skipping mode of operation when synchronized. The VCO input voltage is prebiased to the operating frequency set by the FREQ pin before the external clock is applied. If prebiased near the external clock frequency, the PLL loop only needs to make slight changes to the VCO input in order to synchronize the rising edge of the external clock’s to the rising edge of BG1. The ability to prebias the loop filter allows the PLL to lock-in rapidly without deviating far from the desired frequency. 3769fa 12 For more information www.linear.com/LTC3769 LTC3769 OPERATION The typical capture range of the LTC3769’s PLL is from approximately 55kHz to 1MHz, and is guaranteed to lock to an external clock source whose frequency is between 75kHz and 850kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.6V (rising) and 1.2V (falling). The recommended maximum amplitude for low level and minimum amplitude for high level of external clock are 0V and 2.5V, respectively. Operation When VIN > Regulated VOUT Power Good The PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the VFB pin voltage is not within ±10% of the 1.2V reference voltage. The PGOOD pin is also pulled low when the corresponding RUN pin is low (shut down). When the VFB pin voltage is within the ±10% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V (abs max). When VIN rises above the regulated VOUT voltage, the boost controller can behave differently depending on the mode, inductor current and VIN voltage. In forced continuous mode, the control loop works to keep the top MOSFET on continuously once VIN rises above VOUT. The internal charge pump delivers current to the boost capacitor to maintain a sufficiently high TG voltage. The amount of current the charge pump can deliver is characterized by two curves in the Typical Performance Characteristics section. Overvoltage Mode Selection In pulse-skipping mode, if VIN is between 100% and 110% of the regulated VOUT voltage, TG turns on if the inductor current rises above a certain threshold and turns off if the inductor current falls below this threshold. This threshold current is set to approximately 6%, 4% or 3% of the maximum ILIM current when the ILIM pin is grounded, floating or tied to INTVCC, respectively. If the controller is programmed to Burst Mode operation under this same VIN window, then TG remains off regardless of the inductor current. The OVMODE pin is a logic input that should normally be tied to INTVCC or grounded. Alternatively, the pin can be left floating, which allow a weak internal resistor to pull it down to ground. If the OVMODE pin is grounded and VIN rises above 110% of the regulated VOUT voltage in any mode, the controller turns on TG regardless of the inductor current. In Burst Mode operation, however, the internal charge pump turns off if the chip is asleep. With the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an insufficient TG voltage needed to keep the top MOSFET completely on. To prevent excessive power dissipation across the body diode of the top MOSFET in this situation, the chip can be switched over to forced continuous mode to enable the charge pump; a Schottky diode can also be placed in parallel with the top MOSFET. The OVMODE pin is used to select how the LTC3769 operates during an overvoltage event, defined as when the output feedback voltage (VFB) is greater than 110% of its normal regulated point of 1.2V. It is also used to determine the light-load mode of operation when the LTC3769 is synchronized to an external clock through the PLLIN/MODE pin. OVMODE = INTVCC: An overvoltage event causes the error amplifier to pull the ITH pin low. In Burst Mode operation, this causes the LTC3769 to go to sleep and TG and BG are held off. In pulse-skipping mode, BG is held off and TG will turn on if the inductor current is positive. In forced continuous mode, TG (and BG) will switch on and off as the LTC3769 will regulate the inductor current to a negative peak value (corresponding to ITH = 0V) to discharge the output. When OVMODE is tied to INTVCC, the LTC3769 operates in pulse-skipping mode when synchronized. In summary, with OVMODE = INTVCC, the inductor current is not allowed to go negative (reverse from output to input) except in forced continuous mode, where it does reverse current but in a controlled manner with a regulated negative peak current. OVMODE should be tied to INTVCC in applications where the output voltage may sometimes be above its regulation point (for example, if the output 3769fa For more information www.linear.com/LTC3769 13 LTC3769 OPERATION is a battery or if there are other power supplies driving the output) and no reverse current flow from output to input is desired. OVMODE Grounded or Left Floating: When OVMODE is grounded or left floating, overvoltage protection is enabled and TG is turned on continuously until the overvoltage condition is cleared, regardless of whether Burst Mode operation, pulse-skipping mode, or forced continuous mode is selected by the PLLIN/MODE pin. This can cause large negative inductor currents to flow from the output to the input if the output voltage is higher than the input voltage. Note however that in Burst Mode operation, the LTC3769 is in sleep during an overvoltage condition, which disables the internal oscillator and BOOST-SW charge pump. So the BOOST-SW voltage may discharge (due to leakage) if the overvoltage conditions persists indefinitely. If BOOST-SW discharges, then by definition TG would turn off. When OVMODE is grounded or left floating, the LTC3769 operates in forced continuous mode when synchronized. OVMODE should be tied to ground or left floating in circuits, such as automotive applications, where the input voltage can often be above the regulated output voltage and it is desirable to turn on TG to “pass through” the input voltage to the output. Operation at Low SENSE Pin Common Mode Voltage The current comparator in the LTC3769 is powered directly from the SENSE+ pin. This enables the common mode voltage of the SENSE+ and SENSE– pins to operate at as low as 2.3V, which is below the UVLO threshold. Figure 10 shows a typical application in which the controller’s VBIAS is powered from VOUT while the VIN supply can go as low as 2.3V. If the voltage on SENSE+ drops below 2.3V, the SS pin will be held low. When the SENSE voltage returns to the normal operating range, the SS pin will be released, initiating a new soft-start cycle. BOOST Supply Refresh and Internal Charge Pump The top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each cycle through an external diode when the bottom MOSFET turns on. There are two considerations for keeping the BOOST supply at the required bias level. During start-up, if the bottom MOSFET is not turned on within 200μs after UVLO goes low, the bottom MOSFET will be forced to turn on for ~400ns. This forced refresh generates enough BOOST-SW voltage to allow the top MOSFET ready to be fully enhanced instead of waiting for the initial few cycles to charge up. There is also an internal charge pump that keeps the required bias on BOOST. The charge pump always operates in both forced continuous mode and pulse-skipping mode. In Burst Mode operation, the charge pump is turned off during sleep and enabled when the chip wakes up. The internal charge pump can normally supply a charging current of 55μA. 3769fa 14 For more information www.linear.com/LTC3769 LTC3769 APPLICATIONS INFORMATION The Typical Application on the first page is a basic LTC3769 application circuit. The LTC3769 can be configured to use either inductor DCR (DC resistance) sensing or a discrete sense resistor (RSENSE) for current sensing. The choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. DCR sensing is becoming popular because it does not require current sensing resistors and is more power-efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value. Next, the power MOSFETs are selected. Finally, input and output capacitors are selected. SENSE+ and SENSE– Pins The SENSE+ pin also provides power to the current comparator. It draws ~200μA during normal operation. There is a small base current of less than 1μA that flows into the SENSE– pin. The high impedance SENSE– input to the current comparators allows accurate DCR sensing. Filter components mutual to the sense lines should be placed close to the LTC3769, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If DCR sensing is used (Figure 2b), resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode input voltage range of the current comparators is 2.3V to 60V. The current sense resistor is normally placed at the input of the boost controller in series with the inductor. TO SENSE FILTER, NEXT TO THE CONTROLLER VIN INDUCTOR OR RSENSE 3769 F01 Figure 1. Sense Lines Placement with Inductor or Sense Resistor VBIAS VBIAS VIN VIN SENSE+ SENSE+ C1 (OPTIONAL) R2 DCR SENSE– SENSE– INTVCC INTVCC LTC3769 LTC3769 BOOST BOOST TG TG L INDUCTOR VOUT SW VOUT SW R1 BG BG GND GND 3769 F02b 3769 F02a PLACE C1 NEAR SENSE PINS (2a) Using a Resistor to Sense Current (R1||R2) • C1 = L DCR RSENSE(EQ) = DCR • R2 R1 + R2 (2b) Using the Inductor DCR to Sense Current Figure 2. Two Different Methods of Sensing Current 3769fa For more information www.linear.com/LTC3769 15 LTC3769 APPLICATIONS INFORMATION Sense Resistor Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 2a. RSENSE is chosen based on the required output current. The current comparator has a maximum threshold VSENSE(MAX). When the ILIM pin is grounded, floating or tied to INTVCC, the maximum threshold is set to 50mV, 75mV or 100mV, respectively. The current comparator threshold sets the peak of the inductor current, yielding a maximum average inductor current, IMAX, equal to the peak value less half the peak-to-peak ripple current, ΔIL. To calculate the sense resistor value, use the equation: RSENSE = VSENSE(MAX) ΔI IMAX + L 2 Using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: RSENSE(EQUIV) = The actual value of IMAX depends on the required output current IOUT(MAX) and can be calculated using: IMAX = IOUT(MAX) • If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured using a good RLC meter, but the DCR tolerance is not always the same and varies with temperature. Consult the manufacturers’ data sheets for detailed information. VOUT VIN When using the controller in low VIN and very high voltage output applications, the maximum inductor current and correspondingly the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for boost regulators operating at greater than 50% duty factor. A curve is provided in the Typical Performance Characteristics section to estimate this reduction in peak inductor current level depending upon the operating duty factor. Inductor DCR Sensing For applications requiring the highest possible efficiency at high load currents, the LTC3769 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 2b. The DCR of the inductor can be less than 1mΩ for high current inductors. In a high current application requiring such an inductor, conduction loss through a sense resistor could reduce the efficiency by a few percent compared to DCR sensing. VSENSE(MAX) ΔI IMAX + L 2 To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (VSENSE(MAX)). Next, determine the DCR of the inductor. Where provided, use the manufacturer’s maximum value, usually given at 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C. A conservative value for the maximum inductor temperature (TL(MAX)) is 100°C. To scale the maximum inductor DCR to the desired sense resistor value, use the divider ratio: RD = RSENSE(EQUIV) DCRMAX at TL(MAX) C1 is usually selected to be in the range of 0.1μF to 0.47μF. This forces R1|| R2 to around 2k, reducing error that might have been caused by the SENSE– pin’s ±1μA current. The equivalent resistance R1|| R2 is scaled to the room temperature inductance and maximum DCR: R1||R2 = L (DCR at 20°C)•C1 3769fa 16 For more information www.linear.com/LTC3769 LTC3769 APPLICATIONS INFORMATION The sense resistor values are: R1= R1||R2 R1•RD ; R2 = RD 1−RD The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at VIN = 1/2VOUT : PLOSS_R1 = (VOUT − VIN )• VIN R1 Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. Why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge and switching losses. Also, at higher frequency the duty cycle of body diode conduction is higher, which results in lower efficiency. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ΔIL decreases with higher inductance or frequency and increases with higher VIN: ΔIL = VIN ⎛ V ⎞ 1− IN ⎟ ⎜ f •L ⎝ VOUT ⎠ Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ΔIL = 0.3(IMAX). The maximum ΔIL occurs at VIN = 1/2VOUT. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by RSENSE. Lower inductor values (higher ΔIL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Once the value of L is known, an inductor with low DCR and low core losses should be selected. Power MOSFET Selection Two external power MOSFETs must be selected for the LTC3769: one N-channel MOSFET for the bottom (main) switch, and one N-channel MOSFET for the top (synchronous) switch. The peak-to-peak gate drive levels are set by the INTVCC voltage. This voltage is typically 5.4V during start-up (see EXTVCC pin connection). Consequently, logic-level threshold MOSFETs must be used in most applications. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the on-resistance RDS(ON), Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturer’s data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode, the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT − VIN VOUT Synchronous Switch Duty Cycle = VIN VOUT 3769fa For more information www.linear.com/LTC3769 17 LTC3769 APPLICATIONS INFORMATION If the maximum output current is IOUT(MAX) the MOSFET power dissipation at maximum output current is given by: PMAIN = (VOUT VIN )VOUT V 2 IN 2 • I OUT(MAX) • (1+ • RDS(ON) +k • VOUT 3 • ) IOUT(MAX) VIN • CMILLER • f PSYNC = VIN 2 • I OUT(MAX) • (1+ VOUT ) •RDS(ON) where d is the temperature dependency of RDS(ON). The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. Both MOSFETs have I2R losses while the bottom N-channel equation includes an additional term for transition losses, which are highest at low input voltages. For high VIN the high current efficiency generally improves with larger MOSFETs, while for low VIN the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the bottom switch duty factor is low or during overvoltage when the synchronous switch is on close to 100% of the period. The term (1+ d) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but d = 0.005/°C can be used as an approximation for low voltage MOSFETs. CIN and COUT Selection The input ripple current in a boost converter is relatively low (compared with the output ripple current), because this current is continuous. The input capacitor CIN voltage rating should comfortably exceed the maximum input voltage. Although ceramic capacitors can be relatively tolerant of overvoltage conditions, aluminum electrolytic capacitors are not. Be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. The value of CIN is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance. The required amount of input capacitance is also greatly affected by the duty cycle. High output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of DC current and ripple current. In a boost converter, the output has a discontinuous current, so COUT must be capable of reducing the output voltage ripple. The effects of ESR (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The steady ripple voltage due to charging and discharging the bulk capacitance in a single phase boost converter is given by: VRIPPLE = IOUT(MAX) •(VOUT − VIN(MIN) ) COUT • VOUT • f V where COUT is the output filter capacitor. The steady ripple due to the voltage drop across the ESR is given by: ∆VESR = IL(MAX) • ESR Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient. Capacitors are now available with low ESR and high ripple current ratings (e.g., OS-CON and POSCAP). 3769fa 18 For more information www.linear.com/LTC3769 LTC3769 APPLICATIONS INFORMATION Setting Output Voltage LTC3769 The LTC3769 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 3. The regulated output voltage is determined by: ⎛ R ⎞ VOUT = 1.2V ⎜ 1+ B ⎟ ⎝ RA ⎠ VOUT RB VFB RA 3769 F03 Figure 3. Setting Output Voltage Soft-Start (SS Pin) The start-up of VOUT is controlled by the voltage on the SS pin. When the voltage on the SS pin is less than the internal 1.2V reference, the LTC3769 regulates the VFB pin voltage to the voltage on the SS pin instead of 1.2V. Soft-start is enabled by simply connecting a capacitor from the SS pin to ground, as shown in Figure 4. An internal 10μA current source charges the capacitor, providing a linear ramping voltage at the SS pin. The LTC3769 will regulate the VFB pin (and hence, VOUT) according to the voltage on the SS pin, allowing VOUT to rise smoothly from VIN to its final regulated value. The total soft-start time will be approximately: t SS = CSS • 1.2V 10µA CSS GND 3769 F04 Figure 4. Using the SS Pin to Program Soft-Start Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Also place the feedback resistor divider close to the VFB pin and keep the VFB node as small as possible to avoid noise pickup. LTC3769 SS INTVCC Regulators The LTC3769 features two separate internal P-channel low dropout linear regulators (LDO) that supply power at the INTVCC pin from either the VBIAS supply pin or the EXTVCC pin depending on the connection of the EXTVCC pin. INTVCC powers the gate drivers and much of the LTC3769’s internal circuitry. The VBIAS LDO and the EXTVCC LDO regulate INTVCC to 5.4V. Each of these can supply at least 50mA and must be bypassed to ground with a minimum of a 4.7μF ceramic capacitor. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3769 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the VBIAS LDO or the EXTVCC LDO. When the voltage on the EXTVCC pin is less than 4.8V, the VBIAS LDO is enabled. In this case, power dissipation for the IC is highest and is equal to VBIAS • IINTVCC. The gate charge current is dependent on operating frequency, as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, at 70°C ambient temperature, the LTC3769 INTVCC current is limited to less than 19mA in the QFN package from a 60V VBIAS supply when not using the EXTVCC supply: TJ = 70°C + (19mA)(60V)(47°C/W) = 125°C 3769fa For more information www.linear.com/LTC3769 19 LTC3769 APPLICATIONS INFORMATION In the TSSOP package, the INTVCC current is limited to less than 24mA from a 60V supply when not using the EXTVCC supply: TJ = 70°C + (24mA)(60V)(38°C/W) = 125°C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (PLLIN/MODE = INTVCC) at maximum VIN. When the voltage applied to EXTVCC rises above 4.8V, the VIN LDO is turned off and the EXTVCC LDO is enabled. The EXTVCC LDO remains on as long as the voltage applied to EXTVCC remains above 4.55V. The EXTVCC LDO attempts to regulate the INTVCC voltage to 5.4V, so while EXTVCC is less than 5.4V, the LDO is in dropout and the INTVCC voltage is approximately equal to EXTVCC. When EXTVCC is greater than 5.4V, up to an absolute maximum of 14V, INTVCC is regulated to 5.4V. Significant thermal gains can be realized by powering INTVCC from an external supply. Tying the EXTVCC pin to a 5V supply reduces the junction temperature in the previous example from 125°C to 75°C in a QFN package: TJ = 70°C + (19mA)(5V)(47°C/W) = 75°C and from 125°C to 75°C in the TSSOP package: TJ = 70°C + (24mA)(5V)(38°C/W) = 75°C The following list summarizes possible connections for EXTVCC: EXTVCC Grounded. This will cause INTVCC to be powered from the internal 5.4V regulator resulting in an efficiency penalty at high VBIAS voltages. EXTVCC Connected to an External Supply. If an external supply is available in the 5V to 14V range, it may be used to provide power. Ensure that EXTVCC is always lower than or equal to VBIAS. Topside MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. Capacitor CB in the Block Diagram is charged though external diode DB from INTVCC when the SW pin is low. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate and source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VOUT and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the output voltage: VBOOST = VOUT + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external diode DB must be greater than VOUT(MAX). The external diode DB can be a Schottky diode or silicon diode, but in either case it should have low leakage and fast recovery. Pay close attention to the reverse leakage at high temperatures, where it generally increases substantially. The topside MOSFET driver includes an internal charge pump that delivers current to the bootstrap capacitor from the BOOST pin. This charge current maintains the bias voltage required to keep the top MOSFET on continuously during dropout/overvoltage conditions. The Schottky/ silicon diode selected for the topside driver should have a reverse leakage less than the available output current the charge pump can supply. Curves displaying the available charge pump current under different operating conditions can be found in the Typical Performance Characteristics section. A leaky diode DB in the boost converter can not only prevent the top MOSFET from fully turning on but it can also completely discharge the bootstrap capacitor CB and create a current path from the input voltage to the BOOST pin to INTVCC. This can cause INTVCC to rise if the diode leakage exceeds the current consumption on INTVCC. This is particularly a concern in Burst Mode operation 3769fa 20 For more information www.linear.com/LTC3769 LTC3769 APPLICATIONS INFORMATION Fault Conditions: Overtemperature Protection At higher temperatures, or in cases where the internal power dissipation causes excessive self heating on-chip (such as an INTVCC short to ground), the overtemperature shutdown circuitry will shut down the LTC3769. When the junction temperature exceeds approximately 170°C, the overtemperature circuitry disables the INTVCC LDO, causing the INTVCC supply to collapse and effectively shut down the entire LTC3769 chip. Once the junction temperature drops back to approximately 155°C, the INTVCC LDO turns back on. Long term overstress (TJ > 125°C) should be avoided as it can degrade the performance or shorten the life of the part. Since the shutdown may occur at full load, beware that the load current will result in high power dissipation in the body diodes of the top MOSFETs. In this case, the PGOOD output may be used to turn the system load off. Phase-Locked Loop and Frequency Synchronization The LTC3769 has an internal phase-locked loop (PLL) comprised of a phase frequency detector, a lowpass filter and a voltage-controlled oscillator (VCO). This allows the turn-on of the bottom MOSFET to be locked signal applied to 180 degrees out-of-phase to the rising edge of the external clock. The phase detector is an edge-sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the VCO input. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the VCO input. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage at the VCO input is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the internal filter capacitor, CLP , holds the voltage at the VCO input. 1000 900 800 FREQUENCY (kHz) where the load on INTVCC can be very small. The external Schottky or silicon diode should be carefully chosen such that INTVCC never gets charged up much higher than its normal regulation voltage. 700 600 500 400 300 200 100 0 15 25 35 45 55 65 75 85 95 105 115 125 3769 F05 FREQ PIN RESISTOR (kΩ) Figure 5. Relationship Between Oscillator Frequency and Resistor Value at the FREQ Pin Typically, the external clock (on the PLLIN/MODE pin) input high threshold is 1.6V, while the input low threshold is 1.2V. Note that the LTC3769 can only be synchronized to an external clock whose frequency is within range of the LTC3769’s internal VCO, which is nominally 55kHz to 1MHz. This is guaranteed to be between 75kHz and 850kHz. Rapid phase locking can be achieved by using the FREQ pin to set a free-running frequency near the desired synchronization frequency. The VCO’s input voltage is prebiased at a frequency corresponding to the frequency set by the FREQ pin. Once prebiased, the PLL only needs to adjust the frequency slightly to achieve phase lock and synchronization. Although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the PLL locks. 3769fa For more information www.linear.com/LTC3769 21 LTC3769 APPLICATIONS INFORMATION Table 1 summarizes the different states in which the FREQ pin can be used. Table 1. FREQ PIN PLLIN/MODE PIN FREQUENCY 0V DC Voltage 350kHz INTVCC DC Voltage 535kHz Resistor DC Voltage 50kHz to 900kHz Any of the Above External Clock Phase Locked to External Clock Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the LTC3769 is capable of turning on the bottom MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum ontime limit. In forced continuous mode, if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles but the output will continue to be regulated. More cycles will be skipped when VIN increases. Once VIN rises above VOUT, the loop keeps the top MOSFET continuously on. The minimum on-time for the LTC3769 is approximately 110ns. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the greatest improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc., are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in LTC3769 circuits: 1) IC VBIAS current, 2) INTVCC regulator current, 3) I2R losses, 4) bottom MOSFET transition losses, 5) body diode conduction losses. 1. The VBIAS current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. VBIAS current typically results in a small (<0.1%) loss. 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge, dQ, moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. 3. DC I2R losses. These arise from the resistances of the MOSFETs, sensing resistor, inductor and PC board traces and cause the efficiency to drop at high output currents. 4. Transition losses apply only to the bottom MOSFET(s), and become significant only when operating at low input voltages. Transition losses can be estimated from: Transition Loss = (1.7) VOUT3 • IOUT(MAX) • CRSS • f VIN 5. Body diode conduction losses are more significant at higher switching frequency. During the dead time, the loss in the top MOSFET is IOUT • VDS, where VDS is around 0.7V. At higher switching frequency, the dead time becomes a good percentage of switching cycle and causes the efficiency to drop. 3769fa 22 For more information www.linear.com/LTC3769 LTC3769 APPLICATIONS INFORMATION Other hidden losses, such as copper trace and internal battery resistances, can account for an additional efficiency degradation in portable systems. It is very important to include these system-level losses during the design phase. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series resistance of COUT . ΔILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTI-LOOP® compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior, but it also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 10 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly to optimize transient response once the final PC layout is complete and the particular output capacitor type and value have been determined. The output capacitors must be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET and load resistor directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT , causing a rapid drop in VOUT . No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus, a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. Design Example As a design example, assume VIN = 12V (nominal), VIN = 22V (max), VOUT = 24V, IOUT(MAX) = 4A, VSENSE(MAX) = 75mV, and f = 350kHz. The inductance value is chosen first based on a 30% ripple current assumption. Tie the FREQ pin to GND, generat- 3769fa For more information www.linear.com/LTC3769 23 LTC3769 APPLICATIONS INFORMATION ing 350kHz operation. The minimum inductance for 30% ripple current is: ΔIL = VIN ⎛ V ⎞ 1− IN ⎟ ⎜ f •L ⎝ VOUT ⎠ The largest ripple happens when VIN = 1/2VOUT = 12V, where the average maximum inductor current is: IMAX = IOUT(MAX) • VOUT = 8A VIN A 6.8μH inductor will produce a 31% ripple current. The peak inductor current will be the maximum DC value plus one half the ripple current, or 9.25A. The RSENSE resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: RSENSE ≤ 75mV = 0.008Ω 9.25A Choosing 1% resistors: RA = 5k and RB = 95.3k yields an output voltage of 24.072V. The power dissipation on the top side MOSFET can be easily estimated. Choosing a Vishay Si7848BDP MOSFET results in: RDS(ON) = 0.012Ω, CMILLER = 150pF. At maximum input voltage with T (estimated) = 50°C: PMAIN = (24V – 12V) 24V (12V)2 •(4A)2 • [1+(0.005)(50°C – 25°C)] • 0.012 + (1.7)(24V)3 4A (150pF)(350kHz) = 0.84W 12V COUT is chosen to filter the square current in the output. The maximum output current peak is: ⎛ 31% ⎞ IOUT(PEAK) = 8 • ⎜ 1+ ⎟ = 9.3A ⎝ 2 ⎠ PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 6. Figure 7 illustrates the current waveforms present in the synchronous regulator operating in the continuous mode. Check the following in your layout: 1. Put the bottom N-channel MOSFET MBOT and the top N-channel MOSFET MTOP1 in one compact area with COUT . 2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The path formed by the bottom N-channel MOSFET and the capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the source terminals of the bottom MOSFETs. 3. Does the LTC3769 VFB pin’s resistive divider connect to the (+) terminal of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground and placed close to the VFB pin. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor. 5. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers’ current peaks. An additional 1μF ceramic capacitor placed immediately next to the INTVCC and GND pins can help improve noise performance substantially. A low ESR (5mΩ) capacitor is suggested. This capacitor will limit output voltage ripple to 46.5mV (assuming ESR dominates the ripple). 3769fa 24 For more information www.linear.com/LTC3769 LTC3769 APPLICATIONS INFORMATION SENSE+ PGOOD SENSE– SW LTC3769 OVMODE TG CB M2 BG PLLIN/MODE RSENSE L1 BOOST FREQ fIN VPULLUP + M1 RUN VFB ITH SS VBIAS + GND VIN GND INTVCC VOUT 3769 F06 Figure 6. Recommended Printed Circuit Layout Diagram RSENSE VIN L1 VOUT SW RIN COUT CIN RL 3769 F07 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH Figure 7. Branch Current Waveforms 3769fa For more information www.linear.com/LTC3769 25 LTC3769 APPLICATIONS INFORMATION 6. Keep the switching node (SW), top gate node (TG) and boost node (BOOST) away from sensitive small-signal nodes. All of these nodes have very large and fast moving signals and, therefore, should be kept on the output side of the LTC3769 and occupy a minimal PC trace area. 7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the GND pins of the IC. PC Board Layout Debugging It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold— typically 10% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Reduce VIN from its nominal level to verify operation with high duty cycle. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. An embarrassing problem which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. The output voltage under this improper hook-up will still be maintained, but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor—don’t worry, the regulator will still maintain control of the output voltage. 3769fa 26 For more information www.linear.com/LTC3769 LTC3769 TYPICAL APPLICATIONS VBIAS SENSE+ ILIM CSS 0.1µF CITH 15nF RITH 12.1k SENSE– EXTVCC OVMODE PLLIN/MODE RUN TG FREQ SW SS BOOST VIN 5V TO 24V CIN 22µF L 3.3µH CB 0.1µF MTOP MBOT BG ITH COUTA 22µF ×4 + COUTB 150µF VOUT 24V 5A* D CITHA 100pF INTVCC GND RA 12.1k RSENSE 4mΩ LTC3769 VFB PGOOD RS 232k CINT 4.7µF 100k 3769 F08 CIN, COUTA: TDK C4532X5R1E226M COUTB: SUNCON 35HVH150M D: BAS140W L: PULSE PA1494.362NL MBOT, MTOP: RENESAS RJK0452, RJK0453 *WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED. WHEN VIN > 24V, VOUT FOLLOWS VIN. Figure 8. High Efficiency 24V Boost Converter VBIAS SENSE+ ILIM CSS 0.1µF CITH 15nF RITH 8.66k LTC3769 – SENSE EXTVCC OVMODE PLLIN/MODE RUN TG FREQ SW SS BOOST VIN 5V TO 28V CIN 22µF L 3.3µH CB 0.1µF BG ITH MTOP MBOT COUTA 22µF ×4 + COUTB 150µF VOUT 28V 4A* D CITHA 220pF INTVCC GND RA 12.1k RSENSE 4mΩ VFB PGOOD CINT 4.7µF 100k RS 261k CIN, COUTA: TDK C4532X7R1H685K COUTB: SUNCON 63CE220KX D: BAS140W L: PULSE PA1494.362NL MBOT, MTOP: RENESAS HAT2169H 3769 F09 *WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED. WHEN VIN > 28V, VOUT FOLLOWS VIN. Figure 9. High Efficiency 28V Boost Converter 3769fa For more information www.linear.com/LTC3769 27 LTC3769 TYPICAL APPLICATIONS VBIAS + SENSE ILIM RSENSE 2mΩ LTC3769 EXTVCC OVMODE CB 0.1µF SS MTOP BOOST COUTB 56µF ×2 VOUT* 10V 5A MBOT BG ITH D INTVCC RA 64.9k + TG SW CITHA 820pF COUTA 10µF ×3 VIN 5V TO 60V START-UP VOLTAGE OPERATES THROUGH TRANSIENTS DOWN TO 2.3V L 1.3µH CSS 0.1µF RITH 4.75k + CINB 50µF ×2 SENSE– RUN FREQ CITH 10nF CINA 10µF ×2 CINT 4.7µF GND VFB PLLIN/MODE RB 475k PGOOD 100k L: WÜRTH 7443551130 MBOT, MTOP: INFINEON BSC028N06L53 D: BAS170W 3769 F10 CINA, COUTA: GRM32ER71J106KA12L CINB, COUTB: SUNCON 63HVH56M *WHEN VIN > 10V, VOUT FOLLOWS VIN. Figure 10. High Efficiency 10V Boost Converter VBIAS SENSE+ LTC3769 EXTVCC C1 0.1µF OVMODE RUN FREQ 41.2k CSS 0.1µF SS CITH 15nF RITH 8.66k SENSE– TG RS2 53.6k RS1 1% 26.1k 1% L 10.2µH ITH SW CB 0.1µF MTOP VFB GND PLLIN/MODE PGOOD 100 VIN = 12V 98 COUTA 22µF ×4 + COUTB 220µF VIN = 9V VOUT 24V* 4A VIN = 6V 94 92 90 MBOT BG D INTVCC RA 12.1k CIN 22µF 96 BOOST CITHA 220pF VIN 8V TO 24V EFFICIENCY (%) ILIM 88 CINT 4.7µF 86 0 1 100k 5 6 3769 F11b RB 232k C1: TDK C1005X7R1C104K CIN, COUTA: TDK C4532X5R1E226M COUTB: SUNCON, 50CE220AX L: PULSE PA2050.103NL MBOT, MTOP: RENESAS RJK0305 D: INFINEON BAS140W 4 2 3 OUTPUT CURRENT (A) 3769 F11a Figure 11. High Efficiency 24V Boost Converter with Inductor DCR Current Sensing 3769fa 28 For more information www.linear.com/LTC3769 LTC3769 TYPICAL APPLICATIONS VBIAS SENSE+ LTC3769 EXTVCC OVMODE SENSE– CSS 0.1µF CITH 10nF TG D SW SS RITH 24.9k COUTA 10µF BOOST BG ITH + COUTB 56µF ×2 MBOT VOUT 24V* 2A ILIM CITHA 100pF INTVCC 12.1k 1% VIN 5V TO 60V CIN 10µF ×2 L 6.8µH PLLIN/MODE RUN FREQ 47.5k RSENSE 6mΩ GND VFB PGOOD CINT 4.7µF 100k 232k 1% 3769 F12 CIN, COUTA: MURATA GRM32ER71J106KA12L COUTB: SUNCON 63HVH56M D: DIODES INC B360 L: COILCRAFT XAL1010 6.8µH MBOT: INFINEON BSC100NO6LS *WHEN VIN > 24V, VOUT FOLLOWS VIN. Figure 12. Low IQ Nonsynchronous 24V/2A Boost Converter VIN 18V TO 32V VBIAS SENSE+ LTC3769 0.1µF 15nF 12.1k 100pF • + 33µF L1 4.7µF (×4) BG ITH 4.7µF ×3 4mΩ EXTVCC SENSE– OVMODE ILIM PLLIN/MODE RUN TG FREQ SW SS M1 D1 • L1 VOUT 24V 2.5A 4.7µF ×5 + 220µF ×2 BOOST INTVCC 12.1k VFB 4.7µF GND 232k 3769 F13 L1: COILTRONICS, VERSAPAC VPH5-0067-R D1: CENTRAL SEMICONDUCTOR, CMSH5-60 M1: INFINEON BSC0281106LS3 Figure 13. Low IQ 24VOUT SEPIC Converter 3769fa For more information www.linear.com/LTC3769 29 LTC3769 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697 Rev B) BOTTOM VIEW—EXPOSED PAD 4.00 ±0.10 (4 SIDES) 0.70 ±0.05 4.50 ±0.05 R = 0.115 TYP 0.75 ±0.05 PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 23 24 PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 1 2 2.45 ±0.05 (4 SIDES) 2.45 ±0.10 (4-SIDES) 3.10 ±0.05 PACKAGE OUTLINE (UF24) QFN 0105 REV B 0.200 REF 0.25 ±0.05 0.50 BSC 0.25 ±0.05 0.00 – 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation CA 6.07 (.239) 6.40 – 6.60* (.252 – .260) 4.95 (.195) 4.95 (.195) DETAIL A 1.98 (.078) REF 20 1918 17 16 15 14 13 12 11 6.60 ±0.10 4.50 ±0.10 DETAIL A 2.74 (.108) 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 ±0.05 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 6.07 (.239) RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0° – 8° 0.65 (.0256) BSC 0.50 – 0.75 (.020 – .030) 0.56 (.022) REF DETAIL A IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CA) TSSOP REV K 0913 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3769fa 30 For more information www.linear.com/LTC3769 LTC3769 REVISION HISTORY REV DATE DESCRIPTION A 09/15 Corrected pin 13 and pin 14 functions. PAGE NUMBER 9 3769fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more information www.linear.com/LTC3769 tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC3769 TYPICAL APPLICATION VBIAS SENSE+ LTC3769 EXTVCC OVMODE CSS 0.1µF RITH 15k TG CB 0.1µF BG MBOT PGOOD VFB RB 475k COUTA 4.7µF ×5 + VOUT 48V 2.5A* COUTB 33µF ×2 VOUT FOLLOWS VIN WHEN VIN > 48V D INTVCC RA 12.1k MTOP BOOST ITH CITHA 100pF VIN 5V TO 55V CIN 4.7µF ×3 L 10µH SW SS CITH 15nF SENSE– PLLIN/MODE RUN FREQ 30.1k RSENSE 3mΩ GND PGND 100k CINT 4.7µF 100k 3769 F14 CIN, COUTA: TDK C3225X7S2A475M COUTB: SUNCON 63HVH33M D: BAS170W L: SER2918H-103 MBOT, MTOP: BSC028N06L53 *WHEN VIN < 13V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED. Figure 14. High Efficiency 48V/2.5A Boost Converter RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3784 2-Phase Single Output Synchronous Boost Controller 4.5V ≤ VIN ≤ 60V, VOUT Up to 60V, 50kHz to 900kHz, 4mm × 5mm QFN-28 and SSOP-28 Packages LTC3788/LTC3788-1 Multiphase, Dual Output Synchronous Step-Up Controller LTC3787 2-Phase Single Output Synchronous Boost Controller 4.5V ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz, 4mm × 5mm QFN-28 and SSOP-28 Packages LTC3786 Low IQ Synchronous Step-Up Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz Fixed Operating Frequency, 3mm × 3mm QFN-32, MSOP-16E LTC3862/LTC3862-1/ LTC3862-2 Multiphase, Dual Channel Single Output Current Mode Step-Up DC/DC Controller 4V ≤ VIN ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed Operating Frequency, SSOP-24, TSSOP-24, 5mm × 5mm QFN-24 LT3757/LT3758 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V/100V, 100kHz to 1MHz Fixed Operating Frequency, 3mm × 3mm DFN-10 and MSOP-10E LTC3859AL Low IQ, Triple Output Buck/Buck/Boost Synchronous DC/DC Controller All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 28µA LTC3789 High Efficiency Synchronous 4-Switch Buck-Boost DC/DC Controller 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, 4mm × 5mm QFN-28 and SSOP-28 LT8705 80V VIN and VOUT Synchronous 4-Switch Buck-Boost VIN Range: 2.8V (Need EXTVCC > 6.4V) to 80V, VOUT Range: 1.3V to 80V, DC/DC Controller Four Regulation Loops LTC3890/LTC3890-1/ 60V, Low IQ, Dual 2-Phase Synchronous Step-Down LTC3890-2/LTC3890-3 DC/DC Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz Fixed Operating Frequency, 5mm × 5mm QFN-32, SSOP-28 Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50μA 3769fa 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC3769 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3769 LT 0915 REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014