LTC4231 Micropower Hot Swap Controller Features Description Enables Safe Board Insertion and Removal from a Power Supply n 4µA Supply Current n 0.3µA Shutdown Current n Wide Operating Voltage Range: 2.7V to 36V n Reverse Supply Protection to –40V n Adjustable Analog Current Limit with Circuit Breaker n Automatic Retry or Latchoff on Current Fault n Overvoltage and Undervoltage Monitoring n Controls Single or Back-to-Back N-Channel MOSFETs n 12-Lead MSOP and 3mm × 3mm QFN Packages The LTC®4231 is a micropower Hot Swap™ controller that allows safe circuit board insertion and removal from a live power supply. An internal high side switch driver controls the gate of an external N-channel MOSFET. Back-to-back MOSFETs can be used for reverse supply protection down to –40V. n Applications n n n n n Battery Powered Equipment Solar Powered Systems Portable Instruments Automotive Battery Protection Energy Harvesting The LTC4231 provides a debounce delay and allows the GATE to be ramped up at an adjustable rate. After startup, the LTC4231's quiescent current drops to 4µA during normal operation with output active. UVL, UVH, OV and GNDSW monitor overvoltage and undervoltage periodically, keeping total quiescent current low. Pulling SHDN low shuts down the LTC4231 and quiescent current drops to 0.3µA. During an overcurrent fault, the LTC4231 actively limits current while running an adjustable timer. The LTC4231-1 remains off after a current fault while the LTC4231-2 automatically reapplies power after a cool-down period. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap and PowerPath are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application Battery Hot Swap with Reverse Protection SMAJ24CA 22.5mΩ Si7164DP Power-Up Waveforms VOUT 24V 2A Si5410DU 220µF SENSE 1020k GATE IN UVL 24V 1.65k CONTACT BOUNCE GATE 20V/DIV 20k SOURCE IN 20V/DIV STATUS SOURCE 20V/DIV LTC4231 UVH ILOAD 5A/DIV 4.22k OV SHDN 10ms/DIV 4231 TA01b 32.4k GNDSW TIMER GND 180nF 4231 TA01a 4321fa For more information www.linear.com/LTC4231 1 LTC4231 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage IN............................................................. –40V to 40V Input Voltages SENSE, SOURCE...................................... –40V to 40V IN–SENSE................................................ –40V to 40V SHDN, UVL, UVH, OV, GNDSW............... –0.3V to 40V Input Currents SHDN, UVL, UVH, OV, GNDSW (Note 3).............–1mA Output Voltages GATE–SOURCE (Note 4)..........................–0.3V to 13V GATE–SENSE........................................... –40V to 20V STATUS .................................................. –0.3V to 40V TIMER....................................................... –0.3V to 4V Operating Ambient Temperature Range LTC4231C................................................. 0°C to 70°C LTC4231I..............................................–40°C to 85°C LTC4231H........................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MSOP Package.................................................. 300°C Pin Configuration GATE SENSE IN TOP VIEW TOP VIEW 12 11 10 SHDN 1 SENSE IN SHDN UVL UVH OV 9 SOURCE 13 UVL 2 8 TIMER UVH 3 4 5 6 OV GNDSW GND 7 STATUS 1 2 3 4 5 6 GATE SOURCE TIMER STATUS GND GNDSW 12 11 10 9 8 7 MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 135°C/W UD PACKAGE 12-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 150°C, θJA = 68°C/W EXPOSED PAD (PIN 13) PCB CONNECTION TO GND IS OPTIONAL Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4231CUD-1#PBF LTC4231CUD-1#TRPBF LGMX 12-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C LTC4231CUD-2#PBF LTC4231CUD-2#TRPBF LGSP 12-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C LTC4231IUD-1#PBF LTC4231IUD-1#TRPBF LGMX 12-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC4231IUD-2#PBF LTC4231IUD-2#TRPBF LGSP 12-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC4231HUD-1#PBF LTC4231HUD-1#TRPBF LGMX 12-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C LTC4231HUD-2#PBF LTC4231HUD-2#TRPBF LGSP 12-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C 2 4321fa For more information www.linear.com/LTC4231 LTC4231 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4231CMS-1#PBF LTC4231CMS-1#TRPBF 42311 12-Lead Plastic MSOP 0°C to 70°C LTC4231CMS-2#PBF LTC4231CMS-2#TRPBF 42312 12-Lead Plastic MSOP 0°C to 70°C LTC4231IMS-1#PBF LTC4231IMS-1#TRPBF 42311 12-Lead Plastic MSOP –40°C to 85°C LTC4231IMS-2#PBF LTC4231IMS-2#TRPBF 42312 12-Lead Plastic MSOP –40°C to 85°C LTC4231HMS-1#PBF LTC4231HMS-1#TRPBF 42311 12-Lead Plastic MSOP –40°C to 125°C LTC4231HMS-2#PBF LTC4231HMS-2#TRPBF 42312 12-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. IN = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN VIN Input Supply Voltage Range VIN(UVL) Input Supply Undervoltage Lockout ∆VIN(HYST) Input Supply Undervoltage Lockout Hysteresis ICC Supply Current (Average) Normal On, Voltage or Current Fault IN Rising l 2.7 l 2 2.3 36 V 2.6 V 200 Start-Up or Overcurrent Shutdown (Note 5) IGATE ≤ –0.1µA, CGATE-SOURCE = 1nF, (C-Grade, I-Grade) (H-Grade) SHDN Low, GATE Pulled to GND, (C-Grade, I-Grade) (H-Grade) IN, SENSE = –40V Reverse Input l l l l l l mV 4 4 300 0.3 0.3 –2.5 10 20 600 1 2 –5 µA µA µA µA µA mA 50 53 mV SENSE ΔVSENSE(CB) Circuit Breaker Threshold (VIN – VSENSE) l 47 ΔVSENSE(ACL) Analog Current Limit ISENSE SENSE Input Current During Output Short-Circuit l 65 SHDN = High, SENSE = 12V l ΔVGATE External N-Channel Gate Drive (VGATE – VSOURCE) VIN < 7V, IGATE = 0, –0.1µA VIN ≥ 7V, IGATE = 0, –0.1µA l l ΔVGATE(H) ΔVGATE (VGATE – VSOURCE) Threshold That Deactivates the Charge Pump VIN < 7V VIN ≥ 7V VGATE(L) GATE Low Threshold IGATE(UP) GATE Pull-Up Current IGATE(FAST) 80 90 mV 0.3 1 µA 4.5 10 6.2 11.4 10 18 V V l l 5.5 11 6.5 11.7 10 18 V V To Enter Shutdown or Voltage Fault l 0.4 1.2 1.8 V GATE On, GATE = 1V l –7 –10 –13 µA GATE Fast Pull-Down Current ΔVSENSE = 0.5V, ΔVGATE = 5V l 70 130 GATE, SOURCE mA IGATE(SLOW) GATE Slow Pull-Down Current SHDN = 0V, ΔVGATE = 5V l 0.6 1 tD(ON) Turn-On Debounce Delay UVL = UVH = 2V, OV = 0V, SHDN = Step 0V to 5V l 20 40 60 mA tRETRY Auto-Retry Delay LTC4231-2 l 0.27 0.5 0.73 s tPHL(ILIM) Overcurrent to GATE Low Propagation Delay ΔVSENSE = Step 0mV to 300mV, CGATE = 1nF, ΔVGATE Crosses 1V l 0.5 1 µs ms 4321fa For more information www.linear.com/LTC4231 3 LTC4231 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. IN = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS UVL, UVH, OV, GNDSW, STATUS and SHDN VUV UVL, UVH Threshold VOV OV Threshold VOV(HYST) OV Hysteresis ILEAK(0.9V) UVL, UVH and OV Leakage Current V = 0.9V (C-Grade, I-Grade) (H-Grade) ILEAK(12V) UVL, UVH, OV, GNDSW, STATUS and SHDN Leakage Current V = 12V (C-Grade, I-Grade) (H-Grade) RON(GNDSW) Switch Resistance OV Rising I = 2mA l 0.776 0.795 0.814 l 0.776 0.795 0.814 l 3 V V 15 30 mV l l 0 0 ±10 ±100 nA nA l l 0 0 ±100 ±500 nA nA l 80 200 Ω VOL STATUS Output Low Voltage 0.2 0.4 V VSHDN SHDN Input Threshold l 0.4 0.8 1.5 V tPERIOD Sampling Period l 5 10 15 ms tSAMPLE Sampling Width l 100 200 300 µs 2.4 3.5 ms l TIMER tCB Circuit Breaker Delay CT = 100nF l 1.7 VTIMER(H) TIMER High Threshold TIMER Rising l 1.170 VTIMER(L) TIMER Low Threshold TIMER Falling l 0.07 0.1 0.13 V ITIMER(UP) TIMER Pull-Up Current TIMER = 0.5V, Circuit Breaker Tripped l –35 –50 –65 µA ITIMER(DN) TIMER Pull-Down Current TIMER = 0.5V, Circuit Breaker Recovery l 3 5 7 µA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. 4 1.193 1.216 V Note 3: These pins can be tied to voltages below –0.3V through a resistance that limits the current below 1mA. Note 4: An internal clamp limits GATE to a minimum of 13V above SOURCE. Driving this pin to voltages beyond this clamp may damage the device. Note 5: For modes where GATE is pulled to GND, ICC = IIN + ISENSE. Else ICC = IIN + ISENSE + ISOURCE. 4321fa For more information www.linear.com/LTC4231 LTC4231 Typical Performance Characteristics Average Supply Current (Normal On) vs GATE Leakage Average Supply Current vs IN 1000 5 100 VIN = 12V NORMAL ON IGATE = –0.1µA 4 Average Supply Current vs Temperature NORMAL ON IGATE = –0.1µA ICC (µA) ICC (µA) ICC (µA) 2 NORMAL ON IGATE = –1µA 10 100 3 VIN = 12V NORMAL ON IGATE = 0 1 10 1 SHUTDOWN SHUTDOWN 0 0 10 20 VIN (V) 1 –0.01 40 30 –0.1 4231 G01 Supply Current (Reverse Input) vs IN –3 14 –1 IGATE (µA) –10 –100 0.1 –50 –25 4231 G02 ∆VGATE (Average) vs GATE Leakage ∆VGATE (Average) vs IN 16 IGATE = –0.1µA 14 VIN = 12V 12 –2 10 ∆VGATE (V) ∆VGATE (V) 25 50 75 100 125 150 TEMPERATURE (°C) 4231 G03 12 ICC (mA) 0 8 –1 10 8 VIN = 2.7V 6 4 6 2 0 0 –10 –20 VIN (V) –30 –40 4231 G04 4 0 10 20 VIN (V) 40 30 4231 G05 0 0 –2 –4 –6 –8 IGATE (µA) –10 –12 4231 G06 4321fa For more information www.linear.com/LTC4231 5 LTC4231 Typical Performance Characteristics 1000 IGATE(UP) (µA) –15 –10 –5 0 0 5 10 15 VGATE (V) 20 0.800 CGATE = 1nF CTIMER = 82nF 10 0.785 0.780 OV HIGH TO LOW 0.775 GNDSW Switch Resistance vs IN 50 100 150 200 250 300 VIN – VSENSE (mV) 350 400 0.770 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 4231 G09 STATUS Output Low Voltage vs Current 600 0 4231 G08 STATUS Output Low Voltage vs Temperature 400 VIN = 12V 500 100 VIN = 12V ISTATUS = 2mA 300 90 400 VSTATUS (mV) VSTATUS (mV) RON(GNDSW) (Ω) UVL HIGH TO LOW UVH LOW TO HIGH OV LOW TO HIGH 0.790 1 4231 G07 110 VIN = 12V 0.795 100 0.1 25 UVL, UVH, OV Thresholds vs Temperature THRESHOLD (V) VIN = 12V OVERCURRENT TO GATE LOW PROPAGATION DELAY (µs) –20 Overcurrent to GATE Low Propagation Delay GATE Pull-Up Current vs VGATE 300 200 80 200 100 100 70 6 0 10 20 VIN (V) 30 40 4231 G10 0 0 1 2 3 ISTATUS (mA) 4 5 4231 G11 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4231 G12 4321fa For more information www.linear.com/LTC4231 LTC4231 Pin Functions GATE: Gate Drive for External N-Channel MOSFET. After all start-up conditions are satisfied, a 10μA pull-up current from the internal charge pump charges up ΔVGATE to the high threshold voltage ΔVGATE(H) and then turns off. The charge pump turns on again when ΔVGATE decays by more than 0.7V or every 15ms, whichever comes first, and recharges ΔVGATE to ΔVGATE(H). During GATE turnoff, a 1mA pull-down current discharges GATE to GND. During severe short circuits, a 130mA pull-down current is activated to discharge GATE to SOURCE. SENSE: Current Sense Input. Connect to the output of the current sense resistor. The circuit breaker comparator and the analog current limit amplifier monitor the voltage across the current sense resistor. During an overcurrent fault when ΔVSENSE exceeds 50mV, the circuit breaker comparator trips and triggers TIMER to ramp up. For more severe overcurrent faults, the analog current limit amplifier controls the gate of the external MOSFET to keep ΔVSENSE at 80mV. To disable the circuit breaker comparator and analog current limit amplifier, connect this pin to IN. GND: Device Ground. SOURCE: N-Channel MOSFET Source Connection. Connect this pin to the source of the external MOSFET. GNDSW: Switched GND. Connect this pin to an external resistive network to monitor IN for overvoltage or undervoltage (OV/UV). To reduce the power dissipated by this resistive divider, the LTC4231 periodically samples IN by connecting GNDSW to GND once every 10ms. Tie this pin to GND if unused. IN: Supply Voltage and Current Sense Input. This pin has a nominal undervoltage lockout threshold of 2.3V. SHDN: Shutdown Control Input. A logic high at SHDN enables the LTC4231. GATE ramps up after a debounce delay of 40ms. A logic low at SHDN activates a 1mA pulldown current at GATE, discharging it to GND. Once GATE < 1.2V, the LTC4231 enters a low current Shutdown. Connect to IN if unused. When connected to IN, if IN goes below ground, use a resistor to limit the current to ≤1mA. OV: Overvoltage Comparator Input. Connect this pin to an external resistive network to monitor IN for OV. This pin connects internally to an overvoltage comparator with a 0.795V threshold. To reduce the power dissipated by this resistive divider, the LTC4231 periodically samples IN by connecting GNDSW to GND once every 10ms. Once an OV is detected at IN, GATE and STATUS pull low. Tie this pin to GND if unused. STATUS: Status Output. Open-drain output that goes high impedance when ΔVGATE first exceeds ΔVGATE(H). The state of the pin is latched and resets (pulls low) when SHDN goes low, an UVLO occurs, an OV/UV is detected at IN or an overcurrent fault sets the internal current fault latch. This pin may be left open if unused. TIMER: Timer Input. Connect a capacitor between this pin and GND to set a 24ms/µF duration for overcurrent before the internal current fault latch trips and turns off the MOSFET. For the LTC4231-1 latchoff option, the MOSFET remains off until the current fault latch is cleared by pulling SHDN low or by cycling power. For the LTC4231-2 autoretry option, the current fault latch is cleared automatically and the GATE is ramped up after a 500ms delay. UVH, UVL: Undervoltage Comparator Input. Connect these pins to an external resistive network to monitor IN for UV. These pins connect internally to an undervoltage comparator with a 0.795V threshold. The comparator monitors UVH when GATE is low and UVL when GATE is high to implement separate undervoltage turn-on and undervoltage turn-off thresholds. To reduce the power dissipated by this resistive divider, the LTC4231 periodically samples IN by connecting GNDSW to GND once every 10ms. Once an UV is detected at these pins, GATE and STATUS pull low. Tie both pins to IN if unused. When connected to IN, for applications where IN goes below ground, use a resistor to limit the current to ≤1mA. Exposed Pad (QFN Package): The exposed pad may be left open or connected to device ground. 4321fa For more information www.linear.com/LTC4231 7 LTC4231 Functional Diagram IN SENSE – + VOLTAGE REGULATOR REVERSE VOLTAGE COMPARATOR INTERNAL VCC –+ 80mV –+ 50mV + – REVERSE VOLTAGE COMPARATOR CHARGE PUMP REFRESH TIMER ∆VGATE(H) –+ – + CHARGE PUMP f = 2MHz ∆VGATE LOW COMPARATOR 10µA + – GATE 15V SOURCE ANALOG CURRENT LIMIT AMPLIFIER GATE LOW COMPARATOR + – + – 1.2V CIRCUIT BREAKER COMPARATOR 1mA LOGIC UVL OV/UV BLOCK UVH UV COMPARATOR + – INTERNAL VCC 50µA TIMER HIGH COMPARATOR 1.193V + – + – OV/UV STROBE TIMER TIMER 0.1V + – 0.795V OV 0.795V OV COMPARATOR TIMER LOW COMPARATOR GNDSW STATUS 5µA SHDN GND 4231 FD 8 4321fa For more information www.linear.com/LTC4231 LTC4231 Operation The LTC4231 is a micropower Hot Swap controller that controls an external N-channel MOSFET to turn on and off a supply voltage in a controlled manner. This allows a circuit to be safely inserted and removed from a powered connector without glitches or connector damage from uncontrolled inrush current. When the LTC4231 is first powered up, the gate of the MOSFET is held at GND to keep it off. Pulling SHDN high and IN above undervoltage lockout (UVLO) starts an internal clock that monitors the resistive divider at IN once every 10ms by connecting GNDSW to GND. A 40ms debounce cycle is also started. Average ICC during this debounce mode is 4µA. After the 40ms debounce cycle, the LTC4231 goes into start-up mode to ramp up GATE. In this mode, all circuits blocks except the overvoltage or undervoltage (OV/UV) block are activated and ICC = 300µA. The internal charge pump supplies a 10µA pull-up current to GATE. Once ΔVGATE exceeds ΔVGATE(H), STATUS goes high impedance. This indicates that GATE is high and the power path is on. Average ICC drops to 4µA during this normal on mode as some circuit blocks are shut down and the internal charge pump periodically turns on to recharge GATE as needed. The periodic monitoring of the IN resistive divider continues as long as SHDN is high and IN ≥ 2.3V. If an OV/UV violation is detected during the IN monitoring time, the part goes into voltage fault mode (average ICC = 4µA) where GATE and STATUS is pulled to GND. The debounce cycle restarts when no OV/UV violation is detected during a subsequent IN monitoring window. The LTC4231 has a circuit breaker comparator that monitors the voltage across the current sense resistor. This comparator trips when ΔVSENSE exceeds 50mV, bringing the LTC4231 into overcurrent mode. In this mode, all circuits blocks except the OV/UV block are activated and ICC = 300µA. If ΔVSENSE > 80mV, the analog current limit amplifier limits ΔVSENSE to 80mV by servoing ΔVGATE in an active control loop. The TIMER capacitor is ramped up with a 50µA pull-up when ΔVSENSE > 50mV. When TIMER > 1.193V, the current fault latch is set, causing GATE and STATUS to pull low. The part goes into current fault mode. In current fault mode, the latchoff (LTC4231-1) version keeps TIMER and GATE low. The auto-retry (LTC4231-2) version waits 500ms before GATE is ramped up again. For both versions, the part can be reset by cycling SHDN low then high or by cycling IN to GND and back. After the reset, the LTC4231 goes through a debounce cycle before re-starting GATE. SHDN acts as a shutdown switch for the supply path. When it goes high, the LTC4231 ramps GATE up after a debounce cycle to turn on the external MOSFET. When it goes low, GATE is pulled to GND to turn off the external MOSFET. The LTC4231 then goes into shutdown mode where ICC drops to 0.3µA. IN, SENSE, GATE and SOURCE are protected against reverse inputs of up to –40V. Two reverse voltage comparators detect negative input potentials at SENSE or GATE and quickly connect GATE to SENSE. When used with backto-back MOSFETs as shown in Figure 5, this feature will isolate the load from a negative input. 4321fa For more information www.linear.com/LTC4231 9 LTC4231 Applications Information RSENSE 22.5mΩ ILOAD + CIN 100µF Z1 SMAJ24A 24V BATTERY CELL(S) R5 10Ω R1 1020k R2 1.65k R3 4.22k UV RISING = 23V UV FALLING = 22V OV RISING = 26V R4 32.4k R7 10M M1 Si7120ADN SENSE RG 1k CG 20nF GATE IN VOUT 24V 2A RSTAT 20k SOURCE UVL STATUS LTC4231 UVH SHDN C1 1nF OV GNDSW + R5 2M CL 1000µF TIMER GND CT 39nF GND 4231 F01 Figure 1. Channel Controller with Connector Enable The micropower capability of the LTC4231 makes it ideal for Hot Swap applications in battery powered systems where current load is light or intermittent and power draw is a concern. It can implement battery short circuit protection, reverse battery protection, battery voltage monitoring, power path control, hot-plug and inrush current control in off-grid, autonomous systems. Turn-On Sequence When IN is less than the UVLO level of 2.3V or SHDN is low, GATE is pulled to GND and STATUS pulls low. When IN ≥ 2.3V and SHDN goes high, an internal clock starts timing a 40ms debounce cycle. The clock also times a 200µs strobe of the resistive divider at IN every 10ms to make sure IN is not in OV/UV. Average ICC during this debounce mode is 4µA. Any OV/UV detected will stop and reset the debounce timing cycle. During this voltage fault mode, average ICC is 4µA. The debounce cycle only restarts when a subsequent IN strobe indicates that the input power is within the acceptable range, IN ≥ 2.3V and SHDN is high. When the debounce cycle of 40ms successfully completes, the LTC4231 turns on its charge pump, analog current limit amplifier and TIMER control circuit blocks as it goes 10 into start-up mode (ICC = 300µA). The external MOSFET is turned on by charging up the GATE with a 10μA charge pump generated current source. At start-up, the MOSFET current is typically dominated by the current charging the load capacitor CL. If ΔVSENSE > 80mV, the analog current limit amplifier controls the gate of the MOSFET in a closed loop. This keeps the start-up inrush current at 80mV/RSENSE. When ΔVSENSE > 50mV, the TIMER capacitor charges up with an internal 50µA pull-up current. DEBOUNCE START-UP NORMAL ON GATE 20V/DIV OUT 20V/DIV ILOAD 2A/DIV TIMER 0.5V/DIV 1ms/DIV 4231 F02 Figure 2. Inrush Control by Analog Current Limit 4321fa For more information www.linear.com/LTC4231 LTC4231 Applications Information In most applications, keeping the inrush current at analog current limit is an acceptable start-up method if the TIMER delay is long enough to avoid setting the current fault latch and the MOSFET has adequate safe operating margin. However, for more flexibility in design (See the Design Example section), a capacitor from GATE to GND (Figure 1) can be used to limit the VGATE slew rate for inrush current control. VGATE rises with a slope equal to 10μA/CG (Figure 3). The supply inrush current is then limited to: IINRUSH = CL • 10µA CG In the single MOSFET configuration (Figure 1), the 1mA pull-down from GATE to GND also discharges the load capacitor CL to GND once GATE goes below SOURCE. Overcurrent Fault Once ΔVGATE exceeds ΔVGATE(H), STATUS goes high impedance. ICC drops from 300µA to 4µA (average) during this normal on mode as some circuit blocks are shut down and the internal charge pump periodically turns on when ΔVGATE droops by 0.7V or every 15ms, whichever comes first (Figure 7). DEBOUNCE In the back-to-back MOSFET configuration as shown in Figure 5, SOURCE will also be pulled to GND via the parasitic body diode between GATE and SOURCE, cutting off the load from IN. This configuration is suitable in power path control and reverse battery protection applications where IN is likely to go below GND. START-UP NORMAL ON GATE 20V/DIV OUT 20V/DIV ILOAD 0.5A/DIV 20ms/DIV 4231 F03 Figure 3. Inrush Control by Limiting VGATE Slew Turn-Off Sequence The MOSFET switch can be turned off by SHDN going low, an OV/UV event, an overcurrent setting the current fault latch or IN dropping below its UVLO voltage. Under any of these conditions, STATUS pulls low and the MOSFET is turned off with a 1mA current pulling down from GATE to GND. The 50mV circuit breaker threshold sets the maximum load current allowed under steady state conditions. However, the LTC4231 allows mild overcurrents during supply or load transients when ΔVSENSE momentarily exceeds 50mV but stays below the 80mV analog current limit threshold. For severe overcurrents when ΔVSENSE exceeds 80mV, the analog current limit amplifier controls ΔVGATE to regulate ΔVSENSE to 80mV. The durations of these transient overcurrents must be less than the circuit breaker delay (tCB) which can be adjusted using the capacitor CT at the TIMER pin. When ΔVSENSE exceeds 50mV, the LTC4231 goes into overcurrent mode. CT is charged with a 50μA pull-up. If the overcurrent is transient and ΔVSENSE goes below 50mV before TIMER reaches 1.193V, the 50μA pull-up on TIMER switches to a 5μA pull-down. Multiple overcurrents with a duty cycle > 10% can thus eventually integrate TIMER to 1.193V. When TIMER reaches 1.193V, the LTC4231 goes into current fault mode and sets an internal current fault latch. The external MOSFET will be cut off by a 1mA pull-down from GATE to GND while STATUS pull-down is asserted. The time in which LTC4231 stays in overcurrent mode before going into current fault mode is called the circuit breaker delay and is given by: tCB = CT • 24 [ms/µF] 4321fa For more information www.linear.com/LTC4231 11 LTC4231 Applications Information DEBOUNCE START-UP 300µA AVERAGE ICC 4µA OVER- CURRENT CURRENT FAULT NORMAL ON SHUTDOWN DEBOUNCE 300µA 4µA (IGATE(LEAKAGE) ≤ 0.1µA) START-UP 300µA 4µA 0.3µA 4µA NORMAL ON 4µA (IGATE(LEAKAGE) ≤ 0.1µA) VOLTAGE FAULT 4µA VOVOFF IN GNDSW 200µs ∆VGATE(H) 0.7V GATE SOURCE ∆VSENSE(CB) ∆VSENSE VTIMER(H) VTIMER(L) TIMER SHDN STATUS 40ms tCB 40ms 4231 F04 Figure 4. LTC4231-1 Overcurrent 12 4321fa For more information www.linear.com/LTC4231 LTC4231 Applications Information Auto-Retry vs Latchoff During current fault mode, GATE is held low and TIMER is discharged to GND. Once TIMER < 0.1V, average ICC goes to 4µA and the internal current fault latch is ready to be reset. The LTC4231-2 (automatic retry) waits for a 500ms retry delay after which the internal current fault latch is reset and GATE ramps up to turn the MOSFET back on. The LTC4231-1 (latchoff) version does not restart automatically. Pulling SHDN low for >100µs will reset the internal current fault latch. When SHDN goes high, GATE ramps up after a debounce cycle. Alternatively, IN can be pulled to GND for >100µs then cycled back up again. This UVLO event will reset the internal current fault latch and GATE ramps up after a debounce cycle. A UV/OV detected at IN also resets the internal current fault latch and GATE ramps up after a debounce delay. Analog Current Limit Loop Stability The analog current limit loop on GATE is compensated by the parasitic gate capacitance of the external MOSFET. No further compensation components are normally required. If a small MOSFET with CISS ≤ 1nF is chosen, an RG and CG compensation network connected at GATE may be required (Figure 1) to ensure stability. The resistor, RG, connected in series with CG accelerates the MOSFET gate recovery after a fast gate pull-down. The value of CG should be ≤100nF. An additional 10Ω resistor (R5 in Figure 1) should be added close to the MOSFET gate to prevent possible parasitic oscillation due to trace/wire inductance and capacitance. If an OV or UV violation is detected, the STATUS pulls low and a 1mA pull-down will be activated between GATE and GND to turn off the external MOSFET. When GATE goes <1.2V, average ICC drops to 4µA as the LTC4231 goes into voltage fault mode. It stays in this mode until a subsequent IN strobe sees no OV/UV. The LTC4231 then re-starts after a debounce cycle. Strobing the resistive divider reduces power consumption as the external resistors as well as the internal OV/UV comparators do not dissipate power in between strobes. For a 1M string of resistors used to monitor a VIN of 24V, this strobing scheme reduces the current consumption from 24µA to 0.48µA as the strobing duty cycle is 2% (200µs/10ms). The OV/UV comparators dissipate 35µA during IN strobing. The 2% duty cycle reduces this to an average current of 0.7µA. Note that the response time to an OV/UV event can be as long as 10ms. The four resistors allow three thresholds to be configured. They are the UV rising threshold (VUVON), the UV falling threshold (VUVOFF) and the OV rising threshold (VOVOFF). The OV falling threshold is set by internal hysteresis to be 1.8% below the OV rising threshold. Using the comparator threshold as 0.795V and choosing appropriate values for RTOTAL and R4, the resistor values can be calculated as follows: RTOTAL = R1+R2+R3+R4 Monitor OV and UV Faults When IN is above UVLO and SHDN is high, an internal clock times a 200µs strobe of the resistive divider at IN every 10ms. During this 200µs strobe, the normally high impedance GNDSW is connected to GND with an internal 80Ω switch and the comparators connected to UVH, UVL and OV are awakened from sleep mode. The comparators sense the voltages on the resistive divider, and their outputs are latched at the end of the strobe window. 0.795V R4 = • RTOTAL VOVOFF V R3 = OVOFF − 1 • R4 VUVON V V R2 = UVON − 1 • OVOFF • R4 VUVOFF VUVON U R1= OVOFF − 1 • R4 −R3 −R2 0.795V It is recommended that the total value of the resistor string be less than 2M and traces at UVH, UVL, and OV kept short to minimize parasitic capacitance and improve settling time. 4321fa For more information www.linear.com/LTC4231 13 LTC4231 Applications Information Reverse Input Protection internal switch is activated to connect GATE to SENSE. The body diode of M1 pulls SOURCE to a diode above SENSE. Since M2 is off and its body diode is in the reverse blocking mode, the negative voltage is blocked by the VDS of M2. Negative voltages at IN can occur if a battery is plugged in backwards or a negative supply is inadvertently connected. Back-to-back N-channel MOSFETs can be used as in Figure 5 to prevent the negative voltage from passing to the output load. Figure 6 shows the waveforms when the application circuit in Figure 5 is hot plugged to –24V. Due to the parasitic inductance at IN, SENSE and GATE, the voltages ring significantly below –24V. The TransZorb helps to clamp the negative undershoot and a 40V MOSFET is selected for M2 to survive this undershoot. IN, SENSE, GATE and SOURCE are protected against reverse inputs of up to –40V. When the LTC4231's reverse voltage comparators detect a negative voltage at SENSE, an RSENSE 22.5mΩ ILOAD M1 Si7164DP M2 Si5410DU VOUT 24V 2A RX 10Ω Z1 SMAJ24CA CX 0.1µF CL 100µF R1 1020k R2 1.65k 24V R3 4.22k R4 32.4k SENSE GATE IN RSTAT 20k SOURCE UVL STATUS LTC4231 UV RISING = 23V UV FALLING = 22V OV RISING = 26V UVH OV SHDN GNDSW TIMER GND CT 82nF 4231 F05 Figure 5. Back-to-Back MOSFETs Protect Against Reverse Input IN 20V/DIV GATE 20V/DIV OUT 20V/DIV 1µs/DIV 4231 F06 Figure 6. LTC4231 in Reverse Input Mode 14 4321fa For more information www.linear.com/LTC4231 LTC4231 Applications Information Achieving Low Quiescent Current Table 1 summarizes the average ICC of the various operating modes of the LTC4231. Table 1 MODE Start-Up or Overcurrent Debounce, Normal On, Voltage or Current Fault Shutdown Reverse Input ICC (NORM) ICC (MAX) 300µA 600µA 4µA 10µA 0.3µA 1µA –2.5mA –5mA To lower ICC when GATE is high, the LTC4231 operates in normal on mode, where the charge pump delivers pulses of current to the GATE capacitance (either an external CG or the parasitic capacitance of the external MOSFETs) to boost ΔVGATE to ΔVGATE(H) followed by sleep periods when the GATE capacitance holds up GATE. Leakage will cause ΔVGATE to droop during these sleep periods. When the ΔVGATE low comparator detects ΔVGATE drooping by more than 0.7V, it will activate the charge pump to boost ΔVGATE back to ΔVGATE(H) before returning to sleep mode. In addition to the ΔVGATE low comparator, there is a charge pump refresh timer that turns on the charge pump every 15ms to boost ΔVGATE back to ΔVGATE(H). This timer is reset when the charge pump turns on. When in charge pump sleep mode the LTC4231 consumes 2µA. When the charge pump is on to deliver a current pulse IGATE = –0.1µA to GATE, ICC briefly goes up to 200µA. The amount of leakage at GATE (IGATE(LEAKAGE)) will determine the duty cycle of the charge pump. Figure 7 shows start-up and ∆VGATE regulation (with different IGATE(LEAKAGE)) waveforms from the Figure 5 application circuit. As the average current delivered to GATE during the current pulse is around 15µA, the duty cycle of the charge pump for a IGATE(LEAKAGE) of 0.1µA is 0.1/15 = 0.67%. The average current due to ΔVGATE regulation is then 0.67% • 200µA = 1.3µA. When added to the average current due to OV/UV strobing (0.7µA) and charge pump sleep mode current (2µA), the average quiescent current of the LTC4231 during the normal on mode is 1.3µA + 0.7µA + 2µA = 4µA. The normal on mode average supply current can be estimated using the formula: ICC = 2.7µA + 13.3 •IGATE(LEAKAGE) The Typical Performance Characteristics section shows a graph of average ICC (normal on) against IGATE(LEAKAGE). Shutdown Mode When SHDN goes low, STATUS pulls low and a 1mA pull-down will be activated between GATE and GND to cut off the external MOSFET. When GATE reaches <1.2V, ICC drops to 0.3µA as the LTC4231 goes into shutdown mode. When SHDN goes high, GATE ramps up after the 40ms debounce cycle. Figure 8 shows the application in Figure 5 going into shutdown mode. IGATE = –1µA GATE 20V/DIV ENTERS SHUTDOWN MODE SOURCE 20V/DIV STATUS 20V/DIV ∆VGATE 2V/DIV SHDN 5V/DIV ICC 200µA/DIV 5ms/DIV 4231 F07 Figure 7. Regulating ΔVGATE During Normal On Mode 20µs/DIV 4231 F08 Figure 8. SHDN Going Low Activates Shutdown Mode 4321fa For more information www.linear.com/LTC4231 15 LTC4231 Applications Information Supply Transient Protection When the capacitances at the input and output are very small, rapid changes in current during an output shortcircuit event can cause transients that exceed the 40V absolute maximum ratings of IN, SENSE and SOURCE. To minimize such spikes, use wider traces or heavier trace plating to reduce the power trace inductance. Also, bypass locally with a 10μF electrolytic and 0.1μF ceramic if hot plug inrush current is not a concern. Alternatively, clamp the input with a transient voltage suppressor (Z1 in Figure 5). A 10Ω, 0.1μF snubber damps the response and reduces ringing (RX and CX in Figure 5). Design Example As a design example, take the following specifications for the Figure 5 application circuit. The application is rated for a VIN of 24V at 2A, CL = 100µF. UV rising = 23V, UV falling = 22V, OV rising = 26V. Sense resistor: RSENSE = ∆VSENSE(CB)(MIN) 2A = 47mV = 23.5mΩ 2A Use RSENSE = 22.5mΩ for margin. Worst case analog current limit: ILIMIT(MIN) = ILIMIT(MAX) = ∆VSENSE(ACL)(MIN) 22.5mΩ ∆VSENSE(ACL)(MAX) 22.5mΩ 65mV = 2.89A 22.5mΩ 90mV = = 4A 22.5mΩ = Calculate the worst case time it takes to charge up CL in analog current limit: tCHARGE(MAX) = CL • VIN ILIMIT(MIN) = 100µF • 24V = 0.9ms 2.89A For inrush control using analog current limit, tCHARGE(MAX) must be less than the circuit breaker delay (tCB) for a proper start-up. 16 The worst case power dissipation in MOSFET M1 occurs during a severe overcurrent fault when the current is controlled by analog current limit for the duration of tCB: PDISS = VIN • ILIMIT(MAX) = 24V • 4A = 96W The SOA (safe operating area) curve for the Si7164DP MOSFET shows that it can withstand 180W for 10ms. So choose a tCB that is less than 10ms but higher than 0.9ms (tCHARGE(MAX)). In this case, use tCB = 2ms. CT = tCB 2ms = = 0.082µF = 82nF 24 24 If a low inrush current (< ∆VSENSE(CB)) is preferred, refer to the Figure 1 application circuit which uses a gate capacitor CG to limit the inrush current. Choose IINRUSH = 0.5A which is set using CG: CG = CL IINRUSH • 10µA = 1000µF • 10µA = 20nF 0.5A The time to charge up CL with 0.5A is: tCHARGE = CL • VIN 1000µF • 24V = = 48ms IINRUSH 0.5A In this case tCHARGE can be longer than tCB with no startup issue. The average power dissipation in the MOSFET M1 during this start-up is: PDISS = VIN •IINRUSH 2 = 24V • 0.5A = 6W 2 The SOA of the MOSFET M1 must be evaluated to ensure that it can withstand 6W for 48ms. The SOA curve of the Si7120ADN withstands 10W for 360ms, satisfying the requirement. The purpose of MOSFET M2 is to block the reverse path from OUT (drain of M2) to IN when GATE pulls to GND so that IN can go lower than OUT or even negative. Choose a 40V MOSFET to withstand a worse case reverse DC voltage of –24V. The Si5410DU offers a good choice with a maximum RDS(ON) of 18mΩ at VGS = 10V. 4321fa For more information www.linear.com/LTC4231 LTC4231 Applications Information The IN monitoring resistors R1–R4 should be chosen to yield a total divider resistance of between 1M to 2M for both low power and good transient response. Using the formulas from the Monitor OV and UV Faults section, R1–R4 are calculated as follows (with all resistor values rounded up to the nearest 1% accurate standard values): Choose R1 + R2 + R3 + R4 = 1000kΩ 0.795V R4 = • 1000kΩ VOVOFF Choose R4 = 32.4kΩ to give total divider resistance: R1 + R2 + R3 + R4 = 1060kΩ. V 26V R3 = OVOFF − 1 • R4 = − 1 • 32.4kΩ = 4.22kΩ 23V VUVON V V R2 = UVON − 1 • OVOFF • R4 VUVOFF VUVON 23V 26V − 1 • = • 32.4kΩ = 1.65kΩ 22V 23V V R1= OVOFF − 1 • R4 −R3 −R2 0.795V 26V − 1 • 32.4kΩ − 4.22kΩ − 1.65kΩ = 1020kΩ = 0.795V Layout Considerations To achieve accurate current sensing, a Kelvin connection for the sense resistor is recommended. The PCB layout for the resistor should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistors and the power MOSFETs should include good thermal management techniques for optimal device power dissipation. In Hot Swap applications where load currents can be high, narrow PCB tracks exhibit more resistance than wider tracks and operate at elevated temperatures. 1oz copper exhibits a sheet resistance of about 0.5mΩ/square. The minimum trace width for 1oz copper foil is 0.5mm per amp to make sure the trace stays at a reasonable temperature. Using 0.8mm per amp or wider is recommended. Thicker top and bottom copper such as 3oz or more can improve electrical conduction and reduce PCB trace dissipation. If a resistor R5 (see Figure 1) is used, place it as close as possible to M1's gate input. This will limit the parasitic trace capacitance that leads to M1 self-oscillation. The transient voltage suppressor, Z1, when used, should be mounted close to the LTC4231 using short lead lengths. A recommended PCB layout for the sense resistor and back-to back power MOSFETs is shown in Figure 9. MOSFET M1 MOSFET M2 RSENSE R5 Z1 LTC4231 RSTAT 4231 F09 Figure 9. Recommended Layout 4321fa For more information www.linear.com/LTC4231 17 LTC4231 Applications Information Additional Applications Figure 10 shows a reverse-battery protected application featuring the LTC2955 micropower push-button controller. A press on the push button switch will turn on the LTC4231 while a subsequent press will turn off the LTC4231. In the event the LTC4231 is unable to power-up successfully when EN goes high, the STATUS output is fed back to the KILL input in order to place the LTC4231 back in the very low-power Shutdown mode. Figure 11 illustrates a 36V application with an UV rising threshold of 35V, an UV falling threshold of 33V and an OV rising threshold of 38V. As the IN operating voltage is so near to its 40V absolute maximum rating, a suitable TransZorb is not available to protect IN. Instead, a floating GND architecture is used to help the LTC4231 survive possible voltage transients during short circuit events. This architecture is strictly for handling IN transients during 36V operation. It does not allow DC VIN operation > 39V. RSENSE 45mΩ M1 Si7120ADN M2 Si5410DU Z1 SMAJ28CA VOUT 25V 1A CL 100µF RIN 10k R1 1070k LTC2955-1 VIN 25V OUT INT CIN 100nF R2 1.47k EN RSTAT 4.7M KILL R4 30.9k TIMER PB ON GND R3 4.32k C2 180nF SENSE IN UVL GATE SOURCE LTC4231 UVH STATUS OV TIMER GNDSW SHDN GND CT 180nF UV RISING = 25V UV FALLING = 24V OV RISING = 28.5V 4231 F10 Figure 10. Micropower Push Button and Hot Swap Controllers with Reverse Battery Protection 18 4321fa For more information www.linear.com/LTC4231 LTC4231 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package MS Package 12-Lead Plastic MSOP 12-Lead Plastic MSOP Rev A) (Reference LTC DWG # 05-08-1668 (Reference LTC DWG # 05-08-1668 Rev A) 0.889 ±0.127 (.035 ±.005) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.65 (.0256) BSC 0.42 ±0.038 (.0165 ±.0015) TYP 12 11 10 9 8 7 RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) 0° – 6° TYP 0.406 ±0.076 (.016 ±.003) REF GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 1 2 3 4 5 6 0.650 NOTE: (.0256) 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MS12) 0213 REV A 4321fa For more information www.linear.com/LTC4231 19 LTC4231 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UD Package 12-Lead Plastic QFN (3mm × 3mm) UD Package (Reference LTC DWG Rev Ø) 12-Lead Plastic QFN# 05-08-1855 (3mm × 3mm) (Reference LTC DWG # 05-08-1855 Rev Ø) 0.70 ±0.05 3.50 ±0.05 1.65 ±0.05 2.10 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER R = 0.115 TYP 0.75 ±0.05 11 12 PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 1 2 1.65 ±0.10 (4-SIDES) (UD12) QFN 0709 REV Ø 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 20 0.25 ±0.05 0.50 BSC 4321fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC4231 LTC4231 Revision History REV DATE DESCRIPTION A 09/15 Added H-grade information PAGE NUMBER 2, 3, 4 Updated specifications: VGATE(L), IGATE(UP), tD(ON), tRETRY, tPERIOD, tSAMPLE, tCB 3,4 4321fa For more information www.linear.com/LTC4231 21 LTC4231 Typical Application RSENSE 45mΩ 36V Z1 SMBJ36CA RX 10Ω CX 0.1µF M1 Si7164DP M2 Si7120ADN + Z2 BZX84C39 Z3 BZX84C39 R1 787k R6 1M R2 1.1k R3 1.43k R4 16.9k SENSE IN CL 100µF RSTAT 1M GATE SOURCE UVL VOUT 36V 1A OUT STATUS LTC4231 UVH OV GNDSW SHDN TIMER CT 270nF GND 300Ω UV RISING = 35V UV FALLING = 33V OV RISING = 38V 10nF 4231 F11 Figure 11. 36V Hot Swap Application with Reverse Protection Related Parts PART NUMBER DESCRIPTION COMMENTS LTC4361 Overvoltage/Overcurrent Protection Controller 220µA IQ, 2.5V to 5.5V Operation, 80V Protection LTC4365 OV, UV and Reverse Supply Protection Controller 25µA IQ, 2.5V to 34V Operation, –40V Reverse Input LTC4359 Ideal Diode Controller with Reverse Input Protection 150µA IQ, 9µA in Shutdown, 4V to 80V Operation LTC4364 Surge Stopper/Hot Swap with Ideal Diode 370µA ICC, 4V to 80V Operation, –40V Reverse Input, –20V Reverse Output LTC2960 Nano-Current Dual Voltage Monitor 850nA IQ, 2.5V to 36V Operation, 1.5% Accuracy LTC4229 Ideal Diode and Hot Swap Controller 2.9V to 18V Operation, 2mA IIN, 0.5µs Ideal Diode Turn-On/Off LTC4232 5A Integrated Hot Swap Controller Integrated 33mΩ MOSFET with Sense Resistor, 2.9V to 15V Operation LTC2955 Pushbutton On/Off Controller Automatic Turn-On, 1.2µA IQ, 1.5V to 36V Operation LTC4417 Prioritized PowerPath™ Controller 28µA IQ, 2.5V to 36V Operation, –42V Reverse Input 22 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC4231 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4231 4321fa LT 0915 REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014