PS10/PS11 PS10 - Active High PS11 - Active Low Initial Release Quad Power Sequencing Controller Features Description Sequencing of Four or More* Supplies, ICs, or Subsystems Independently Programmable Delays Between Open Drain PWRGD Flags (5ms to 200ms) ±10V to ±90V Operation Tracking in Combination with Schottky Diodes Input Supervisors Including: o UV/OV Lock Out/Enable o Power-On-Reset (POR) Low Power Consumption, 0.4mA Supply Current Small SO-14 Package Many of today’s high performance FPGA’s, Microprocessors, DSP and industrial/embedded subsystems require sequencing of the input power. Historically this has been accomplished: i) discretely using comparators, references & RC circuits; ii) using expensive programmable controllers; or iii) with low voltage sequencers requiring resistor drop downs and several high voltage optocoupler or level shift components. The PS10/11 saves board space, improves accuracy, eliminates optocouplers or level shifts and reduces overall component count by combining four timers, programmable input UV/OV supervisors, a programmable POR and four 90V open drain outputs. A high reliability, high voltage, junction isolated process allows the PS10/11 to be connected directly across the high voltage input rails. *By Daisy-Chaining PS10/11’s Applications The power-on-reset interval (POR) may be programmed by a capacitor on Cramp. To sequence additional systems, PS10/11 may be daisy chained together. If at any time the input supply falls outside the UV/OV detector range the PWRGD outputs will immediately become INACTIVE. Down sequencing may be accomplished with additional components (see page 11). Power Supply Sequencing -48V Telecom and Networking Distributed Systems -24V Cellular and Fixed Wireless Systems -24V PBX Systems +48V Storage Systems FPGA, Microprocessor Tracking Industrial/Embedded System Timing/Sequencing High Voltage MEMs Driver’s Supply Sequencing High Voltage Display Driver’s Supply Sequencing The PS10/PS11 is available in a space saving SO-14 package. Typical Application Circuit Waveform (49.9k pull-up on PS11 PWRGD pins) GND or +48V 14 487K /EN VIN 6 PWRGD-D / PWRGD-D UV PWRGD-C / PWRGD-C 6.81K PWRGD-B / PWRGD-B 5 9.76K 7 PS10/PS11 OV VEE TB RTB TD TC 11 12 RTC 13 RTD PWRGD-A / PWRGD-A Ramp 1 +12V DC/DC CONVERTER COM 2 3 4 /EN +5V DC/DC CONVERTER COM /EN 10 +3.3V DC/DC CONVERTER COM 10nF /EN +2.5V DC/DC CONVERTER -48V or GND COM Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. Relative to Negative Rail A051204 Supertex, Inc. • 1235 Bordeaux Drive, Sunnyvale, CA 94089 • Tel: (408) 222-8888 • FAX: (408) 222-4895 • www.supertex.com 1 PS10/PS11 Absolute Maximum Ratings* VEE referenced to VIN pin +0.3V to -100V VPWRGD referenced to VEE voltage -0.3V to +100V VUV and VOV referenced to VEE Voltage -0.3V to 12V Operating Ambient Temperature -40°C to +85°C Operating Junction Temperature -40°C to +125°C Storage Temperature Range Ordering Information Active State of Power Good Flags Package Options High PS10NG Low PS11NG -65° to +150°C Power Dissipation @ 25°C, 14-Pin SOIC 14 Pin SOIC 750mW *Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Electrical Characteristics (-10V ≤ V IN Symbol Parameter ≤ -90V, TA = 25°C unless otherwise specified) Min Typ Max Units Conditions -10 V 400 450 µA VEE = -48V 1.16 1.22 1.28 V Low to High Transition 1.06 1.12 1.18 V High to Low Transition Supply (Referenced to VIN pin) VEE Supply Voltage IEE Supply Current -90 OV and UV Control (Referenced to VEE pin) VUVH VUVL VUVHY IUV UV High Threshold# # UV Low Threshold # UV Hysteresis 100 UV Input Current # mV 1.0 nA VUV = VEE + 1.9V VOVH OV High Threshold 1.16 1.22 1.28 V Low to High Transition VOVL # 1.06 1.12 1.18 V High to Low Transition VOVHY IOV OV Low Threshold OV Hysteresis # 100 OV Input Current mV 1.0 nA VUV = VEE + 1.9V # Specifications apply over 0°C ≤ TA ≤ 70°C Power Good Timing (Test Conditions: CRAMP = 10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V) Ramp Pin Output Current 10 µA tPWRGD-A Time from UV High to PWRGD-A 8.8 ms VEE = -48V, CRAMP = 10nF, see Typical Application Circuit tPWRGD-B Maximum time from PWRGD-A to PWRGD-B 150 200* 250 ms RTB = 120kΩ tPWRGD-B Minimum time from PWRGD-A to PWRGD-B 3.0 5.0* 8.0 ms RTB = 3kΩ tPWRGD-C Maximum time from PWRGD-B to PWRGD-C 150 200* 250 ms RTC = 120kΩ tPWRGD-C Minimum time from PWRGD-B to PWRGD-C 3.0 5.0* 8.0 ms RTC = 3kΩ tPWRGD-D Maximum time from PWRGD-C to PWRGD-D 150 200* 250 ms RTD = 120kΩ tPWRGD-D Minimum time from PWRGD-C to PWRGD-D 3.0 5.0* 8.0 ms RTD = 3kΩ IRAMP *Note: Variations will track. For example if tPWRGD-A is 250ms then so will be tPWRGD-B/C/D. Contact factory for tighter tolerance version. Power Good Outputs (Test Conditions: VUV = VEE + 1.9V, VOV = VEE + 0.5V) VPWRGD-x(hi) Power Good Pin Breakdown Voltage 90 VPWRGD-x(lo) Power Good Pin Output Low Voltage 0.4 IPWRGD-x(lk) Maximum Leakage Current <1.0 2 V PWRGD-x = HI Z 0.5 V IPWRGD = 1mA, PWRGD-x = LOW 10 µA VPWRGD = 90V, PWRGD-x = HI Z A051204 PS10/PS11 PWRGD Logic Model Condition PS10 INACTIVE (not ready) 0 VEE ACTIVE (Ready) 1 HI Z INACTIVE (not ready) 1 HI Z ACTIVE (Ready) 0 VEE PS11 PWRGD-A/B/C/D Pinout PWRGD-D (PS10) PWRGD-D (PS11) 1 14 V IN PWRGD-C (PS10) PWRGD-C (PS11) 2 13 TD PWRGD-B (PS10) PWRGD-B (PS11) 3 12 TC PWRGD-A (PS10) PWRGD-A (PS11) 4 11 TB OV 5 10 RAMP UV 6 9 NC V EE 7 8 NC Top View Pin Description PWRGD-D – This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-C goes active. PWRGD-C – This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-B goes active. PWRGD-B – This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-A goes active. PWRGD-A – This open drain Power Good Output Pin is held inactive on initial power application and goes active one POR delay after the UV pin goes above its High threshold (provided VIN stays within the UV/OV window during this period). To function as an indicator a pullup resistor must be connected from this pin to a voltage rail no more than 90V from VEE. OV – This Over Voltage (OV) sense pin, when raised above its high threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin falls below the low threshold limit, initiating a new start-up cycle. VEE - This pin is the negative terminal of the power supply input to the circuit. VIN – This pin is the positive terminal of the power supply input to the circuit and can withstand 90V with respect to VEE. TD – The resistor connected from this pin to VEE pin sets the time delay from PWRGD-C going active to PWRGD-D going active. TC – The resistor connected from this pin to VEE pin sets the time delay from PWRGD-B going active to PWRGD-C going active. TB – The resistor connected from this pin to VEE pin sets the time delay from PWRGD-A going active to PWRGD-B going active. RAMP – This pin provides a current output so that a timing ramp is generated when a capacitor is connected. This timing Ramp is used to program POR and the time from satisfaction of the UV/OV supervisors to PWRGD-A. NC– No Connect. This pin can be grounded or left floating. UV – This Under Voltage (UV) sense pin, when lowered below its low threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin rises above the low threshold limit, initiating a new start-up cycle. 3 A051204 PS10/PS11 Functional Block Diagram Band Gap Reference UV Vint Regulator & POR - V IN + Vbg Logic UVLO PWRGD-A - OV + PWRGD-B VEE PWRGD-C Vint - + PWRGD-D Programmable Timer 10uA Vint - 1.2V TB RAMP Functional Description The PS10/PS11 are designed to sequence up to 4 power supply modules, ICs or subsystems when the backplane voltage is within the programmed Under-voltage and Overvoltage limits. The power good open drain outputs are sequentially enabled starting from PWRGD-A to PWRGDD. The time delay between power goods is programmable up to 200ms simply by changing the value(s) of RTB, RTC, and RTD. The initial time between satisfaction of the UV/OV supervisors & PWRGD-A can be programmed with Cramp. TC TD tive transition. PWRGD-D will change into an active state after a programmed time delay from PWRGD-C inactive to active transition. The controller continuously monitors the UV and OV pins as long as the internal UVLO and POR circuits are satisfied. At any time during the start up cycle or thereafter, crossing the UV low and OV high limits will cause an immediate discharge on Cramp and reset on the power good pins. When the input voltage returns to a value within the programmed UV and OV limits, a new start up sequence will initiate immediately. Description of Operation Programming the Under and Over Voltage Limits During the initial power application, the Power Good pins are held low (rising with VIN) for PS10 and high for the PS11. Once the internal under voltage lock out has been satisfied, the circuit checks the input supply under voltage (UV) and over voltage (OV) sense circuits to ensure that the input voltage is within programmed limits. These limits are determined by the selected values for R1, R2, and R3, which form a voltage divider. The UV and OV pins are connected to comparators with nominal 1.17V thresholds and 100mV of hysteresis (1.17V ± 50mV). They are used to detect under voltage and over voltage conditions at the input to the circuit. Whenever the OV pin rises above its high threshold (1.22V) or the UV pin falls below its low threshold (1.12V), the PWRGD outputs immediately deactivate. At the same time, a 10µA current source is enabled, charging the external capacitor connected to the ramp pin. The rise time of the ramp pin is determined by the value of the capacitor (10µA/Cramp). When the ramp voltage reaches 8.8V, the PWRGD-A pin will change into an active state. PWRGD-B will change into an active state after a programmed time delay from PWRGD-A inactive to active transition. PWRGD-C will change into an active state after a programmed time delay from PWRGD-B inactive to ac- Calculations can be based on either the desired input voltage operating limits or the input voltage shutdown limits. In the following equations the shutdown limits are assumed. The undervoltage and overvoltage shut down thresholds can be programmed by means of the three resistor divider formed by R1, R2 and R3. Since the input currents on the UV and OV pins are negligible the resistor values may be calculated as follows: 4 A051204 PS10/PS11 From the calculated resistor values the OV and UV start up threshold voltages can be calculated as follows: UVOFF = VUVL = 1.12 = (VEEUV(off)) x (R2+R3)/(R1+R2+R3) UVON = VUVH = 1.22 = (VEEUV(on)) x (R2+R3)/(R1+R2+R3) OVOFF = VOVL = 1.22 = (VEEOV(off)) x R3/(R1+R2+R3) OVON = VOVL = 1.12 = (VEEOV(on)) x R3/(R1+R2+R3) Where (VEEUV(off)) and (VEEOV(off)) relative to VEE are Under and Over Voltage Shut Down Threshold points. Where (VEEUV(on)) and (VEEOV(on)) are Under and Over Voltage Start Up Threshold points relative to VEE. If we select a divider current of 100 µA at a nominal operating input voltage of 50 Volts, then Then (VEEUV(on)) = 1.22 x (R1+R2+R3)/(R2+R3) R1+R2+R3 = 50V/100µA = 500kΩ (VEEUV(on)) = 1.22 x (487k+6.65k+9.31k)/(6.65k+9.31k ) = 38.45V From the second equation, for an OV shut down threshold of 65V, the value of R3 may be calculated. And (VEEOV(on)) = 1.12 x (R1+R2+R3)/R3 OVOFF = 1.22 = (65xR3)/500k (VEEOV(on) ) = 1.12 x (487k +6.65k +9.31k)/9.31k = 60.51V R3 = (1.22x 500k)/65 = 9.38k Therefore, the circuit will start when the input supply voltage is in the range of 38.45V to 60.51V. The closest 1% value is 9.31kΩ. From the first equation, for a UV shut down threshold of 35V, the value of R2 can be calculated. UVOFF = 1.12 = 35 x (R2+R3)/ 500k R2 = ((1.12 x 500k)/35) – 9.76k = 6.69k 6.65kΩ is a standard 1% value Then R1 = 500k – R2 – R3 = 484.04kΩ. 487kΩ, is a standard 1% value. 5 A051204 PS10/PS11 Undervoltage/Overvoltage Operation PWRGD Flags Delay Programming GND When the ramp voltage hits Vint – 1.17V, PWRGD-A becomes active indicating that the input supply voltage is within the programmed limits. PWRGD-B goes active after a programmed time delay after PWRGD-A went active. PWRGD-C goes active after a programmed time delay after PWRGD-B went active. PWRGD-D goes active after a programmed time delay after PWRGD-C went active. UVOFF UVON Vin OVON OVOFF PWRGD The resistors connected from TB, TC, and TD to VEE pin determines the delay times between the PWRGD flags. SET RESET Start-up Timing (PS11 PWRGD-A Active Low) The value of the resistors determines the capacitor charging and discharging current of a triangular wave oscillator. The oscillator output is fed into an 8-bit counter to generate the desired time delay. The respective time delay is defined by the following equation: tTX = (255 x 2 x COSC x VPP)/ICD and ICD = Vbg / (4 x RTX) Where tTX = Time delay between respective PWRGD flags COSC = 120pF (internal oscillator capacitor) VPP = 8.2V (peak-to-peak voltage swing of oscillator) ICD = Charge and discharge current of oscillator Vbg = 1.17V (internal band gap reference) RTX = Programming resistor at TB, TC, or TD Combining the two equations and solving for RTX yields: RTX = (Vbg x tTX) / (2040 x COSC x VPP) 6 = 0.585 x 10 x tTX tPWRGD-A is the time delay from VEEUV(on) to PWRGD-A going active. It can be approximated by For a time delay of 200ms RTX tPWRGD-A = CRAMP x (VINT-1.17)/IRAMP where = 0.585 x 106 x 0.2 = 117k For a time delay of 5ms RTX = 0.585 x 106 x 0.005 = 2.925k CRAMP = capacitor connected from RAMP pin to VEE pin VINT = internal regulated power supply voltage (10V typ) IRAMP = 10µA charge current 6 A051204 PS10/PS11 The following waveforms demonstrate the sequencing of the PWRGD flags: PWRGD Timing (Maximum Delays) Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 118k, RTC = 118k, RTD = 118k, RPULL-UP = 47k. PWRGD Timing (PS11) Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 118k, RTC = 59k, and RTD = 46.4k. Relative to Negative Rail PS11 Power Down Sequence after UVOFF Relative to Negative Rail Test conditions: CRAMP = 10nF, RTB = 3.24k, RTC = 3.24k, RTD = 3.24k, RPULL-UP = 47k, CPWRGD_B = 0.47µF, CPWRGD_C = 0.94µF, CPWRGD_D = 1.41µF, VUVOFF = 33.4V, the assumed brick turn-off threshold is 2.7V min TTL logic high. See power down sequencing on Page 11. PWRGD Timing (Minimum Delays) Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 3.24k, RTC = 3.24k, RTD = 3.24k, RPULL-UP = 47k. Relative to Negative Rail Relative to Negative Rail 7 A051204 PS10/PS11 PS11 Power Down Sequence after OVOFF Test conditions: CRAMP = 10nF, RTB = 3.24k, RTC = 3.24k, RTD = 3.24k, RPULL-UP= 47k, CPWRGD_B = 0.47µF, CPWRGD_C = 0.94µF, CPWRGD_D = 1.41µF, VOVOFF = 61.6V, the assumed brick turn-off threshold is 2.7V min TTL logic high. See power down sequencing on Page 11. Relative to Negative Rail PWRGD Output Configuration The PS10 and PS11 open drain power good outputs can be connected directly to the Enable pins of the DC/DC converter. The internal pull-up and clamp of the DC/DC converter sets the logic High Enable/Disable voltage. GND 487K V IN V+ PWRGD-D UV DC/DC Converter PWRGD-C 6.81K 9.76K EN PWRGD-A OV VEE +3.3V PWRGD-B PS10 COM TB RTB TC RTC TD RTD V- Ramp 10nF -48V Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. 8 A051204 PS10/PS11 PWRGD Output Configuration, continued GND 487K V IN V+ PWRGD-D UV DC/DC Converter PWRGD-C 6.81K V EE /EN PWRGD-A OV 9.76K +3.3V PWRGD-B PS11 COM TB TC RTB RTC TD V- Ramp 10nF RTD -48V Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active Low Enabled Converters. Opto-isolated Enable Some applications require opto-isolator interface to the Enable pin of the DC/DC converter. Make sure that the current transfer ratio of the opto-coupler selected is at least 100% to ensure proper pull-down current on the Enable pin. GND 487K VIN V+ PWRGD-D UV 49.9k DC/DC Converter PWRGD-C 6.81K PWRGD-B PS10 Opto-coupler PWRGD-A +3.3V EN OV 9.76K V EE COM TC TB RTB RTC TD RTD V- Ramp 10nF -48V Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. 9 A051204 PS10/PS11 Opto-isolated Enable, continued GND 487K VIN PWRGD-D UV 49.9k V+ DC/DC Converter PWRGD-C 6.81K PWRGD-B PS11 PWRGD-A OV VEE 9.76K Opto-coupler +3.3V /EN COM TB RTB TC RTC TD V- Ramp 10nF RTD -48V Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active Low Enabled Converters. Increasing the Under and Over Voltage Hysteresis If the internal UV hysteresis is insufficient for a particular system application, then it may be increased by using separate resistor dividers for UV and OV and providing a resistor feedback from UV pin to the PWRGD pin. GND 487k 499k VIN PWRGD-D UV V+ DC/DC Converter PWRGD-C +3.3V PWRGD-B PS10 Ruvhys PWRGD-A EN OV VEE 16.5k COM TB TC TD V- Ramp 9.76k RTB RTC RTD 10nF -48V Note: 1. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. 2. Over voltage shut down set to 63.6V Ruvhys can be calculated based on higher UV On voltage (say 42V): Ruvhys = (Vuvon - Vdiode - Vpwrgdlow)/((Vin-Vuvon)/487k Vuvon/16.5k) = (1.22-0.65-0.4)/((42-1.22)/487k - 1.22/16.5k) = 17.35k 10 A051204 PS10/PS11 Increasing the Under and Over Voltage Hysteresis, continued GND 499k 487k VIN V+ PWRGD-D DC/DC Converter PWRGD-C UV +3.3V PWRGD-B PS11 /EN PWRGD-A OV COM Ruvhys 16.5k VEE TB TD TC V- Ramp 10k 9.76k RTB RTC 10nF RTD -48V Note: 1. Other power good outputs will have the same configuration as PWGRGD-A for Active Low Enabled Converters. 2. Over voltage shut down set to 63.6V Ruvhys can be calculated based on higher UV On voltage (say 42V): Ruvhys = (Vuvon - Vdiode - Vce/((Vin-Vuvon)/487k Vuvon/16.5k) = (1.22-0.65-0.1)/((42-1.22)/487k - 1.22/16.5k) = 47.97k Power Down Sequencing In some applications, a power down sequence may be required. To accomplish this, a capacitor is connected to the power good pins that need to be sequenced down. The power good turn off delays can be approximated by TPWRGD-B(off) = C1 x VENOFF / IPULLUP , TPWRGD-C(off) = C2 x VENOFF / IPULLUP , TPWRGD-D(off) = C3 x VENOFF / IPULLUP , where: TPWRGD-B(off) -Time delay from PWRGD-A going High to PWRGD-B going high. TPWRGD-c(off) -Time delay from PWRGD-A going High to PWRGD-C going high. TPWRGD-D(off) -Time delay from PWRGD-A going High to PWRGD-D going high. VENOFF - DC/DC minimum off voltage (2.7V typ) IPULLUP - DC/DC /EN pin pull-up current (1mA typ) Note: Adding C1, C2, C3 will have a negligible affect on the power good fall time. GND 487K V IN V+ /EN4 DC/DC Converter PWRGD-D UV /EN3 PWRGD-C 6.81K /EN2 PWRGD-B PS11 +3.3V /EN PWRGD-A OV COM 9.76K VEE TB RTB TD TC RTC RTD V- Ramp 10nF C3 C2 C1 -48V Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Only PWRGD-A to DC/DC converter connection is shown for simplicity. 11 A051204 PS10/PS11 PS10 Power Good Clamp If the active high enabled dc/dc converter used does not have an internal clamp, an external zener diode may be used to protect the module. GND 487K VIN V+ PWRGD-D UV PWRGD-C 6.81K DC/DC Converter 49.9k PWRGD-B PS10 +3.3V EN PWRGD-A OV 9.76K COM VEE TB RTB TC RTC TD V- Ramp 10nF RTD -48V Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. Typical Application Circuit for a 12V Non-Isolated System Most FPGAs, Processors, ASICs, and DSPs require sequencing and rail voltage limitation during start-up and power down sequence of its rails. A typical requirement is: VDD_CORE must not exceed VDD_IO more than 0.6V and VDD_IO must not exceed VIN at any time. This can be accomplished by sequencing the dc/dc converters by the following manner: Turn On: VDD_CORE first, VDD_IO second, and VIN last. Tun-Off: VIN first, VDD_IO second, and VDD_CORE last. The Schottky diodes will limit the voltage between the rails to around 0.3V @ 3A during the power-up and power-down sequence. Assuming that the /EN pins of the dc/dc converters have no pull-up and have a 1.0V turn-off threshold, the power-down sequence time delays can be approximated by: TPWRGD-C to TPWRGD-B = 1µF x 1V / 1mA = 1ms TPWRGD-B to TPWRGD-A = (2µF-1µF) x 1V / 1mA = 1ms +12V R9 R8 14 R1 VIN 6 1 PWRGD-D UV PWRGD-C R2 PWRGD-B 5 R3 7 VEE /EN 2 Buck Converter 3 +5V TC 11 TD 12 13 /EN +3.3V RTC RTD VDD_IO 30BQ015 Ramp /EN 10 Buck Converter RTB LOAD 4 Buck Converter TB VIN 30BQ015 PWRGD-A PS11 OV 12k 12k 10nF VDD_CORE GND +2.5V C1 C2 2uF 1uF GND Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 2004 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. A051204 Doc. #: DSFP-PS10PS11 12 A051204 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 / FAX: (408) 222-4895 www.supertex.com Package Outlines 14-LEAD SO PACKAGE (NG) (NARROW BODY) 0.340 ± 0.005 (8.636 ± 0.127) D 0.017 ± 0.003 (0.4318 ± 0.0762) B E H 0.156 ± 0.002 (3.9624 ± 0.0508) 0.500 T Y P. (12.700) 0.2335 ± 0.0105 (5.9309 ± 0.2667) 0.193 ± 0.012 (4.9022 ± 0.3048) 0.350 T Y P. (8.890) D1 h 0.006 ± 0.002 (0.1524 ± 0.0508) A 7° (4 P LC S ) 45° L1 A1 C 0° - 8 ° e 0.063 ± 0.005 (1.600 ± 0.127) 0.020 ± 0.009 (0.508 ± 0.2286) 0.050 T Y P. (1.270) Note: C ircle (e.g. B ) indicates J E DE C R eference. Doc. #: DSPD14SONG ©2004 S upertex Inc. All rights res erved. Unauthorized us e or reproduction prohibited. L 0.006 ± 0.004 (0.1524 ± 0.1016) 0.035 ± 0.015 (0.889 ± 0.381) Meas urement Legend = 0.0275 ± 0.0025 (0.6985 ± 0.0635) Dimens ions in Inches (Dimens ions in Millimeters ) A050604 1235 B ordeaux Drive, S unnyvale, C A 94089 T E L: (408) 222-8888 / F AX : (408) 222-4895 www.s upertex.com