LTC4226 Wide Operating Range Dual Hot Swap Controller Features Description Allows Safe Board Insertion into Live Backplane n Selectable Current Limit and Dual-Rate Timer Accommodate Load Surges n Fast Response Limits Peak Fault Current n Wide Operating Voltage Range: 4.5V to 44V n Optional Auto-Retry or Latchoff after Overcurrent Fault n High Side Drive for External N-Channel MOSFET n Allows Parallel Power Paths for High Current Applications n Available in 16-Pin QFN (3mm × 3mm) and MSOP Packages The LTC®4226 dual Hot Swap™ controller allows two power paths to be safely inserted and removed from a live backplane or powered connector. Using N-channel pass transistors, supply voltages ranging from 4.5V to 44V are ramped up at an adjustable rate. Applications The LTC4226 can also be configured as a bidirectional current limiter/circuit breaker. For high current applications, two channels may be configured as parallel power paths. n n n n n n Three selectable ratios of current limit to circuit breaker threshold accommodate noisy loads and momentary high peak currents without interruption, while a dual-rate fault timer protects the MOSFET from extended output overcurrent events. FAULT outputs indicate the circuit breaker status. The LTC4226-1 remains off after a fault while the LTC4226-2 automatically retries after a 0.5s delay. Apple FireWire/IEEE 1394 Disk Drives Rugged 12V, 24V Applications Hot Board/Connector Insertion Uni/Bidirectional Current Limiter/Circuit Breaker L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application 2 Port FireWire Application SS3P5 30mΩ PORT 1 1394 1394 SOCKET PLUG FDMS86500DC 7V TO 33V VCC1 SENSE1 GATE1 ON1 CURRENT LIMIT SELECT VCC 10V/DIV OUT1 CABLE INSERTION FTMR1 VOUT 10V/DIV 220nF FAULT1 LTC4226-2 CLS GND FAULT2 220nF ON2 FTMR2 VCC2 SMCJ33A* Inrush after Load Connection SENSE2 GATE2 30mΩ *36.7V TO 40.6V BV OUT2 PORT 2 1394 1394 SOCKET PLUG FDMS86500DC 4226 TA01a IOUT 1A/DIV INRUSH CURRENT VCC = 12V CLOAD = 1mF 1ms/DIV 4226 TA01b 4226f 1 LTC4226 Absolute Maximum Ratings (Notes 1, 2) VCCn............................................................ –0.3V to 55V SENSEn, ONn, FAULTn, CLS........................ –0.3V to 55V GATEn (Note 3)........................................... –0.3V to 68V OUTn (Note 3)............................................. –0.3V to 55V GATEn – OUTn (Note 3).............................. –0.3V to 18V FTMRn.......................................................... –0.3V to 4V Operating Ambient Temperature Range LTC4226C................................................. 0°C to 70°C LTC4226I..............................................–40°C to 85°C Storage Temperature Range................... –65°C to 150°C MSOP Lead Temperature (Soldering, 10 sec)......... 300°C Pin Configuration ON2 FAULT2 FAULT1 ON1 TOP VIEW TOP VIEW 16 15 14 13 2 GATE1 3 OUT1 4 11 SENSE2 17 10 GATE2 9 FTMR1 5 6 7 OUT2 8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FAULT2 ON2 VCC2 SENSE2 GATE2 OUT2 FTMR2 CLS MS PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/W FTMR2 SENSE1 12 VCC2 CLS 1 GND VCC1 FAULT1 ON1 VCC1 SENSE1 GATE1 OUT1 FTMR1 GND UD PACKAGE 16-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 68°C/W EXPOSED PAD (PIN 17), PCB GND CONNECTION OPTIONAL Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4226CUD-1#PBF LTC4226CUD-1#TRPBF LFRC 16-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C LTC4226CUD-2#PBF LTC4226CUD-2#TRPBF LFRD 16-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C LTC4226IUD-1#PBF LTC4226IUD-1#TRPBF LFRC 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC4226IUD-2#PBF LTC4226IUD-2#TRPBF LFRD 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC4226CMS-1#PBF LTC4226CMS-1#TRPBF 42261 16-Lead Plastic MSOP 0°C to 70°C LTC4226CMS-2#PBF LTC4226CMS-2#TRPBF 42262 16-Lead Plastic MSOP 0°C to 70°C LTC4226IMS-1#PBF LTC4226IMS-1#TRPBF 42261 16-Lead Plastic MSOP –40°C to 85°C LTC4226IMS-2#PBF LTC4226IMS-2#TRPBF 42262 16-Lead Plastic MSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4226f 2 LTC4226 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VCC = 12V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VCCn Input Supply Range ICCn Input Supply Current VCC = 12V l VCCn(UVL) Input Supply Undervoltage Lockout VCC Rising l l 4.5 3 ∆VCCn(HYST) Input Supply Undervoltage Lockout Hysteresis 44 V 0.7 2 mA 3.7 4.5 200 V mV Circuit Breaker and Current Limit VCB Circuit Breaker Threshold (VCC – SENSE) VLIMIT Current Limit Voltage ISENSE Sense Pin Input Current (VCC – SENSE = 0V) l ∆VGATE External N-Channel Gate Drive (GATE – OUT) IGATE = 0µA, –1µA; VCC > 6V IGATE = 0µA, –1µA; VCC < 6V l l IGATE(UP) Gate Pull-Up Current GATE = OUT = 1V IGATE(DN) Gate Pull-Down Current GATE = 12V, OUT = 0V, ON = 0V GATE = OUT = VCC = 12V, ON = 0V or FAULT = 0V GATE = 5V, OUT = 0V, ON = 3V, Severe Fault VON Rising Channel-to-Channel VCB Mismatch 45 50 55 ±6 % 70 93 139 86 115 173 103 136 205 mV mV mV ±6 % 40 200 µA 10 8 12 12 16 16 V V l –5 –9 –13 µA l l l 1 50 100 3 150 200 5 300 1000 mA µA mA l 1.17 1.24 1.3 l l (VCC – SENSE), CLS = 0V (VCC – SENSE), CLS = Open (VCC – SENSE), CLS = 3V Channel-to-Channel VLIMIT Mismatch l l l l mV Gate Drive Comparator Inputs VON ON Pin Threshold Voltage ∆VON(HYST) ON Pin Hysteresis Voltage 50 ON Pin Input Current VON = 1.2V l IFTMR(CB) FTMR Pin Pull-Up Current (Circuit Breaker) VFTMR = 0V, Circuit Breaker Fault l IFTMR(CL) FTMR Pin Pull-Up Current (Current Limit) VFTMR = 0V, Current Limit Engaged, CLS = 0V VFTMR = 0V, Current Limit Engaged, CLS = Open VFTMR = 0V, Current Limit Engaged, CLS = 3V IFTMR(DEF) FTMR Pin Pull-Down Current (Default) IFTMR(RST) FTMR Pin Pull-Down Current (Reset) VFTMR(H) VFTMR(L) ION V mV 0 ±1 µA –1.4 –2 –2.6 µA l l l –14 –25 –56 –20 –36 –80 –26 –46 –104 µA µA µA VFTMR = 1V, Default l 1.4 2 2.6 µA VFTMR = 1V, Reset l 70 100 130 µA FTMR Pin Threshold Voltage (Trip) l 1.17 1.23 1.3 V FTMR Pin Threshold Voltage (Reset) l 0.1 0.2 V 0.2 0.4 V 5 10 mA Fault Timer Fault I/O V(OL) FAULT Pin Low Output Voltage Circuit Breaker Fault, IFAULT = 2mA l I(OL) FAULT Pin Low Output Pull-Down Current Circuit Breaker Fault, VFAULT = 5V, VCC = 12V l 2 VFAULT FAULT Pin Input Threshold Voltage No Internal Fault, External Input l 0.3 0.5 0.8 V I(OH) FAULT Pin Pull-Up Current No Internal Fault, VFAULT = 2V l –5 –10 –20 µA V(OH) FAULT Pin High Output Voltage No Internal Fault, IFAULT = 0µA, VCC = 12V l 2 3.8 5 V 4226f 3 LTC4226 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VCC = 12V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Three-State Input VCLS(L) CLS Pin Low Threshold Voltage l l VCLS(H) CLS Pin High Threshold Voltage VCLS(Z) CLS Pin Voltage in Open State 0.4 2 V V 1.38 V ICLS(Z) Allowable CLS Pin Leakage in Open State l ±2 µA ICLS(L) CLS Pin Low Input Current l –2 –4 –8 µA ICLS(H) CLS Pin High Input Current l 2 4 8 µA 0.1 1 µs Timing Delay tOFF(SENSE) Severe Overcurrent Fault to GATE Low CGATE = 1nF, (VCC – SENSE = 4V) l tOFF(FAULT) FAULT Input Low to GATE Low CGATE = 1nF l 3 6 30 µs tOFF(FMTR) FTMR High to GATE Low CGATE = 1nF l 3 7 30 µs tOFF(ON) ON Low to GATE Low CGATE = 1nF l 25 60 µs tOFF(UVLO) VCC Enters Undervoltage to GATE Low CGATE = 1nF l tON(ON) ON High to GATE High VCC Above Undervoltage l Channel-to-Channel tON(ON) Mismatch tON(UVL) VCC Exits Undervoltage to GATE High Auto-Retry Delay 25 60 µs 10 20 ms ±10 % 100 ms ±10 % 1 s l ON High Channel-to-Channel tON(UVL) Mismatch tD(COOL) 5 l 25 50 l LTC4226-2 Only Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. l 0.25 0.5 Note 3: Limits on maximum rating is defined as whichever limit occurs first. Internal clamps limit the GATE pin to a minimum of 12V above OUT, a diode voltage drop below OUT, or a diode voltage drop below GND. Driving the GATE to OUT pin voltage beyond the clamp may damage the device. 4226f 4 LTC4226 Typical Performance Characteristics Circuit Breaker Voltage vs Supply Voltage Supply Current vs Supply Voltage VCB (mV) 400 55.0 55 52.5 50 45 200 0 60 0 10 20 30 VCC (V) 40 40 50 47.5 0 10 4226 G01 Current Limit Voltage vs Supply Voltage 45.0 –50 50 VLIMIT (mV) VLIMIT (mV) 0 10 20 30 VCC (V) 40 CLS = OPEN CLS = 0V 50 –50 50 –25 0 25 50 TEMPERATURE (°C) 75 4226 G04 100 0.01 5 4226 G07 600 ∆VGATE (V) 10 ∆VGATE (V) 10 100 100 200 300 400 500 SENSE VOLTAGE (VIN – VSENSE) (mV) Gate Voltage vs Supply Voltage –10 75 0 4226 G06 15 0 25 50 TEMPERATURE (°C) CLS = OPEN 0.1 15 –25 CLS = 0V 1 –15 0 –50 CLS = 3V 10 Gate Voltage vs Gate Pull-Up Current –5 100 CGATE = 1nF 4226 G05 Gate Pull-Up Current vs Temperature 75 4226 G03 100 100 CLS = 0V 0 25 50 TEMPERATURE (°C) Active Current Limit Delay vs Sense Voltage 150 CLS = OPEN –25 4226 G02 CLS = 3V 150 IGATE(UP) (µA) 40 200 CLS = 3V 50 20 30 VCC (V) Current Limit Voltage vs Temperature 200 100 50.0 ACTIVE CURRENT LIMIT DELAY (µs) ICC (µA) 800 Circuit Breaker Voltage vs Temperature VCB (mV) 1000 600 TA = 25°C, VCC = 12V, unless otherwise noted. 0 5 0 –5 –10 IGATE(UP) (µA) –15 4226 G08 0 0 10 20 30 VCC (V) 40 50 4226 G09 4226f 5 LTC4226 Typical Performance Characteristics Gate Voltage vs Gate Pull-Down Current Gate Voltage vs Severe Fault Gate Pull-Down Current ON = 0V 15 10 10 ∆VGATE (V) ∆VGATE (V) 10 5 5 0 1 2 3 IGATE(DN) (mA) 4 0 5 0 100 4226 G10 Circuit Breaker Timer Current vs Temperature 200 300 IGATE(DN) (mA) 400 0 –50 500 IFTMR(CL) (µA) –2.0 –1.8 75 100 Fault Output Low Voltage vs Current 5 –90 –2.2 0 25 50 TEMPERATURE (°C) 4226 G12 –110 –2.4 –25 4226 G11 Current Limit Timer Current vs Temperature –2.6 IFTMR(CB) (µA) 5 4 CLS = 3V –70 VOL (V) 0 –50 3 2 CLS = OPEN –30 –1.6 –1.4 –50 –25 0 25 50 TEMPERATURE (°C) 75 –10 –50 100 1 CLS = 0V –25 0 25 50 TEMPERATURE (°C) 75 4226 G13 Supply Undervoltage Lockout vs Temperature 0.7 3.8 0.6 3.6 0.5 0.4 0 25 50 TEMPERATURE (°C) 75 100 4226 G16 2 8 10 4226 G15 13 VCC(UVL) VCC(UVL) – ∆VCC(HYST) 3.4 3.0 –50 4 6 IOL (mA) ON Turn-On Time vs Temperature 3.2 –25 0 15 tON(ON) (ms) 4.0 VCC(UVL) (V) 0.8 0.3 –50 0 100 4226 G14 Fault Input Threshold Voltage vs Temperature VFAULT (V) Gate Voltage vs Temperature 15 ∆VGATE (V) 15 TA = 25°C, VCC = 12V, unless otherwise noted. 11 9 7 –25 0 25 50 TEMPERATURE (°C) 75 100 4226 G17 5 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4226 G18 4226f 6 LTC4226 Pin Functions CLS: Three-State Current Limit Select Input. Tying this pin low enables 1.5× current limit; opening this pin enables 2× current limit and tying this pin high (above 2V) enables 3× current limit. A higher current limit selection permits larger current transients to pass without invoking current limiting. The CLS pin permits dynamic current limit selection. The three input states configure the preset current limit voltage VLIMIT to approximately 1.5×, 2× or 3× of 1.15 • VCB. Exposed Pad: The exposed pad may be left open or connected to device ground. FAULT1, FAULT2: FAULT Input/Output Status. When the FTMR pin has reached the VFTMR(H) threshold, the fault status is set active and the FAULT pin output pulls low. When fault is inactive, a 10µA current source pulls this pin up to a diode below its internal supply voltage. Pulling the FAULT pin low turns off the external MOSFET without affecting the FTMR pin status. The FAULT pin is not latched. FTMR1, FTMR2: Fault Timer. A capacitor sets the dualrate fault timer durations: circuit breaker CB timeout and current limit CL timeout. The FTMR pin pulls up with IFTMR(CB) when the sense resistor voltage is between VCB and VLIMIT. The FTMR pin pulls up with IFTMR(CL) when the sense resistor voltage is at or above VLIMIT. FTMR pulls low with IFTMR(DEF) when the sense resistor voltage falls below VCB. When the FTMR voltage reaches the VFTMR(H) threshold, the fault status is activated. To reset FTMR, the ON pin can be pulled low or the corresponding supply voltage can be pulled below the undervoltage lockout threshold. The capacitor on the FTMR pin is pulled to GND with IFTMR(RST) to clear the fault status. For the LTC4226-1 latchoff option, the MOSFET remains off until faults are cleared by cycling the ON pin or by an undervoltage condition on the corresponding supply. For the LTC4226-2 auto-retry option, after a tD(COOL) delay, FTMR is reset, the fault status is cleared, and the GATE begins to ramp up. The LTC4226-2 can be forced to restart by cycling the ON pin or by an undervoltage condition on the corresponding supply. GATE1, GATE2: Gate Drive for External MOSFET. The gate driver controls the external N-channel MOSFET switch by applying a voltage across the GATE and OUT pins which connect to the MOSFET gate and source pins. A charge pump sources 9µA at the GATE pin to turn on the external MOSFET. When the MOSFET is on, the GATE pin voltage is clamped at ∆VGATE above the OUT pin. During turn-off, the GATE pin is discharged by a 3mA pull-down with about 2.85mA of current flowing to the OUT pin. In a severe fault, the GATE pin is discharged to the OUT pin with a minimum of 100mA. When the MOSFET is off, the GATE pin is pulled towards ground with 150µA and a voltage clamps limits the GATE voltage to a diode drop below the OUT pin. GND: Device ground ON1, ON2: ON Control Inputs. The ON pins have a 1.23V threshold with 50mV of hysteresis. A high input turns on the external MOSFET with a 10ms delay. A low input turns off the external MOSFET and resets circuit breaker faults. OUT1, OUT2: Gate Drive Return. Connect this pin to the source of the external N-channel MOSFET switch. This pin provides a return for the gate pull-down circuit. When the GATE pin is below the OUT pin, the internal clamp diode draws current from this OUT pin. SENSE1, SENSE2: Current Sense Negative Input. The circuit breaker comparator and the current limit amplifier monitor the voltage across the sense resistor. The current limiting amplifier controls the GATE of the external MOSFET to keep the sense resistor voltage at VLIMIT. The current limit is set higher than the circuit breaker to accommodate noisy loads that momentarily exceed the circuit breaker comparator threshold. VCC1, VCC2: Supply Voltage and Current Sense Positive Input. An undervoltage lockout circuit disables the MOSFET switch until VCC is above the lockout voltage VCC(UVL) for 50ms. 4226f 7 LTC4226 Functional Block Diagram VCC1 SENSE1 UVLO VCB ON1 + – CB CHARGE PUMP + – + ON VREF VLIMIT – + + – CL 9µA – GATE1 12V OUT1 IFTMR(CB) IFTMR(CL) 10µA FTMR1 CB CL FAULT1 + DEF FTMR(H) RST VREF IFTMR(DEF) LOGIC – IFTMR(RST) + CHANNEL 1 FTMR(L) 0.1V – CLS GND IFTMR(CB) IFTMR(CL) 10µA CHANNEL 2 FTMR2 CB CL FAULT2 + DEF FTMR(H) RST VREF IFTMR(DEF) LOGIC – IFTMR(RST) + FTMR(L) 0.1V ON2 CHARGE PUMP – + 9µA GATE2 ON VREF – 12V OUT2 CB + – + – VLIMIT + – + – VCB CL UVLO VCC2 SENSE2 4226 BD 4226f 8 LTC4226 Operation The LTC4226 controls two independent Hot Swap channels. It is designed to turn each supply voltage on and off in a controlled manner, allowing live insertion into a powered connector or backplane. The LTC4226 powers-up the output of a channel when that channel’s VCC pin has remained above the 3.7V undervoltage lockout threshold VCC(UVL) for more than 50ms and its ON pin has remained above the VON threshold for more than 10ms. During normal operation, a charge pump turns on the external N-channel MOSFET providing power to the load. Each channel’s charge pump derives its power from its own VCC supply pin. To protect the MOSFET, the GATE voltage is clamped at about 12V above the OUT pin. It is also clamped a diode voltage below the OUT pin and a diode voltage below GND. The current flowing through the MOSFET is measured by the external sense resistor. The sense voltage across the sense resistor is measured between the VCC and SENSE pins. The LTC4226 has a circuit breaker (CB) comparator to detect the sense current above circuit breaker threshold and a current limit (CL) amplifier to actively clamp the sense current at the current limit threshold. Both the CB comparator and the CL amplifier monitor the sense resistor voltage between the VCC and SENSE pins. When the sense voltage exceeds VCB but is below VLIMIT, the CB comparator enables a 2μA IFTMR(CB) current source that ramps up the voltage on the FTMR pin. If the sense resistor voltage exceeds VLIMIT, the CL amplifier limits the current in the MOSFET by reducing the GATE-to-OUT voltage with an active control loop. The fast response CL amplifier can quickly gain control of the GATE-to-OUT voltage in the event of an OUT-to-GND short circuit. The FTMR pin is ramped up by the larger IFTMR(CL) current source during active current limiting. If the sense voltage falls below VCB, the FTMR is ramped down by the default 2μA IFTMR(DEF) pull-down current. A fault timeout occurs when an overcurrent condition persists above VCB that causes the FTMR pin to ramp to the VFTMR(H) threshold. When this occurs, the MOSFET is turned off and the FAULT pin asserts low. The FTMR has two timeout durations: a longer circuit breaker (CB) timeout with a lower current IFTMR(CB) ramp up when the current limit is not activated and a shorter current limit (CL) timeout with a higher current IFTMR(CL) ramp up if current limit is active. The CLS input state sets the higher current IFTMR(CL) at 20μA when CLS = 0V; 36μA when CLS = open; 80μA when CLS > 2V. During current limit, the sense voltage is at VLIMIT. There can be significant MOSFET power dissipation while in current limit due to the substantial drain-to-source voltage. The CL timeout duration should be selected based on the external MOSFET safe-operating-area to prevent MOSFET damage. The CL timeout is set by the FTMR capacitor CT and the IFTMR(CL) pull-up to the VFTMR(H) threshold. Setting the current limit higher than the circuit breaker threshold allows momentary current load spikes as long as the average current remains below the circuit breaker limit. Both channels share a common current limit select, CLS pin. This pin has three input states: low, open and high. The three input states configure the preset current limit VLIMIT to approximately 1.5×, 2× or 3× of 1.15 • VCB. After a fault timeout, the auto-retry (LTC4266-2) version waits 0.5 seconds before resetting FTMR. After the FTMR capacitor is discharged, the GATE pin is free to ramp up again after the FAULT pin resets high. For the latchoff (LTC4266-1) version, there is no 0.5 second restart delay. For both versions, FTMR can be reset by cycling the ON pin low and then high or by cycling VCC below and then above UVLO. The FAULT pin pulls low when active with a 5mA current limit. The pin can drive a low-current 2mA LED with a series resistor connected to VCC. The FAULT pin has an internal 10μA pull-up current to a diode below its internal VCC when signaling no fault. Pulling the FAULT pin below the VFAULT threshold causes the external MOSFET to turn off without affecting FTMR status. The FAULT pin can be wire-OR’ed with other open-drain outputs. The output voltage of the Hot Swap circuit is ramped down when the ON pin transitions low or VCC falls below the 3.7V undervoltage lockout. The gate driver discharges the GATE pin with 3mA (including 2.85mA to the OUT pin) when GATE > OUT and 150µA to GND when GATE < OUT. 4226f 9 LTC4226 Applications Information The typical LTC4226 application is in high availability systems that distribute positive voltage supplies between 4.5V to 44V to hot-swappable ports or cards. It can also be used in daisy chain port applications like FireWire to provide instant current limit. At start-up, the switch current is typically dominated by the current charging the load capacitor, CL1. If the sense voltage reaches VLIMIT, the current limit amplifier controls the gate of the MOSFET in a closed loop. This keeps the start-up inrush current at the current limit. The basic two channel applications are shown in Figure 1 and Figure 2. Figure 1 shows the LTC4226 in a card resident application with an upstream connector. Figure 2 shows the LTC4226 on a backplane or motherboard with a downstream connector. Each Hot Swap channel has a power path controlled by an external MOSFET switch and a sense resistor for monitoring current. Several conditions must be present before the external MOSFET can be turned on. The fault timer FTMR is reset by either UVLO or ON low status. The external supply VCC must exceed its undervoltage lockout level VCC(UVL) for more than 50ms. The ON pin must be high for more than 10ms and the FAULT pin must be high before the external MOSFET turns on with no additional delay. Turn-On Sequence During turn-on, a 9µA current charges the gate of the MOSFET switch: Q1 for channel 1. The current limit amplifier monitors the current in the channel 1 power path by sensing the voltage across the resistor, RS1. If the channel is not in UVLO, the ON pin low to high assertion delay is 10ms. The FAULT pin must be high before the external switch turns on. When the channel is not in UVLO and the ON pin is high, there is no delay from the FAULT low to high transition to turn on of the external switch. CONNECTOR CONNECTOR 2 1 RS1 5mΩ 12V R1 720k ON1 GND R2 100k C1 470pF R6 1k FAULT1 CLS C3 22nF FTMR1 LTC4226-1 CLS R3 240k R4 100k PLUG-IN CARD GND CT2 33nF FTMR2 ON2 OUT2 C2 470pF 5V BACKPLANE CT1 33nF FAULT2 SENSE2 GATE2 CL1 100µF 12V 8.9A OUT OUT1 FAULT1 VCC2 ON2 SENSE1 GATE1 ON1 R5 10k FAULT2 + Z1 SMCJ15A VCC1 R7 1k Q1 FDMS86500DC OR Si7164DP Z2 SMCJ7V0A RS2 10mΩ Q2 FDMS86500DC OR Si7164DP + CL2 220µF 5V 4.45A OUT 4226 F01 Figure 1. 2-Channel Card Resident Controller with Upstream Connector 4226f 10 LTC4226 Applications Information CONNECTOR CONNECTOR 1 2 C1 470pF R2 100k R1 720k RS1 5mΩ 12V Q1 FDMS86500DC OR Si7164DP 12V 8.9A OUT Z1 SMCJ15A SENSE1 GATE1 ON1 ON1 FTMR1 FAULT1 FAULT1 LTC4226-1 CLS CLS ON2 ON2 FTMR2 VCC2 5V C2 470pF GND FAULT2 FAULT2 Z2 SMCJ7V0A R4 100k SENSE2 GATE2 RS2 10mΩ R2 240k + OUT1 CL1 100µF CT1 33nF GND CT2 33nF OUT2 + VCC1 CL2 220µF 5V 4.45A OUT Q2 FDMS86500DC OR Si7164DP 4226 F02 MOTHERBOARD OR BACKPLANE PLUG-IN CARD Figure 2. 2-Channel Backplane Resident Controller with Downstream Connector CONNECTOR CONNECTOR 1 2 R1 720k 12V RS1 5mΩ Q1 FDMS86500DC OR Si7164DP 12V 8.9A OUT Z1 SMCJ15A SENSE1 GATE1 ON1 FTMR1 FAULT1 CLS LTC4226-1 CLS FAULT GND FAULT2 ON2 ON2 C1 470pF R2 100k FTMR2 VCC2 5V Z2 SMCJ7V0A SENSE2 GATE2 RS2 10mΩ + OUT1 CT1 33nF GND CT2 33nF OUT2 Q2 FDMS86500DC OR Si7164DP CL1 100µF + VCC1 CL2 220µF 5V 4.45A OUT MOTHERBOARD PLUG-IN CARD 4226 F03 Figure 3. 2-Channel Controller with a Common ON/OFF Connection 4226f 11 LTC4226 Applications Information + C1 100µF CONNECTOR CONNECTOR 1 2 Q1 FDMS86500DC OR Si7164DP RG1 10Ω Z1 SMCJ15A VCC1 SENSE1 GATE1 ON1 FTMR1 FAULT ON2 LTC4226-1 CLS FTMR2 SENSE2 GATE2 GND CT2 33nF FAULT2 VCC2 RG2 10Ω OUT2 CG1 10nF 5V + C2 220µF Z2 SMCJ7V0A RS2 10mΩ Q2 FDMS86500DC OR Si7164DP CL1 100µF CT1 33nF GND ON2 + CG1 10nF OUT1 FAULT1 CLS 12V 8.9A OUT + 12V RS1 5mΩ CL2 220µF 5V 4.45A OUT MOTHERBOARD CONNECTOR PLUG-IN CARD OR CONNECTOR 4226 F04 Figure 4. 2-Channel Controller with Inrush Current Control but without Connector Enable Turn-Off Sequence The MOSFET switch can be turned off by a variety of conditions. A normal turn-off is initiated by the ON pin going low. Additionally, a circuit breaker/current limit timeout will cause the MOSFET to turn off, as will VCC dropping below its undervoltage lockout potential VCC(UVL). Alternatively, the FAULT pin can be externally pulled low to force the gate shutdown. Under any of these conditions, the MOSFET is turned off with a 3mA current pulling down from GATE. About 2.85mA of that current flows from GATE to OUT and the remainder flows to GND. When the GATE voltage is below the OUT pin, the GATE is pulled towards GND by a 150µA current source. during current limit while preserving the fast pull-down of the gate. The capacitor CG should be sized to limit the inrush current below the circuit breaker trip current. For leaded MOSFET with heatsink, an additional 10Ω resistor (as shown with R1 in Figure 13) can be added close to the MOSFET gate pin to prevent possible parasitic oscillation due to more trace/wire inductance and capacitance. The MOSFET is turned on by a 9µA current source charging up the GATE. When the GATE voltage reaches the MOSFET threshold voltage, the MOSFET turns on and the SOURCE voltage follows the GATE voltage as it increases. The GATE voltage rises with a slope 9µA/CG and the supply inrush current is: Inrush Current Control In most applications, keeping the inrush current at current limit is an acceptable start-up method if it does not trip the fault timer FTMR and the MOSFET has an adequate safe operating margin. To keep the inrush sense resistor voltage below the circuit breaker threshold voltage VCB, a resistor RG and a capacitor CG can be inserted between the GATE pin and ground as shown in Figure 4. The capacitor CG with a grounded terminal and interconnect inductance can lead to parasitic MOSFET oscillations. A resistor RG between 10Ω and 100Ω is typically adequate to prevent parasitic oscillation. RG also allows CG to act as a charge reservoir IINRUSH = CL • 9µA CG (1) Note that the voltage across the MOSFET switch can be large during inrush current control. If the inrush current is below the circuit breaker threshold, the fault timer FTMR is not activated. In some applications like Firewire where a large supply voltage step up transient can occur, the current limit amplifier is momentarily activated and the GATE is partially discharged. Once the switch current falls below the current limit, the GATE will continue to charge up at the supply inrush control rate. 4226f 12 LTC4226 Applications Information Overcurrent Fault The LTC4226 manages overcurrent faults by differentiating between circuit breaker faults and current limit faults. Typical applications have a load capacitor to filter the load current. A large load capacitor is an effective filter, but it can increase MOSFET switch power dissipation at start-up or during step up supply transients. When the MOSFET is fully enhanced and the current is below the current limit, the MOSFET power dissipation is low and is determined by the RDSON and the switch current. If the current is above the circuit breaker threshold but below current limit, the circuit breaker CB comparator activates a IFTMR(CB) pull-up current source at the FTMR pin. When the channel current exceeds the current limit, the CL amplifier activates the gate driver pull-down in a closed loop manner. The excess GATE overdrive voltage is abruptly discharged to the OUT pin until the sense voltage between VCC and SENSE drops below VLIMIT. This brief interval is kept short by the fast responding amplifier to reduce the excessive channel current. Next the CL amplifier servos the GATE pin to maintain the sense voltage at VLIMIT. During this current limit interval, the power dissipation in the MOSFET increases. The worst case switch power dissipation occurs during a load short where the current is set by the current limit with the entire supply voltage appearing across the MOSFET. During active current limiting, the FTMR pin is pulled up with IFTMR(CL). Dual-Rate Fault Timer The fault timer pin FTMR, as illustrated in Figure 5 timing waveforms, has a dual-rate fault pull-up that extends the allowable duration of peak currents that are above the circuit breaker threshold but below the current limit level. When the load current exceeds the current limit threshold, the power dissipation in the MOSFET may be high due to the potentially large drain-to-source voltage. In this condition, the FTMR pull-up current increases to reduce the fault timer duration. When the load current is below the current limit threshold, the power dissipation in the MOSFET is less since the MOSFET is fully enhanced and the drain-to-source voltage is small. Therefore, when the current is below the current limit threshold but above the circuit breaker threshold, the FTMR pull-up current is re- ILIM ICB IOUT MOSFET OFF FTMR VOUT MODEST OVERLOAD IGNORED SEVERE OVERLOAD SHUTS OFF 4226 F05 Figure 5. Dual-Rate Fault Timing duced. The MOSFET will turn off in a fault condition where the average current is above the circuit breaker threshold, but the dual-rate timer extends the allowable duration for peak currents that remain below the current limit level. The FTMR pin has comparators and four current sources connected to an external capacitor CT. The four current sources are: the default pull-down current IFTMR(DEF), the circuit breaker pull-up current source IFTMR(CB), the higher current limit pull-up current source IFTMR(CL) and the reset pull-down current source IFTMR(RST). When the FTMR pin voltage exceeds the VFTMR(H) threshold, the FTMR comparator signals a fault timeout. The FTMR pin is held low in default normal mode whenever the circuit breaker comparator, the current limit amplifier and the reset are all inactive. The default mode has the IFTMR(DEF) pull-down current source activated. When the sense voltage exceeds the circuit breaker threshold VCB but is below VLIMIT, the circuit breaker comparator enables the IFTMR(CB) pull-up current source and disables the IFTMR(DEF) current source. When the sense voltage reaches the VLIMIT threshold, the current limit amplifier activates the higher IFTMR(CL) pull-up current source. When the FTMR pin ramps up to VFTMR(H), the FTMR(H) comparator trips. The FAULT pin is asserted low and the GATE to OUT voltage is discharged to turn off the MOSFET. For the Auto-Retry option, the Auto-Retry internal timing is initiated. The FTMR pin is asserted high at VFTMR(H) until the FTMR(L) comparator is reset low at VFTMR(L) by the IFTMR(RST) pull-down source, which is activated by ON low or UVLO or at the end of the Auto-Retry interval of typically 0.5s. The FAULT pin goes high when the FTMR 4226f 13 LTC4226 Applications Information pin is pulled below VFTMR(L). The GATE to OUT voltage can ramp up for Auto-Retry mode if the ON pin is high and VCC is not in UVLO. When the MOSFET current exceeds the circuit breaker threshold but remains below the current limit the fault time is given by: tCB = CT • 1.23V IFTMR(CB) ( 2) When the current limit is active the fault time is given by: tLIMIT = CT • 1.23V IFTMR(CL) (3) During active current limiting, a large MOSFET drain to source voltage can appear, and tLIMIT should be selected appropriately based on the worst MOSFET safe-operatingarea with the OUT pin shorted to ground. A IFTMR(RST) pull-down source is active when resetting the fault status. The current sources at the FTMR pin can be overdriven externally. The FTMR pin can be pulled high externally above VFTMR(H) to force a fault status or the FTMR pin can be pulled low externally towards ground to force a reset status. Both the FAULT and GATE pins behave the same way for externally driven FTMR as described above for internal mode. A prolonged external pull-down is not recommended as it may mask normal FTMR operation. Selecting Current Limit to Circuit Breaker Ratio The ratio of the current limit voltage VLIMIT and circuit breaker voltage VCB can be configured to allow low duty cycle, high crest factor load events like hard drive spin up to operate above the maximum average load current without invoking current limit. Avoiding current limit events is a good practice as the load voltage is not glitched unnecessarily by the current limit amplifier and the MOSFET power dissipation is kept low. The unlatched CLS pin has three input states (low, open and high). This pin configures both Hot Swap channels simultaneously the preset current limit voltage VLIMIT to approximately 1.5×, 2× or 3× of 1.15 • VCB. However, higher current limit settings will result in higher MOSFET power dissipation in the event of a load short. Proper choice of the MOSFET must accommodate high MOSFET power dissipation under the worst case short-circuit. There are three IFTMR(CL), each corresponds with a VLIMIT selected by the CLS input. The typical MOSFET SOA (safe operating area) has a constant P2t characteristic for single narrow (<10ms) pulse dissipation. An increase in current (VLIMIT) for constant MOSFET drain/source voltage results in square reduction in allowed stress duration tLIMIT (or square increase in IFTMR(CL)). The CLS pin is internally pulled to 1.23V. If it is driven by a three-state output, the maximum allowable opencircuit leakage is ±2µA. The driving output must source or sink more than 10µA in the high or low state. If the CLS trace crosses noisy digital signal lines, an RC filter close to the CLS pin will filter noise pickup (as shown in Figure 1: R5/C3). Auto-Retry vs Latchoff The LTC4226-2 (automatic retry) version resets the FTMR pin after a 0.5 second delay following a FTMR(H) comparator timeout if the VCC voltage remains above the 4V undervoltage lockout threshold VCC(UVL) and the ON pin remains above its 1.23V VON threshold. This retry delay can be terminated to force a 50ms delay restart by cycling VCC below the VCC(UVL) undervoltage threshold or a 10ms delay restart by cycling the ON pin below the VON threshold. The latchoff option (LTC4226-1) does not reset FTMR(L) comparator automatically. It requires voltage cycling at either the ON pin or the VCC pin to reset FTMR pin. Resetting Faults The circuit breaker fault can be reset by cycling the ON pin below and then above the ON comparator threshold. There is a turn on delay of 10ms after the ON pin transitions high. Alternatively, the VCC pin can be cycled below and then above the undervoltage lockout threshold to reset faults. There is a turn on delay of 50ms after the VCC pin exits the undervoltage lockout. The FTMR pin reset begins with the FTMR pin pulled down with 100µA to ground. This is followed by a start-up with a 10µA FAULT pin pull-up and a 9µA GATE pin pull-up. 4226f 14 LTC4226 Applications Information Fault Status The FAULT status pin is active low with a 10µA current source pull-up to a diode below its internal supply voltage, typically 5V for any VCC >7V. When a fault occurs, the FAULT pin pulls to ground with a 5mA limit. Although the FAULT pin has the same voltage rating as the supply pin, sinking LED current as in Figure 9 requires a series resistor to reduce pin power dissipation. The FAULT pin is also an unlatched input to synchronize the MOSFET GATE. Pulling this pin externally below 0.3V causes the GATE to shutoff immediately. This pin can optionally be wire-ORed with other LTC4226's FAULT pins to turn off their GATEs when one of the LTC4226 has a circuit breaker fault with the FTMR pin asserted at VFTMR(H). The other LTC4226's FTMR pin is unaffected by the low external FAULT input. When the LTC4226 with fault is reset (see section on auto-retry and resetting faults), the wire-ORed FAULT pins return high and the GATEs revert to their prior states. It is not recommended to connect an LED to wire-ORed FAULT pins. used as FAULT indicators with resistors to reduce power dissipation at the FAULT pins. VCC Overvoltage Detection The FTMR pin can be used to detect a VCC overvoltage condition with a Zener diode Z2 as shown in Figure 6. Resistor R5 and Zener Z3 protect the FTMR pin from excessive voltage while R6 provides a ground path. An overvoltage at VCC beyond 35V will pull the FTMR pin above 1.23V through diode D2A and force a fault status. If VCC has a transient suppressor as shown in Figure 10, the overvoltage threshold should be set at 35V which is below the transient suppressor SMCJ33A minimum breakdown voltage of 36.7V. VCC Z2 33V R5 1k D2A 1N4148 FTMR Z3 3V R6 1M 4226 F06 Daisy Chained Ports Figure 7, illustrates FireWire power distribution with LTC4226 Hot Swap circuits and supply diode-ORing. The Firewire devices can be power providers or power consumers and can be daisy chained together. In Figure 8, a 2-port device allows either port to be powered internally through diode D1 or to be powered from the opposite port. The higher voltage source delivers power to the external port devices and the internal FireWire controller interface. This permits the host power to be shutdown while the FireWire controller remains active with external power provided by the port. The port can relay actively current limited power as long as there are power sources in the chain. More than two ports per device are possible permitting power consumption or distribution among multiple ports. The ports allow live plugging and unplugging with port load capacitances as large as 1mF at 33V for Figure 8. The output port step up surge current is actively limited. Figure 9 shows a 12V host power source application that can drive a remote load capacitance up to 100µF with a small MOSFET like the Si2318DS. 2mA rated LEDs can be Figure 6. VCC Overvoltage Detection Supply Transient Protection All pins on the LTC4226 are tested for 44V operation with the exception of FTMR and GATE. The GATE pins are voltage clamped either to OUT or GND while the FTMR pins are low voltage. If greater than 44V supply transients are possible, 33V transient suppressors are highly recommended at the VCC pins to clamp the voltage below the 55V absolute maximum voltage rating of the pins. Output Positive Overvoltage Isolation Transient voltage suppressors are adequate for clamping short overvoltage pulses at the ports, but they may overheat if forced to sink large currents for extended periods. Figure 10 shows how series MOSFETs can be used to isolate positive port voltages up to the MOSFET VBVDSS. Q3 and Q4 are turned off when the overvoltage detection Zener Z2 pulls both FTMR1 and FTMR2 high through D2A and D2B. The resistors R7 and R8 with MOSFETs Q5 and Q6 facilitate restart by pulling up through the body diodes of Q1 and Q2, respectively. 4226f 15 LTC4226 Applications Information NODE B 1394 SOCKET NODE A LTC4226 1394 PLUG 1394 SOCKET 1394 PLUG 1394 SOCKET POWER CONSUMER POWER PATH 1394 SOCKET POWER SOURCE NODE C LTC4226 1394 SOCKET 1394 PLUG 1394 PLUG 1394 SOCKET POWER PROVIDER (MASTER) LTC4226 POWER PATH 1394 SOCKET NODE D LTC4226 POWER SOURCE 1394 PLUG 1394 SOCKET 1394 PLUG 1394 SOCKET POWER CONSUMER 4226 F07 ALTERNATE POWER PROVIDER (SLAVE) Figure 7. FireWire Power Distribution Example D1 SS3P5 OPTIONAL 7V TO 33V RS1 30mΩ V REG R1 150k R3 150k PHY VCC1 SENSE1 GATE1 OUT1 ON1 FTMR1 FAULT1 OPTIONAL CONTROLLER LTC4226-2 CLS GND FAULT2 FTMR2 ON2 R2 50k + C1 10µF Z1 SMCJ33A PORT 1 1394 1394 SOCKET PLUG Q1 FDMS86500DC OR Si7164DP R4 50k VCC2 SENSE2 GATE2 RS2 30mΩ OUT2 Q2 FDMS86500DC OR Si7164DP 1.5A CT1 220nF CT2 220nF PORT 2 1394 1394 SOCKET PLUG 1.5A 4226 F08 Figure 8. 2-Port FireWire Master or Slave Application 4226f 16 LTC4226 Applications Information D1 SS3P5 OPTIONAL 12V RS1 33mΩ FAULT INDICATORS R1 4.7k VCC1 LED1 SENSE1 GATE1 1.35A OUT1 ON1 FTMR1 CT1 15nF FAULT1 LTC4226-2 CLS R2 4.7k PORT 1 1394 1394 SOCKET PLUG Q1 Si2318CDS GND CT2 15nF FAULT2 FTMR2 ON2 LED2 VCC2 SENSE2 GATE2 PORT 2 1394 1394 SOCKET PLUG Q2 Si2318CDS RS2 33mΩ Z1 DFLT15A OUT2 1.35A 4226 F09 Figure 9. 12V FireWire Ports with LED Fault Indicators R7 1k D1 SS3P5 RS1 30mΩ OPTIONAL 7V TO 33V V REG R1 150k R3 150k PHY VCC1 SENSE1 GATE1 LTC4226-2 C1 10µF Z1 SMCJ33A FTMR2 SENSE2 GATE2 RS2 30mΩ RG2 10Ω OUT2 Q2 FDMS86500DC OR Si7164DP D2B MMBD4148CA Q4 FDMS2672 OR Si7172DP R8 1k Z3 3V CT2 220nF FAULT2 VCC2 1.5A CT1 220nF GND ON2 + D2A MMBD4148CA OUT1 FTMR1 CLS R4 50k PORT 1 1394 1394 SOCKET PLUG RG1 10Ω ON1 R2 50k R5 1k Q3 FDMS2672 OR Si7172DP Q1 FDMS86500DC OR Si7164DP FAULT1 OPTIONAL CONTROLLER Z2 33V Q5 BSS139 PORT 2 1394 1394 SOCKET PLUG 1.5A 4226 F10 Q5 BSS139 R6 1M Figure 10. 2 FireWire Ports with Positive Overvoltage Isolation 4226f 17 LTC4226 Applications Information Design Example Setting the current limit fault timeout at about 14ms gives: As a design example, take the following specifications for Figure 8 with a load capacitor COUT of 1mF (not shown on schematic) at the cable end of port 1: t • 20µA CT = LIMIT = 228nF 1.23V The channel is rated for a maximum VCC of 33V at 1.5A, COUT = 1mF and current limit at 1.5× of circuit breaker current. Choose a standard value of 220nF. The resulting FTMR timeout in current limit is: tLIMIT = 13.5ms Circuit breaker current plus a 15% margin: The FTMR circuit breaker timeout is: ICB = 1.5A • 1.15 = 1.725A, tCB = 135ms Sense resistor: The resistor pair R1 and R2 sets the ON threshold voltage for both channels. In this case R1 = 150k, R2 = 50k: RS = 50mV ≈ 29mΩ 1.5A • 1.15 Start-up in current limit with CLS low, VCC ON Threshold = (R1+R2) •1.23 = 4.92V R2 VLIMIT = 1.5 • 1.15 • VCB Layout Considerations and To achieve accurate current sensing, Kelvin connections for the sense resistor are recommended. The PCB layout of Kelvin sensing traces should be balanced, symmetrical and minimized to reduce error. In addition, the PCB layout for the sense resistors and the power MOSFETs should include good thermal management techniques for device power dissipation such as vias and wide metal area. A recommended PCB layout for the sense resistor and power MOSFET is illustrated in Figure 11. To avoid the need for the additional MOSFET GATE pin resistor (R1 in Figure 13), the GATE trace over ground plane should have minimized trace length and capacitance. ILIMIT = 1.5 • 1.15 • ICB ≈ 2.98A Calculate the time it takes to charge up COUT in current limit: tCHARGE = COUT • VCC ≈ 11ms ILIMIT During a normal start-up where all of the current charges COUT, the average power dissipation in the MOSFET is given by: V •I PDISS = CC LIMIT = 49.2W 2 Q2 RS2 If the output is shorted to ground, the average power dissipation in MOSFET doubles: RG2 PDISS = VCC • ILIMIT = 98.4W The SOA (safe operating area) curve for the FDMS86500DC MOSFET shows 100W for 35ms. During a normal startup the MOSFET dissipates 49.2W for 11ms at 33V with adequate SOA margin. LTC4226 1 RG1 RS1 Q1 4226 F11 Figure 11. Recommended Layout 4226f 18 LTC4226 Applications Information resistors. Separate resistors allow different current limit in each direction to be set. The transient suppressor at the sense pins allow the circuit breaker to trip when either the input or output voltage exceeds the suppressor breakdown voltage. When the OUT voltage exceeds the suppressor breakdown, GATE2 shuts down after FTMR2 time-out and this can prevent suppressor blow out. The timing capacitor at FTMR2 can be selected to keep the suppressor within safe operating area. In Hot Swap applications where load currents can be 5A, narrow PCB tracks exhibit more resistances than wide tracks and operate at elevated temperatures. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 0.5mΩ/ square. The use of vias allow multi-copper planes to be used to improve both electrical conduction and thermal dissipation. Thicker top and bottom copper such as 3oz or more can improve electrical conduction and reduce PCB trace dissipation. High Current Applications Figure 13 and Figure 14 show 44A and 89A continuous current applications for bus power distribution. The bus connection inductance causes a supply dip at the sense resistor when there is a load transient. The worst transient is a short at the output or the sudden connection of an uncharged load capacitor. Without capacitors C1 and C2 for channel 1, VCC1 voltage can dip below the LTC4226 undervoltage lockout threshold resulting in a channel 1 UVLO reset. The low ESR electrolytic capacitor C1 and ceramic capacitor C2 should be placed very close to the sense resistor VCC1 terminal and the ground plane to minimize inductance. It is important to minimize noise pickup on PCB traces for ON, FTMR, FAULT, CLS and GATE. If an RG resistor is used, place the resistor as close to the MOSFET gate as possible to limit the parasitic trace capacitance that leads to MOSFET self-oscillation. Bidirectional Current Limiting Figure 16 shows an application with bidirectional current limiting with a common sense resistor. Figure 12 shows an asymmetric bidirectional current limiter for operating voltage between 7V and 30V using two separate sense 30mΩ VIN 7V TO 30V RANGE 50mΩ FDMS86500DC OR Si7164DP FDMS86500DC OR Si7164DP SMCJ33A VCC1 SENSE1 SENSE2 VCC2 ON1 FAULT1 CLS FAULT2 FAULT1 CLS GATE1 OUT1 OUT2 GATE2 FTMR1 LTC4226-2 220nF GND FAULT2 ON2 OUT 7V TO 30V RANGE 1.48A/0.89A 220nF FTMR2 4226 F12 Figure 12. 7V to 30V Asymmetric Bidirectional Current-Limiter 4226f 19 LTC4226 Applications Information RS1 1mΩ 12V + R1 10k R2 10k C1 1000µF 25V C2 22µF ×10 25V X5R Q1 IRF2804S-7PPBF VCC1 SENSE1 GATE1 OUT1 ON1 ON1 FTMR1 FAULT1 FAULT1 LTC4226-2 CLS GND FAULT2 FAULT2 FTMR2 ON2 ON2 VCC2 SENSE2 GATE2 + C3 1000µF 25V C4 22µF ×10 25V X5R RS2 1mΩ CT1 10nF CT2 10nF OUT2 RG2 10Ω Z1 SM6S15AHE3/2D OUTPUT1 12V, 44A CG1 RG1 10nF 10Ω Q2 IRF2804S-7PPBF CG2 10nF OUTPUT2 12V, 44A 4226 F13 Figure 13. Dual Continuous 44A Typical Output At the occurrence of severe load transient, the GATE1 voltage undershoots the voltage needed for current limit regulation. The RG1 and CCG1 network between GATE1 and OUT1 help restore GATE1 voltage quickly to the voltage needed for current limit regulation. When a heatsink is a used and gate interconnect has significant capacitance and inductance, optional resistors R1 and R2 can be inserted close to the MOSFET’s gate to prevent parasitic oscillation. The product of R1 and MOSFET CISS add delay to the current limit response. For short PCB gate interconnection, these optional resistors are not needed. Two Hot Swap channels with identical sense resistors and MOSFETs can have their outputs connected together to almost double the current output capability without significant improvement in MOSFET’s SOA. OUTPUT1 in Figure 14 can be connected to OUTPUT2 to give 178A. FTMR1 and FTMR2 should be kept separate as capacitors CT1 and CT2 individually monitor the sense voltages across RS1 and RS2 respectively. In the event of a current fault, one channel may time out earlier than the adjacent channel due to mismatch. If FAULT1 and FAULT2 are kept separate, the current in the channel of the first fault is diverted to the adjacent channel with a second fault time out occurring later. Now consider the case where FAULT1 and FAULT2 are tied together during a current fault. First fault channel FAULT1 pulls low and this causes an input low at FAULT2 with GATE2 pulling low immediately. FTMR2 does not time out due to the common FAULT connection with GATE2 disabled earlier than the case of separate FAULT connection. The MOSFET Q1 where the first occurrence of current fault occurs would not be stressed as much as Q2 since the fully enhanced Q2 determines the parallel channels VCC and OUT voltage drop. Common ON pin connections are preferred for parallel channel applications. 4226f 20 LTC4226 Applications Information RS1 Q1 0.5mΩ IRF1324S-7PPBF +12V + R3 10k R4 10k C1 1000µF ×2 25V C2 22µF ×20 25V X5R CG1 RG1 10nF 10Ω R1* 10Ω VCC1 OUTPUT1 12V, 89A SENSE1 GATE1 OUT1 ON1 ON1 FTMR1 CT1 1nF FAULT1 FAULT1 LTC4226-2 CLS GND CT2 1nF FAULT2 FAULT2 FTMR2 ON2 ON2 VCC2 SENSE2 GATE2 R2* 10Ω Z1 SM8S15AHE3/2D + C3 1000µF ×2 25V C4 22µF ×20 25V X5R OUT2 RG2 10Ω CG2 10nF OUTPUT2 12V, 89A Q2 RS2 0.5mΩ IRF1324S-7PPBF CONNECTION OPTION TO SHARE MOSFET SOA *OPTIONAL 4226 F14 Figure 14. Dual Continuous 89A Typical Output One drawback of the separate FTMR scheme for parallel channels is that one timer may ramp up in current limit mode before the other channel, resulting in shorter circuit breaker timer duration and/or a reduction in the combined circuit breaker current threshold due to RDS(ON) mismatch. These issues are solved by using two cross-coupled PNP clamps connected between the FTMR pins as shown in Figure 15. The FAULT pins are shorted together and connected to an external open drain pull-down which is controlled by a gate synchronization signal. The PNPs prevent a current limited channel’s FTMR from ramping up too fast while the other channel is still in circuit breaker mode. If only one of the channels is in current limit mode, the clamp from the other channel will slow down the current limited channel’s FTMR ramp rate as shown in Figure 15’s accompanying waveforms. This scheme assumes common VCC and ON pins, and both channels should be on the same chip. Channel to channel matching is 6% for VCB, 6% for VLIMIT, and GATE high skew delay timing for both ON and VCC are 10%. The GATE pins must be synchronized by asserting the FAULT inputs low to mask out tON(UVL) skew. Asserting the FAULT pins low for at least 100ms at power-up will ensure that the MOSFETs turn on together. LTC4226 FTMR2 FTMR1 FAULT1 FAULT2 FTMR2 FAULT DELAYED OFF ON CT1 10nF Q3 Q4 2N3906 2N3906 CT2 10nF FTMR 0.5V/DIV IOUT 5A/DIV FAULT 5V/DIV FTMR1 TOTAL OUTPUT CURRENT FAULT 1ms/DIV 4226 F15 Figure 15. PNP Connected FTMR for 2 Parallel Channels 4226f 21 LTC4226 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1700 Rev A) Exposed Pad Variation AA 0.70 ±0.05 3.50 ±0.05 1.65 ±0.05 2.10 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER R = 0.115 TYP 0.75 ±0.05 15 PIN 1 TOP MARK (NOTE 6) 16 0.40 ±0.10 1 1.65 ±0.10 (4-SIDES) 2 (UD16 VAR A) QFN 1207 REV A 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-4) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ±0.05 0.50 BSC 4226f 22 LTC4226 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 4.039 ± 0.102 (.159 ± .004) (NOTE 3) 0.50 (.0197) BSC 0.305 ± 0.038 (.0120 ± .0015) TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0° – 6° TYP 0.280 ± 0.076 (.011 ± .003) REF 16151413121110 9 GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 1234567 8 0.50 NOTE: (.0197) 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS16) 1107 REV Ø 4226f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC4226 Typical Application 30mΩ Si7164DP VIN 7V TO 30V Si7164DP OUT 7V TO 30V 1.48A SMCJ33A OUT2 GATE2 SENSE2 VCC1 VCC2 SENSE1 GATE1 OUT1 ON1 FAULT1 CLS FAULT2 FTMR1 FAULT1 LTC4226-2 CLS 220nF GND FAULT2 220nF FTMR2 ON2 4226 F16 Figure 16. Bidirectional Current-Limiter Related Parts PART NUMBER DESCRIPTION COMMENTS LTC1421 Dual Channel Hot Swap Controller Operates from 3V to 12V, Supports –12V LTC1422 Single Channel Hot Swap Controller Operates from 2.7V to 12V LTC1645 Dual Channel Hot Swap Controller Operates from 3V to 12V, Power Sequencing, LTC1647 Dual Channel Hot Swap Controller Operates from 2.7V to 16.5V LTC4210 Single Channel Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting LTC4211 Single Channel Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control LTC4215 Single Hot Swap Controller with ADC and I2C Interface Operates from 2.9V to 15V, Monitors Voltage and Current with 8-Bit ADC LTC4216 Single Channel Hot Swap Controller Operates from 0V to 6V LTC4218 Single Channel Hot Swap Controller Operates from 2.9V to 26.5V, Adjustable, 5% Accurate (15mV) Current Limit LTC4222 Dual Hot Swap Controller with ADC and I2C Interface Operates from 2.9V to 29V, Digitally Monitors Voltage and Current with 10-Bit ADC LTC4224 Dual Channel Hot Swap Controller Operates from 1V to 6V LTC4227 Dual Ideal Diode and Single Hot Swap Controller Operates from 2.9V to 18V LTC4228 Dual Ideal Diode and Hot Swap Controller Operates from 2.9V to 18V LTC4230 Triple Channel Hot Swap Controller Operates from 1.7V to 16V, Multifunction Current Control LTC4280 Single Hot Swap Controller with ADC and I2C Interface Operates from 2.9V to 15V, Monitors Voltage and Current with 8-Bit ADC LTC4352 Ideal Diode Controller with Monitoring Operates from 0V to 18V, UV, OV LTC4364 Surge Stopper/Hot Swap Controller with Ideal Diode Operates from 4V to 80V, –40V Reverse Input 4226f 24 Linear Technology Corporation LT 1012 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2012