LT8494 - SEPIC/Boost DC/DC Converter with 2A, 70V Switch, and 7μA Quiescent Current

LT8494
SEPIC/Boost DC/DC
Converter with 2A, 70V Switch,
and 7µA Quiescent Current
FEATURES
DESCRIPTION
Low Ripple Burst Mode® Operation:
7µA IQ at 12VIN to 5VOUT
Output Ripple (<10mV Typ.)
nn Dual Supply Pins:
Improves Efficiency
Reduces Minimum Supply Voltage to ~1V after
Start-Up to Extend Battery Life
nn Wide Input Voltage Range of ~1V to 60V (2.5V to
32V for Start-Up)
nn PG Functional for Input Supply Down to 1.3V
nn FMEA Fault Tolerant in TSSOP Package
nn Fixed Frequency PWM, SEPIC/BOOST/FLYBACK
Topologies
nn NPN Power Switch: 2A/70V
nn Programmable Switching Frequency: 250kHz to 1.5MHz
nn UVLO Programmable on SWEN Pin
nn Soft-Start Programmable with One Capacitor
nn Small 20-Lead QFN or 20-Lead TSSOP Packages
The LT®8494 is an adjustable frequency (250kHz to 1.5MHz)
monolithic switching regulator. Quiescent current can be
less than 7µA when operating and is ~0.3µA when SWEN
is low. The LT8494 can be configured as either a SEPIC,
boost or flyback converter.
APPLICATIONS
Additional features such as frequency foldback and softstart are integrated. The LT8494 is available in 20-lead
QFN and 20-lead TSSOP packages with exposed pads
for low thermal resistance. Fault tolerance in the TSSOP
allows for adjacent pin shorts or an open without raising
the output voltage above its programmed value.
nn
The low ripple Burst Mode operation maintains high
efficiency at low output current while keeping output
ripple below 10mV. Dual supply pins (VIN and BIAS) allow
the part to automatically operate from the most efficient
supply. Input supply voltage can be up to 60V for SEPIC
topologies and up to 32V (with ride-through up to 60V)
for boost and flyback topologies. After start-up, battery
life is extended since the part can draw current from its
output (BIAS) even when VIN voltage drops below 2.5V.
Using a resistor divider on the SWEN pin provides a programmable undervoltage lockout (UVLO) for the converter.
A power good flag signals when VOUT reaches 92% of the
programmed output voltage.
Automotive ECU Power
Power for Portable Products
nn Industrial Supplies
nn
nn
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
450kHz, 5V Output SEPIC Converter
VOUT
5V
0.35A (VIN = 3V)
0.6A (VIN = 5V)
1.0A (VIN > 12V)
15µH
4.7µF
VIN SW
BIAS
SWEN
LT8494
PG
RT SS
GND FB
169k
1µF
Efficiency
1M
316k
4.7pF
47µF
×2
8494 TA01a
90
85
VIN = 24V
80
VIN = 12V
15
EFFICIENCY (%)
•
SUPPLY CURRENT (µA)
15µH
•
VIN
3V TO 60V
No-Load Supply Current
20
2.2µF
10
VIN = 5V
75
70
5
65
0
0
12
24
36
INPUT VOLTAGE (V)
48
60
8494 TA01b
60
0.0
0.2
0.4
0.6
LOAD CURRENT (A)
0.8
1.0
8494 TA01c
8494f
For more information www.linear.com/LT8494
1
LT8494
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, BIAS Voltage.......................................................60V
SWEN Voltage............................................................60V
FB Voltage..................................................................60V
SW Voltage................................................................70V
PG Voltage...................................................................6V
RT Voltage...................................................................6V
SS Voltage...................................................................3V
Operating Junction Temperature Range
LT8494E, LT8494I (Notes 2, 3)........... –40°C to 125°C
LT8494H (Notes 2, 3)......................... –40°C to 150°C
Storage Temperature Range............... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FE Package........................................................ 300°C
PIN CONFIGURATION
TOP VIEW
19 NC
FB
3
18 VIN
NC
4
17 NC
NC
5
NC
6
PG
7
14 GND
SS
8
13 NC
NC
9
12 SWEN
FB
20 SW
2
NC
1
FB
NC
BIAS
20 19 18 17 16
PG
BIAS
TOP VIEW
SS 1
15 GND
RT 2
14 GND
21
GND
GND 3
GND 4
13 GND
12 SW
NC 5
8
NC
NC
9 10
VIN
7
GND
6
SWEN
11 GND
21
GND
RT 10
UF PACKAGE
20-LEAD (4mm × 4mm) PLASTIC QFN
θJA = 47°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
16 GND
15 NC
11 NC
FE PACKAGE
20-LEAD PLASTIC TSSOP
θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8494EUF#PBF
LT8494EUF#TRPBF
8494
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LT8494IUF#PBF
LT8494IUF#TRPBF
8494
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LT8494EFE#PBF
LT8494EFE#TRPBF
LT8494FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT8494IFE#PBF
LT8494IFE#TRPBF
LT8494FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT8494HFE#PBF
LT8494HFE#TRPBF
LT8494FE
20-Lead Plastic TSSOP
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
8494f
2
For more information www.linear.com/LT8494
LT8494
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VSWEN = 12V, VBIAS = 5V, unless otherwise noted (Note 2).
PARAMETER
CONDITIONS
TYP
MAX
Minimum VIN Operating Voltages
VBIAS < 2.5V
VBIAS ≥ 2.5V
l
l
MIN
2.4
2.5
0
V
V
Minimum BIAS Operating Voltages
VIN < 2.5V
VIN ≥ 2.5V
l
l
2.4
2.5
0
V
V
Power Switch Driver (PSD) Overvoltage Threshold
(Note 4)
VIN or BIAS Rising
VIN or BIAS Falling
l
l
34
33.9
36.5
36.4
V
V
32.1
32
Power Switch Driver (PSD) Overvoltage Threshold
Hysteresis (Note 4)
Quiescent Current from VIN
Quiescent Current from BIAS
BIAS to VIN Comparator Threshold
100
VSWEN = 0V
VSWEN = 5V, VFB = 1.25V
VSWEN = 5V, VFB = 1.25V (LT8494E, LT8494I)
VSWEN = 5V, VFB = 1.25V (LT8494H)
UNITS
mV
l
l
0.3
3.0
3.0
3.0
0.9
4.8
6.2
8.0
µA
µA
µA
µA
VSWEN = 0V
VSWEN = 5V, VFB = 1.25V
VSWEN = 5V, VFB = 1.25V (LT8494E, LT8494I)
VSWEN = 5V, VFB = 1.25V (LT8494H)
l
l
0.07
1.7
1.7
1.7
0.5
2.8
3.5
10
µA
µA
µA
µA
VBIAS-VIN, VBIAS Rising, VIN = 12V
VBIAS-VIN, VBIAS Falling, VIN = 12V
Hysteresis (Rising-Falling Threshold)
l
l
l
0.55
0.17
0.20
0.9
0.37
0.53
1.2
0.57
0.8
V
V
V
l
1.178
Feedback Voltage
1.202
1.230
V
FB Pin Bias Current (Note 7)
VFB = 1.202V
0.1
20
nA
FB Voltage Line Regulation
5V ≤ VIN ≤ 32V, BIAS = 5V
5V ≤ VIN ≤ 32V, BIAS = 0V
0.2
0.2
10
10
m%/V
m%/V
Minimum Switch Off-Time
70
Minimum Switch On-Time
ns
95
RT = 68.1k
RT = 324k
ns
l
l
0.92
219
1.0
250
1.06
280
MHz
kHz
Switch Current Limit at Minimum Duty Cycle (Note 5)
l
2.1
2.55
2.95
A
Switch Current Limit at Maximum Duty Cycle (Note 6)
l
1.3
1.85
2.4
A
Switching Frequency
Switch VCESAT
ISW = 1.2A
340
Switch Leakage Current (Note 7)
VSW = 12V, VSWEN = 0V
0.01
1
μA
8.2
12.2
μA
0
35
240
25
200
550
nA
nA
nA
1
1.1
V
Soft-Start Charging Current (Note 7)
VSS = 100mV
SWEN Pin Current (Note 7)
VSWEN = 1.2V
VSWEN = 5V
VSWEN = 12V
SWEN Rising Voltage Threshold
l
5.2
l
0.9
l
l
86
82
SWEN Voltage Hysteresis
PG Threshold as % of VFB Regulation Voltage
mV
30
VFB Rising
VFB Falling
PG Hysteresis
92
88
mV
97
93
46
%
%
mV
PG Output Voltage Low
ISINK = 1.25mA
ISINK = 100μA, VBIAS = 0V, VIN = 1.3V
ISINK = 100μA, VBIAS = 1.3V, VIN = 0V
l
l
l
33
15
15
150
150
150
mV
mV
mV
PG Leakage Current
VPG = 5V (LT8494E, LT8494I)
VPG = 5V (LT8494H)
l
l
0
0
0.3
1.0
μA
μA
8494f
For more information www.linear.com/LT8494
3
LT8494
ELECTRICAL CHARACTERISTICS
Note 1:Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Voltages are with respect to GND pin unless
otherwise noted.
Note 2:The LT8494E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8494I is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. The LT8494H is guaranteed over the full
–40°C to 150°C operating junction temperature range. Operation lifetime is
derated at junction temperatures greater than 125°C.
Note 3:This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating range when
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair device
reliability.
Note 4:See Power Supplies and Operating Limits in the Applications
Information section for more details.
Note 5:Current limit guaranteed by design and/or correlation to static test.
Slope Compensation reduces current limit at higher duty cycles.
Note 6:Max duty cycle current limit measured at 1MHz switching
frequency.
Note 7:Polarity specification for all currents into pins is positive. All
voltages are referenced to GND unless otherwise specified.
TYPICAL PERFORMANCE CHARACTERISTICS
No Load Supply Current
FRONT PAGE APPLICATION
VIN=12V
Load Regulation
0.15
FRONT PAGE APPLICATION
0.10
2.0
60
40
20
TYPICAL
LOAD REGULATION (%)
SUPPLY CURRENT (µA)
80
Maximum Load Current
2.5
LOAD CURRENT (A)
100
TA = 25°C unless otherwise specified.
1.5
1.0
MINIMUM
0.5
0
–50
–10
30
70
110
TEMPERATURE (°C)
150
0.0
8494 G04
Switching Waveforms, Burst
Mode Operation
0.05
0.00
–0.05
0
12
24
36
VIN (V)
48
60
–0.15
VSW
10V/DIV
IL
0.5A/DIV
IL
0.5A/DIV
VOUT
5mV/DIV
VOUT
5mV/DIV
200
400
600
800
LOAD CURRENT (mA)
1000
8495 G18
Transient Load Response, Load
Current is Stepped from 20mA
(Burst Mode Operation) to 220mA
VOUT
100mV/DIV
IL
0.5A/DIV
10µs/DIV
1µs/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
ILOAD = 20mA
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
ILOAD = 0.5A
8494 G16
0
8494 G05
Switching Waveforms, Full
Frequency Continuous Operation
VSW
10V/DIV
VIN=12V
FRONT PAGE APPLICATION
REFERENCED TO VOUT AT 100mA LOAD
–0.10
500µs/DIV
8494 G18
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
8494 G17
8494f
4
For more information www.linear.com/LT8494
LT8494
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Load Response, Load
Current is Stepped from 300mA
to 500mA
Switch Current Limit at Minimum
Duty Cycle
500µs/DIV
8494 G19
3.0
3.0
2.5
2.5
SWITCH CURRENT LIMIT (A)
IL
0.5A/DIV
SWITCH CURRENT LIMIT (A)
Switch Current Limit at 500kHz
VOUT
50mV/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
TA = 25°C unless otherwise specified.
2.0
1.5
1.0
0.5
0.0
10
20
30
40 50 60 70
DUTY CYCLE (%)
80
2.0
1.5
1.0
0.5
0
–50
90
0
50
100
TEMPERATURE (°C)
8494 G06
Feedback Voltage
Switch VCESAT
FB VOLTAGE (V)
SWITCH VCESAT (mV)
1.22
400
300
200
1.21
1.20
0.5
RT = 324k
0
1.0
0.5
1.5
SWITCH CURRENT (A)
1.18
–50
2.0
0
50
100
TEMPERATURE (°C)
8494 G08
0.0
–50
150
Frequency Foldback
Minimum Switch On-Time
Minimum Switch Off-Time
400
RT = 324k
200
160
SWITCH OFF-TIME (ns)
SWITCH ON-TIME (ns)
600
100
80
60
40
20
0
0.2
0.5
0.7
FB VOLTAGE (V)
1.0
1.2
8494 G12
0
–50
150
180
120
RT = 68.1k
800
100
50
TEMPERATURE (°C)
8494 G11
140
1000
0
8494 G09
1200
SWITCHING FREQUENCY (kHz)
RT = 68.1k
1.0
1.19
100
0
Oscillator Frequency
1.5
1.23
500
0
8494 G07
FREQUENCY (MHz)
600
150
140
120
100
80
60
40
20
0
100
50
TEMPERATURE (°C)
150
8494 G13
0
–50
0
100
50
TEMPERATURE (°C)
150
8494 G14
8494f
For more information www.linear.com/LT8494
5
LT8494
TYPICAL PERFORMANCE CHARACTERISTICS
Overvoltage Lockout
TA = 25°C unless otherwise specified.
Internal UVLO
35.5
PG Pin Current vs Supply Voltage
2.50
20
PG = 0.4V
VIN OR BIAS RISING
34.5
34.0
VIN OR BIAS FALLING
33.5
16
2.45
PG PIN CURRENT (mA)
35.0
VIN/BIAS VOLTAGE (V)
VIN OR BIAS VOLTAGE (V)
18
VIN/BIAS RISING
2.40
VIN/BIAS FALLING
2.35
VIN = BIAS = SWEN
14
12
10
8
VIN = BIAS, SWEN = 0
6
4
2
33.0
–50
0
50
100
TEMPERATURE (°C)
2.30
–50
150
0
50
100
TEMPERATURE (°C)
8494 G15
1000
350
200
150
100
4
5
8494 G22
10k PULL-UP FROM VIN TO PG
PG OUTPUT VOLTAGE (V)
FB PIN CURRENT (µA)
250
2
3
VIN VOLTAGE (V)
3
100
300
1
PG Output Voltage
vs Supply Voltage
FB Pin Current
400
SWEN PIN CURRENT (nA)
0
8494 G20
SWEN Pin Current
10
1
0.1
2
1
0.01
50
0
0
150
0
10
20
30
40
50
SWEN PIN VOLTAGE (V)
60
0.001
0
10
8494 G23
20
30
40
FB VOLTAGE (V)
50
QUIESCENT CURRENT (µA)
CURRENT INTO PIN (nA)
5
40
IFB
0
–50
ISWEN
0
1
2
VIN/BIAS VOLTAGE (V)
3
8494 G25
Quiescent Current
VIN = 1.25V
VSWEN = 1.2V
20
0
8494 G24
Pin Current
60
0
60
100
50
TEMPERATURE (°C)
150
VIN = 12V
VBIAS = VSWEN = 5V
VFB = 1.25V
4
CURRENT INTO VIN
3
2
CURRENT INTO BIAS
1
0
–50
8494 G26
0
100
50
TEMPERATURE (°C)
150
8494 G27
8494f
6
For more information www.linear.com/LT8494
LT8494
PIN FUNCTIONS
(QFN/TSSOP)
SS (Pin 1/Pin 8):Soft-Start Pin. Place a soft-start capacitor
on this pin. Upon start-up, the SS pin will be charged by
a (nominally) 256k resistor to about 2.1V.
VIN (Pin 10/Pin 18):Supply Input Pin. This pin is typically
connected to the input of the DC/DC converter. Must be
locally bypassed.
RT (Pin 2/Pin 10):Oscillator Frequency Set Pin. Place a
resistor from this pin to ground to set the internal oscillator frequency. Minimize capacitance on this pin. See the
Applications Information section for more details.
SW (Pin 12/Pin 20): Switch Pin. This is the collector of
the internal NPN power switch. Minimize trace area connected to this pin to minimize EMI.
GND (Pins 3, 4, 9, 11, 13, 14, 15, Exposed Pad 21/Pins
14, 16, Exposed Pad 21): Ground. Solder all pins and
the exposed pad directly to the local ground plane. The
exposed pad metal of the package provides both electrical
contact to ground and good thermal contact to the printed
circuit board.
NC (Pins 5, 7, 8, 18, 19/4, 5, 6, 9, 11, 13, 15, 17, 19):
NC pins are not connected to internal circuitry. Some NC
pins in the TSSOP package must be left floating to ensure
FMEA fault tolerance (see Applications Informations section for details).
SWEN (Pin 6/Pin 12):Switch Enable Detect Pin. This pin
enables/disables the switching regulator and soft-start. A
resistor divider can be connected to SWEN to perform an
undervoltage lockout function.
BIAS (Pin 16/Pin 1): Supply Input Pin. This pin is typically connected to the output of the DC/DC converter in
cases where VIN can be higher than VOUT. Must be locally
bypassed.
FB (Pin 17/Pin 2, 3): Output Voltage Feedback Pin. The
LT8494 regulates the FB pin to 1.202V. Connect a resistor divider between the output, FB and GND to set the
regulated output voltage.
PG (Pin 20/Pin 7):The PG pin is the open-drain output of
an internal comparator. PG remains low until the FB pin
is above 92% of the regulation voltage, and there are no
fault conditions. See the Applications Information section
for more details.
8494f
For more information www.linear.com/LT8494
7
LT8494
BLOCK DIAGRAM
2.1V
SS
256k
Q S
SR2
R
100mV
CHIP
SHUTDOWN
–
+
1.202V
FB
1.00V
+
–
DIE
TEMP
165°C
34V
+
–
+
–
VOLTAGE
REFS
ILIMIT
VC_LIMITER
–
+A1
FREQUENCY
FOLDBACK
2.15V
1.10V
1.00V
OTHERS
Burst
Mode
DETECT
VC
34V
–
+
+
–
2.4V
–
+A3
QUADRATIC
RAMP
GENERATOR
1.10V
2.4V
SW
R Q
SR1
S
POWER
SWITCH
DRIVER
Q1
+
–
ADJUSTABLE
OSCILLATOR
–
+
BIAS
LOW POWER MODE
A2
RT
VIN
SUPPLY
SELECT
LOGIC
DISABLE PSD
SOFTSTART
SWEN
+
–
OVP
GND
PG
PGOOD
CHIP
SHUTDOWN
8494 BD
8494f
8
For more information www.linear.com/LT8494
LT8494
OPERATION
The LT8494 is a constant-frequency, current mode
SEPIC/boost/flyback regulator. Operation can be best
understood by referring to the Block Diagram. In the Block
Diagram, the adjustable oscillator, with frequency set by
the external RT resistor, enables an RS latch, turning on
the internal power switch. An amplifier and comparator
monitor the switch current flowing through an internal
sense resistor, turning the switch off when this current
reaches a level determined by the voltage at VC. An error
amplifier adjusts the VC voltage by measuring the output
voltage through an external resistor divider tied to the FB
pin. If the error amplifier’s output voltage (VC) increases,
more current is delivered to the output; if the VC voltage
decreases, less current is delivered. An active clamp on
the VC voltage provides current limit. An internal regulator
provides power to the control circuitry.
In order to improve efficiency, the NPN power switch
driver (see Block Diagram) supplies NPN base current
from whichever of VIN and BIAS has the lower supply
voltage. However, if either of them is below 2.4V or above
34V (typical values), the power switch draws current from
the other pin. If both supply pins are below 2.4V or above
34V then switching activity is stopped.
To further optimize efficiency, the LT8494 automatically
enters Burst Mode operation in light load situations. Between bursts, all circuitry associated with controlling the
output switch is shut down, reducing the VIN/BIAS pin
supply currents to be less than 3µA typically (see Electrical Characteristics).
The LT8494 contains a power good comparator which
trips when the FB pin is above 92% of its regulated value.
The PG output is an open-drain transistor that is off when
the output is in regulation, allowing an external resistor to
pull the PG pin high (See Applications Information section
for details).
Several functions are provided to enable a very clean
start-up for the LT8494.
• First, the SWEN pin voltage is monitored by an internal
voltage reference to give a precise turn-on threshold.
An external resistor divider can be connected from the
input power supply to the SWEN pin to provide a userprogrammable undervoltage lockout function.
• Second, the soft-start circuitry provides for a gradual
ramp-up of the switch current. When the part is brought
out of shutdown, the external SS capacitor is first discharged, and then an integrated 256k resistor pulls the
SS pin up to ~2.1V. By connecting an external capacitor
to the SS pin, the voltage ramp rate on the pin can be
set. Typical values for the soft-start capacitor range
from 100nF to 1µF.
• Finally, the frequency foldback circuit reduces the
maximum switching frequency when the FB pin is below
1V. This feature reduces the minimum duty cycle that
the part can achieve thus allowing better control of the
switch current during start-up.
8494f
For more information www.linear.com/LT8494
9
LT8494
APPLICATIONS INFORMATION
Low Ripple Burst Mode Operation
To enhance efficiency at light loads, the LT8494 regulator
enters low ripple Burst Mode operation keeping the output
capacitor charged to the proper voltage while minimizing
the input quiescent current. During Burst Mode operation,
the LT8494 regulator delivers single-cycle bursts of current to the output capacitor with each followed by a sleep
period where the output power is delivered to the load by
the output capacitor. The quiescent currents of VIN/BIAS
are reduced to less than 3µA typically during the sleep
time (see Electrical Characteristics table).
As the load current decreases towards a no-load condition, the frequency of single current pulses decreases
(see Figure 1), therefore the percentage of time that the
LT8494 operates in sleep mode increases, resulting in
reduced average input current and thus high efficiency
even at very low loads.
By maximizing the time between pulses, the LT8494 quiescent current is minimized. Therefore, to optimize the
quiescent current performance at light loads, the current
in the feedback resistor divider and the reverse current
in the external diode must be minimized, as these appear
to the output as load currents. More specifically, during
the sleep time, the boost converter has the reverse diode
leakage current conducting from output to input, while
the SEPIC converter has leakage current conducting from
output to ground. Use the largest possible feedback resis-
SWITCHING FREQUENCY (kHz)
500
FRONT PAGE APPLICATION
400
In Burst Mode operation, the burst frequency and the
charge delivered with each pulse will not change with
output capacitance. Therefore, the output voltage ripple
will be inversely proportional to the output capacitance.
In a typical application with a 47μF output capacitor, the
output ripple is about 10mV, and with two 47μF output
capacitors the output ripple is about 5mV (see Switching
Waveforms, Burst Mode Operation in Typical Performance
Characteristics section). The output voltage ripple can continue to be decreased by increasing the output capacitance.
At higher output loads the LT8494 regulator runs at the
frequency programmed by the RT resistor and operates as
a standard current mode regulator. The transition between
high current mode and low ripple Burst Mode operation is
seamless, and will not disturb the output voltage.
Setting the Output Voltage
The output voltage is programmed with a resistor divider
from output to the FB pin (R2) and from the FB pin to
ground (R1). Choose the 1% resistors according to:
V

R2 = R1 OUT – 1
 1.202 
Note that choosing larger resistors decreases the quiescent
current of the application circuits. In low load applications,
choosing larger resistors is more critical since the part
enters Burst Mode operation with lower quiescent current.
Power Switch Duty Cycle
In order to maintain loop stability and deliver adequate
current to the load, the power NPN (Q1 in the Block Diagram) cannot remain on for 100% of each clock cycle.
The maximum allowable duty cycle is given by:
300
200
100
0
0.1
tors and a low leakage Schottky diode in applications with
ultralow Q current.
1
10
100
LOAD CURRENT (mA)
1000
DCMAX =
TP –Minimum Switch Off-Time
•100%
TP
8494 F01
Figure 1. Switching Frequency in Burst Mode Operation
8494f
10
For more information www.linear.com/LT8494
LT8494
APPLICATIONS INFORMATION
where TP is the clock period and Minimum Switch Off-Time
(found in the Electrical Characteristics) is typically 70ns.
Conversely, the power NPNs (Q1 in the Block Diagram)
cannot remain off for 100% of each clock cycle, and will
turn on for a minimum time (Minimum Switch On-Time)
when in regulation. This Minimum Switch On-Time governs
the minimum allowable duty cycle given by:
Minimum Switch On-Time
DCMIN =
•100%
T
P
where TP is the clock period and Minimum Switch On-Time
(found in the Electrical Characteristics) is typically 95ns.
The application should be designed such that the operating
duty cycle (DC) is between DCMIN and DCMAX. Normally,
DC rises with higher VOUT and lower VIN.
Duty cycle equations for both boost and SEPIC topologies
are given below, where VD is the diode forward voltage
drop and VCESAT is typically 340mV at 1.2A.
For the boost topology:
DC ≅
VOUT – VIN + VD
VOUT + VD – VCESAT
For the SEPIC topology:
DC ≅
VOUT + VD
VIN + VOUT + VD – VCESAT
The LT8494 can be used in configurations where the duty
cycle is higher than DCMAX, but it must be operated in the
discontinuous conduction mode or Burst Mode operation
so that the effective duty cycle is reduced.
Setting the Switching Frequency
The LT8494 uses a constant frequency PWM architecture
that can be programmed to switch from 250kHz to 1.5MHz
by using a resistor tied from the RT pin to ground. Table 1
shows the necessary RT values for various switching
frequencies.
Table 1. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz)
RT VALUE (kΩ)
0.25
324
0.4
196
0.6
124
0.8
88.7
1.0
68.1
1.2
54.9
1.4
45.3
1.5
41.2
Inductor Selection
General Guidelines: The high frequency operation of the
LT8494 allows for the use of small surface mount inductors.
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. To
improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low DCR
(copper wire resistance) to reduce I2R losses, and must be
able to handle the peak inductor current without saturating. Note that in some applications, the current handling
requirements of the inductor can be lower, such as in the
SEPIC topology when using uncoupled inductors, where
each inductor only carries a fraction of the total switch
current. Molded chokes or chip inductors usually do not
have enough core area to support peak inductor currents
in the 2A to 3A range. To minimize radiated noise, use a
toroidal or shielded inductor. Note that the inductance of
shielded types will drop more as current increases, and
will saturate more easily.
Minimum Inductance: Although there can be a trade-off
with efficiency, it is often desirable to minimize board
space by choosing smaller inductors. When choosing
an inductor, there are two conditions that limit the minimum inductance; (1) providing adequate load current,
and (2) avoidance of subharmonic oscillation. Choose
an inductance that is high enough to meet both of these
requirements.
8494f
For more information www.linear.com/LT8494
11
LT8494
APPLICATIONS INFORMATION
Adequate Load Current: Small value inductors result in
increased ripple currents and thus, due to the limited peak
switch current, decrease the average current that can be
provided to a load (IOUT). In order to provide adequate
load current, L should be at least:
DC • VIN
L>


V
•I
2 ( f )  ILIM – OUT OUT 
VIN • η 

L1||L2 >
( VIN – VCESAT ) • (2DC– 1)
0.76 • (1.5 •DC+1) • f • (1–DC)
for the uncoupled inductor SEPIC topologies.
Maximum Inductance: Excessive inductance can reduce
current ripple to levels that are difficult for the current comparator (A2 in the Block Diagram) to cleanly discriminate,
thus causing duty cycle jitter and/or poor regulation. The
maximum inductance can be calculated by:
For boost topologies, or:
L>
for boost and coupled inductor SEPIC, or:
DC • VIN


V
•I
2 ( f )  ILIM – OUT OUT –IOUT 
VIN • η


LMAX =
VIN – VCESAT DC
•
IMIN(RIPPLE) f
where LMAX is L1||L2 for uncoupled SEPIC topologies and
IMIN(RIPPLE) is typically 150mA.
for the SEPIC topologies.
where:
L = L1||L2 for the uncoupled SEPIC topology
DC = switch duty cycle (see previous section)
ILIM = switch current limit, typically about 2.35A at 50%
duty cycle (see the Typical Performance Characteristics
section)
Current Rating: Finally, the inductor(s) must have a rating
greater than its peak operating current to prevent inductor
saturation resulting in efficiency loss.
In steady state, the peak and average input inductor currents (continuous conduction mode only) are given by:
IL1(PEAK) =
VOUT •IOUT VIN •DC
+
VIN • η
2 •L1• f
η = power conversion efficiency (typically 85% to 90%
for boost and 80% to 85% for SEPIC at high currents)
f = switching frequency
Negative values of L indicate that the output load current
IOUT exceeds the switch current limit capability of the
LT8494.
for the boost and uncoupled inductor SEPIC topology.
Avoiding Subharmonic Oscillations: The internal slope
compensation circuit of LT8494 helps prevent the subharmonic oscillations that can occur when the duty cycle is
greater than 50%, provided that the inductance exceeds
a minimum value. In applications that operate with duty
cycles greater than 50%, the inductance must be at least:
L>
IL1(AVG) =
VOUT •IOUT
VIN • η
For uncoupled SEPIC topologies, the peak and average
currents of the output inductor L2 are given by:
IL2(PEAK) =IOUT +
VOUT • (1–DC)
2 •L2 • f
IL2(AVG) =IOUT
( VIN – VCESAT ) • (2DC– 1)
0.76 • (1.5 •DC+1) • f • (1–DC)
8494f
12
For more information www.linear.com/LT8494
LT8494
APPLICATIONS INFORMATION
For the coupled inductor SEPIC:
the ceramic capacitor at audio frequencies, generating
audible noise. Since LT8494 operates at a lower current
limit during Burst Mode operation, the noise is typically
very quiet. If this is unacceptable, use a high performance
tantalum or electrolytic capacitor at the output.

 V •DC
V
IL(PEAK) =IOUT •  1+ OUT  + IN
 VIN • η  2 •L • f
 V

IL(AVG) =IOUT • 1+ OUT 
 VIN • η 
Diode Selection
Note: Inductor current can be higher during load transients.
It can also be higher during short-circuit and start-up if
inadequate soft-start capacitance is used. Thus, IL(PEAK)
may be higher than the switch current limit of 2.95A, and
the RMS inductor current is approximately equal to IL(AVG).
Choose an inductor having sufficient saturation current
and RMS current ratings.
Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage.
Multilayer ceramic capacitors are an excellent choice, as
they have an extremely low ESR and are available in very
small packages. X5R or X7R dielectrics are preferred, as
these materials retain their capacitance over wider voltage
and temperature ranges. Always use a capacitor with a
sufficient voltage rating. Many capacitors rated at 2.2µF
to 20µF, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired output voltage. Solid
tantalum or OS-CON capacitors can be used, but they will
occupy more board area than a ceramic and will have a
higher ESR with greater output ripple.
Ceramic capacitors also make a good choice for the input
decoupling capacitor, which should be placed as closely as
possible to the VIN and BIAS pins of the LT8494. A 2.2µF
to 4.7µF input capacitor is sufficient for most applications.
Audible Noise
Ceramic capacitors are small, robust and have very low
ESR. However, due to their piezoelectric nature, ceramic
capacitors can sometimes create audible noise when
used with the LT8494. During Burst Mode operation, the
LT8494 regulator’s switching frequency depends on the
load current, and at very light loads the regulator can excite
The diode used in boost or SEPIC topologies conducts
current only during the switch off-time. During the switch
on-time, the diode has reverse voltage across it. The peak
reverse voltage is equal to VOUT in the boost topology
and equal to (VOUT + VIN) in the SEPIC topology. Use a
diode with a reverse voltage rating greater than the peak
reverse voltage.
An additional consideration is the reverse leakage current. The leakage current appears to the output as load
current and affects the efficiency, most noticeably, under
light load conditions. In Burst Mode operation, after the
inductor current vanishes, the reverse voltage across the
boost diode is approximately equal to VOUT – VIN in the
boost topology and VOUT in the SEPIC topology. The percentage of time that the diode is reverse biased increases
as load current decreases.
Schottky diodes that have larger forward voltages often
have less leakage, so a trade-off exists between light
load and high load efficiency. Also the Schottky diodes
with larger reverse bias ratings may have less leakage at
a given output voltage, therefore, superior leakage performance can be achieved at the expense of diode size.
Finally, keep in mind that the leakage current of a power
Schottky diode goes up exponentially with junction temperature. Therefore, the Schottky diode must be selected
with care to avoid excessive increase in light load supply
current at high temperatures.
Soft-Start
The LT8494 contains a soft-start circuit to limit peak
switch currents during start-up. High start-up current is
inherent in switching regulators since the feedback loop
is saturated due to VOUT being far from its final value. The
8494f
For more information www.linear.com/LT8494
13
LT8494
APPLICATIONS INFORMATION
regulator tries to charge the output capacitor as quickly as
possible, which results in large peak currents. The start-up
current can be limited by connecting an external capacitor
(typically 100nF to 1µF) to the SS pin. This capacitor is
slowly charged to ~2.1V by an internal 256k resistor once
the part is activated. SS pin voltages below ~0.8V reduce
the internal current limit. Thus, the gradual ramping of
the SS voltage also gradually increases the current limit
as the capacitor charges. This, in turn, allows the output
capacitor to charge gradually toward its final value while
limiting the start-up current. When the switching regulator shuts down, the soft-start capacitor is automatically
discharged to ~100mV or less before charging resumes,
thus assuring that the soft-start occurs after every reactivation of the switching regulation.
Power Supplies and Operating Limits
The LT8494 draws supply current from the VIN and BIAS
pins. The largest supply current draw occurs when the
switching regulator is enabled (SWEN is high) and the
power switch is toggling on and off. Under light load conditions the switching regulator enters Burst Mode operation
where the power switch toggles infrequently and the input
current is significantly reduced (see the Low Ripple Burst
Mode Operation section).
Power Switch Driver (PSD) Operating Range: The NPN
power switch is driven by a power switch driver (PSD) as
shown in the Block Diagram. The driver must be powered
by a supply (VIN or BIAS) that is above the minimum operating voltage and below the PSD overvoltage threshold.
These voltages are typically 2.4V and 34V respectively (see
Electrical Characteristics).
If neither VIN nor BIAS is within this operating range, the
PSD and the switching regulator are automatically disabled. Voltages up to 60V are not harmful to the PSD,
however, as discussed, switching regulation is automatically disabled when neither VIN nor BIAS is in the valid
operating range.
When both VIN and BIAS are too low for proper LT8494
operation (typically < 2.4V), the chip will enter shutdown
and draw minimal current from both supplies.
Automatic Power Supply Selection: In order to minimize
power loss, the LT8494 draws as much of its required current as possible from the lowest suitable voltage supply (VIN
or BIAS) in accordance with the requirements described
in the previous two sections. This selection is automatic
and can change as VIN and/or BIAS voltages change.
The LT8494 compares the VIN and BIAS voltages to determine which is lower. The comparator has an offset
and hysteresis as shown in the Electrical Characteristics
section. The voltage comparison happens continuously
when the power switch is toggling. The result of the latest
comparison is latched inside the LT8494 when switching
stops. If the power switch is not toggling, the LT8494 uses
the last VIN vs BIAS comparison to determine which supply is lower. After initial power up or any thermal lockout
the LT8494 always concludes that VIN is the lower supply
voltage until subsequent voltage comparisons can be made
while the power switch is toggling.
BIAS Connection for SEPIC Converters: For SEPIC converters, where VIN can be above or below VOUT, BIAS is
typically connected to VOUT which improves efficiency
when VIN voltage is higher than VOUT. Connecting BIAS
to VOUT in a SEPIC topology also allows the switching
regulator to operate with VIN above 34V (typical switch
driver overvoltage threshold) in cases where VOUT is
regulated below the PSD overvoltage threshold. Finally,
connecting BIAS to VOUT also allows the converter to
operate from VIN voltages less than 2.4V after VOUT rises
within the PSD operating range. This can be very useful
in battery powered applications since the battery voltage
drops as it discharges.
BIAS Connection for Boost Converters: For boost converters, BIAS is typically connected to VOUT or to ground.
Connecting BIAS to VOUT allows the converter to operate
with VIN < 2.5V after VOUT has risen within the PSD operating range. However, during no load conditions on VOUT,
despite VIN being selected as the primary input supply,
the overall power loss will be slightly elevated due to the
small amount of current still being drawn from the higher
voltage BIAS pin. To minimize boost converter power loss
during no load conditions, connect BIAS instead to ground.
8494f
14
For more information www.linear.com/LT8494
LT8494
APPLICATIONS INFORMATION
For boost applications with VOUT higher than the PSD operating range, the BIAS pin should not typically be connected
to VOUT. The LT8494 will never draw the majority of its
current from BIAS due to the excessive voltage, therefore
this connection does not help to improve efficiency. Alternative choices for the BIAS pin connection are ground
or another supply that is within the PSD operating range.
Maximum VIN for Boost Converters: VIN cannot generally
be higher than VOUT in boost topologies because of the DC
path from VIN to VOUT though the inductor and the output
diode. If VIN must be higher than VOUT, then the inductor
must be powered by a separate supply that is always below
VOUT. Otherwise a SEPIC topology can be used.
Also, the LT8494 will not operate in a boost topology
with VIN voltages above the PSD operating range unless
BIAS is connected to an alternative supply within the valid
operating range.
VIN/BIAS Ramp Rate: While initially powering a switching
converter application, the VIN/BIAS ramp rate should be
limited. High VIN/BIAS ramp rates can cause excessive
inrush currents in the passive components of the converter.
This can lead to current and/or voltage overstress and
may damage the passive components or the chip. Ramping rates less than 500mV/µs, depending on component
parameters, will generally prevent these issues. Also, be
careful to avoid hot-plugging. Hot-plugging occurs when
an active voltage supply is instantly connected or switched
to the input of the converter. Hot-plugging results in very
fast input ramp rates and is not recommended. Finally,
for more information, refer to Linear Application Note 88,
which discusses voltage overstress that can occur when
inductive source impedance is hot-plugged to an input
pin bypassed by ceramic capacitors.
Output Power Good
The power good circuits operate properly as long as either
VIN or BIAS is above 1.3V. When the LT8494’s output
voltage is above 92% of the regulation voltage, which
refers to the FB pin voltage being above 1.1V (typical), the
output voltage is considered good and the open-drain PG
pin becomes high impedance and is typically pulled high
with an external resistor. Otherwise, the internal pull-down
device will pull the PG pin low. To prevent glitches, the
power good function has around 46mV of hysteresis on
the FB pin.
As shown in Figure 2, the PG pin is also actively pulled low
during several fault conditions: The SWEN pin is below 1V,
thermal shutdown, or VIN and BIAS are both under 2.4V.
LT8494
FB
1.10V
–
+
PG
VIN AND BIAS UNDERVOLTAGE
OVER TEMPERATURE
SWEN
1.00V
–
+
8494 F02
Figure 2. Power Good Function
Enabling the Switching Regulator
The SWEN pin is used to enable or disable the switching regulator. The rising threshold of SWEN is typically
1V, with 30mV of hysteresis. The switching regulator is
disabled by driving the SWEN pin below this threshold
which deactivates the NPN power switch. The switching regulator is enabled by driving SWEN pin above its
threshold. Before active switching begins, the soft-start
capacitor will be quickly discharged then slowly charged
causing a gradual startup of the regulator. SWEN can
be connected to VIN if always on operation is desired,
although some current may flow into the SWEN pin (see
Typical Performance Characteristics) increasing overall
bias current of the system.
By connecting a resistor divider from VIN to SWEN (see
Figure 3), the LT8494 will be programmed to disable the
switching regulator when VIN drops below a desired threshold. Typically, this threshold is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
8494f
For more information www.linear.com/LT8494
15
LT8494
APPLICATIONS INFORMATION
LT8494
VIN
R4
1M
R3
487k
SWEN
1.00V
VC
–
+
2.1V
256k
SS
8494 F03
Figure 3. VIN Undervoltage Lockout
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current
limit or latch low under low source voltage conditions.
The input UVLO prevents the regulator from operating at
source voltages where the problems might occur.
As shown in Figure 3, by connecting a resistor divider
from the VIN pin to the SWEN pin, the falling undervoltage
lockout threshold is set to:
VIN(UVLO) =
R3+R4
• 0.97V
R3
From the previous equation, the resistor divider shown in
Figure 3 gives the VIN pin a falling undervoltage lockout
threshold of 2.96V. When VIN is below this threshold, the
switching regulation is disabled and the SS pin starts to
discharge. After choosing the value of R3, for example,
R4 can be calculated using:
 VIN(UVLO) 
R4 = R3 • 
– 1 Ω
 0.97

High Temperature Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT8494. The exposed pad on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread heat dissipated by the LT8494.
Placing additional vias can reduce thermal resistance
further. The maximum load current should be derated
as the ambient temperature approaches the maximum
junction rating. Power dissipation within the LT8494 is
estimated by calculating the total power loss from an
efficiency measurement and subtracting the diode loss,
FB resistor loss and inductor loss. The die temperature is
calculated by multiplying the LT8494 power dissipation by
the thermal resistance from junction to ambient.
The power switch and its driver dissipate the most power
in the LT8494 (see Block Diagram). Higher switch current, duty cycle and output voltage result in higher die
temperature. Power loss in the power switch driver also
increases with higher input supply voltage. The PSD is
supplied by the lowest suitable voltage on VIN and BIAS.
Connecting BIAS to a low voltage supply, often VOUT, can
reduce the maximum die temperature of the LT8494 (see
Automatic Power Supply Selection section).
Also note that leakage current into the SWEN and FB
pins increases at high junction temperatures (see Typical
Performance Characteristics). The potential leakage current
should be considered when choosing high value resistors
connected to those pins.
Thermal Lockout: If the die temperature reaches approximately 165°C, the part will go into thermal lockout and the
chip will be reset. The part will be enabled again when the
die temperature has dropped by ~5°C (nominal). During
thermal lockout, the PG pin is actively pulled low, see the
Output Power Good section for more details.
Fault Tolerance
The LT8494 is designed to tolerate single fault conditions
in the TSSOP package. Shorting two adjacent pins together
or leaving one single pin floating does not raise VOUT or
cause damage to the LT8494 regulator.
Table 3 and Table 4 show the effects that result from shorting adjacent pins and from a floating pin, respectively.
NC pins 4, 9, 17, and 19 must remain floating on the
PCB to ensure fault tolerance. NC pins 5 and 15 are not
connected to internal circuitry and can either be floated
or grounded on the PCB without effecting the fault tolerance. It is recommended that the remaining NC pins (6,
11 and 13) also remain floating on the PCB for best fault
tolerance. Table 3 assumes that all NC pins are floating.
For the best fault tolerance to inadvertent adjacent pin
shorts, the BIAS pin must be tied to something higher
than 1.230V or to the output to avoid overvoltage during
a short from FB to BIAS.
8494f
16
For more information www.linear.com/LT8494
LT8494
APPLICATIONS INFORMATION
Table 3. Effects of Pin Shorts (TSSOP)
PIN NAMES
PIN #
EFFECT ON OUTPUT
FB/BIAS
1/2
Output voltage will fall to approximately
1.202V if BIAS is connected to the output.
PG/SS
7/8
No effect or output will fall below regulation.
Table 4.Effects of Floating Pins (TSSOP)
PIN NAME
BIAS
PIN #
1
EFFECT ON OUTPUT
Depending on the VIN voltage and the circuit
topology, floating this pin will degrade device performance or the output will fall below
regulation.
FB
2, 3
No effect if the other FB pad is soldered.
PG
7
No effect on output.
SS
8
No effect after part has started. Can
potentially lead to an increase of inrush
current during start-up.
RT
10
Output may fall below regulation.
SWEN
12
Enable state of the pin becomes undefined.
Output will not exceed regulation voltage.
GND
14
No effect if Exposed Pad is soldered.
GND
16
No effect on output.
VIN
18
Depending on the BIAS voltage and the circuit
topology, floating this pin will degrade device
performance or the output will fall below
regulation.
SW
10
Output will fall below regulation voltage.
Exposed Pad
21
Output maintains regulation, but potential
degradation of device performance.
in Figures 4 and 5, must be kept as short as possible. This
is implemented in the suggested PCB layouts in Figures 6
and 7. Shortening this path will also reduce the parasitic
trace inductance. At switch-off, this parasitic inductance
produces a flyback spike across the LT8494 switch. When
operating at higher currents and output voltages, with poor
layout, this spike can generate voltages across the LT8494
that may exceed its absolute maximum rating. A ground
plane should also be used under the switcher circuitry
to prevent interplane coupling and overall noise. The FB
components should be kept as far away as practical from
the switch node. The ground for these components should
be separated from the switch current path. Failure to do
so can result in poor stability or subharmonic oscillation.
L1
D1
C1
VOUT
SW
VIN
LT8494
HIGH
FREQUENCY
SWITCHING
PATH
C2
LOAD
GND
8494 F04
Figure 4. High Speed Chopped Switching Path for Boost Topology
C2
L1
D1
VOUT
•
Layout Hints
SW
LT8494
VIN
C1
GND
HIGH
FREQUENCY
L2
SWITCHING
PATH
C3
LOAD
•
As with all high frequency switchers, when considering
layout, care must be taken to achieve optimal electrical,
thermal and noise performance. One will not get advertised performance with a careless layout. For maximum
efficiency, switch rise and fall times are typically in the
5ns to 10ns range. To prevent noise, both radiated and
conducted, the high speed switching current path, shown
8494 F05
Figure 5. High Speed Chopped Switching Path for
SEPIC Topology
8494f
For more information www.linear.com/LT8494
17
LT8494
APPLICATIONS INFORMATION
VOUT
C2
D1
SW
FB
1
20
2
19
3
18
4
17
5
C1
15
PG
7
14
SS
8
13
9
12
10
11
RT
VIN
16
21
6
L1
GND
SWEN
GND
VIAS TO GROUND PLANE
8494 F06
Figure 6. Suggested Component Placement for Boost Topology
Using TSSOP Package. Pin 21 (Exposed Pad) Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
D1
VOUT
C1
• •
C3
C2
FB
1
20 SW
2
19
3
18
4
17
5
6
21
L1
VIN
16
15
PG
7
14
SS
8
13
9
12
10
11
RT
L2
GND
SWEN
GND
VIAS TO GROUND PLANE
8494 F07
Figure 7. Suggested Component Placement for SEPIC Topology
Using TSSOP Package. Pin 21 (Exposed Pad) Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
8494f
18
For more information www.linear.com/LT8494
LT8494
TYPICAL APPLICATIONS
450kHz, 5V Output SEPIC Converter (Same as Front Page Application)
L1
15µH
•
D1
VOUT
5V
0.35A (VIN = 3V)
0.6A (VIN = 5V)
1.0A (VIN > 12V)
•
VIN
3V TO 60V
C3
2.2µF
L2
15µH
SW
VIN
SWEN
RT
SS
169k
4.7pF
1M
LT8494
PG
C1
4.7µF
BIAS
C2
47µF
×2
FB
GND
316k
1µF
8494 TA02c
C1: 4.7µF, 100V, X5R, 1206
C3: 2.2µF, 100V, X5R, 1206
C2: TAIYO YUDEN, EMK325BJ476MM-T
D1: ONSEMI MBRA2H100
L1, L2: COILTRONICS DRQ125-150-R
750kHz, 16V to 32V Input, 48V Output, 0.5A Boost Converter
VIN
16V TO 32V
L1
22µH
D1
1M
SW
VIN
SWEN
C1
2.2µF
PG
RT
93.1k
10pF
FB
25.5k
LT8494
C2
4.7µF
×2
GND BIAS
SS
VOUT
48V
0.5A
0.2µF
8494 TA02a
C1: 2.2µF, 50V, X5R, 1206
C2: 4.7µF, 100V, X7R, 1210
D1: ONSEMI MBRA2H100
L1: WÜRTH LHMI 74437349220
Transient Response with 400mA to
500mA to 400mA Output Load Step
Efficiency, VIN = 24V
Start-Up Waveforms
100
VOUT
0.5V/DIV
AC-COUPLED
EFFICIENCY (%)
95
90
VOUT
20V/DIV
VSS
0.5V/DIV
IL
0.5A/DIV
85
IL
0.5A/DIV
200µs/DIV
80
8494 TA02d
VIN = 24V
75
70
0
100
200
300
400
LOAD CURRENT (mA)
5ms/DIV
8494 TA02e
VIN = 24V
96Ω LOAD
500
8494 TA02b
8494f
For more information www.linear.com/LT8494
19
LT8494
TYPICAL APPLICATIONS
Wide Input and Output Range SEPIC Converter with Charge Pump Switches at 400kHz
D1
D2
C10
10µF
•
SW
SWEN
RT
D5
196k
C2
10µF
×2
OUTPUT
ADJUST
BIAS
LT8494
GND
SS
1M
D6
L2
22µH
VIN
C1
2.2µF
C3
3.3µF
•
VIN
6V TO 38V
(6V TO 32V FOR STARTUP)
R1
1.2Ω
C7
10µF
×2
C9
10µF
D7
VOUT
20V to 60V
80mA
D3
D4
L1
22µH
C8
10µF
×2
78.7k
FB
PG
26.7k
0.1V TO 3.2V
DAC
(SET DAC TO 3.2V FOR START-UP)
1µF
8494 TA03a
L1, L2: COILCRAFT MSD1260T-223ML
C1: 2.2µF, 50V, X5R, 1206
C2, C7-C10: TAIYO YUDEN GMK325C7106KMHT, 10µF 35V, X7S, 1210
C3: 3.3µF, 100V, X7R, 1210
D1-D4: FAIRCHILD 0540
D5-D7: ON-SEMI MBRA2H100
R1: 1.2Ω, 0.5W, SMD, 2010
8494f
20
For more information www.linear.com/LT8494
LT8494
TYPICAL APPLICATIONS
Li-Ion to 12V, Low Quiescent Current Boost at 650kHz
L1
6.8µH
Efficiency, VIN = 3.3V
D1
VOUT
12V
0.2A
1M
SW
VIN
SWEN
C1
4.7µF
PG
RT
113k
90
85
FB
110k
LT8494
C2
47µF
GND BIAS
SS
95
EFFICIENCY (%)
VIN
2.8V TO 4.1V
1µF
80
75
70
65
8494 TA04a
60
C1: 4.7µF, 6.3V, X7R, 1206
C2: 47µF, 16V, X5R, 1210
D1: ONSEMI MBRM120LT1G
L1: WÜRTH LHMI 74437346068
55
0.2
1
10
LOAD CURRENT (mA)
100 200
8494 TA04b
Low Quiescent Current, 5V to 300V, 250kHz Flyback Converter
DANGER HIGH VOLTAGE!
Operation by High Voltage Trained Personnel Only
T1
1:5
VIN
5V
D1
VOUT
300V
2mA
•
14.7µH
D2
•
1M
1M
1M
SW
VIN
SWEN
PG
C1
2.2µF
RT
324k
C2
22nF
FB
12.1k
LT8494
GND BIAS
SS
1µF
8494 TA05
*KEEP MAXIMUM OUTPUT POWER BELOW 0.6W
C1: 2.2µF, 25V, X5R, 1206
C2: TDK C3225CH2J223K
D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES
D2: ON SEMICONDUCTOR MBRA2H100
T1: WÜRTH-FLEX FLEXIBAL TRANSFORMER 749196121
Start-Up Waveforms
Switching Waveforms
VOUT
0.5V/DIV
IPRIMARY
0.5A/DIV
VOUT
50V/DIV
IPRIMARY
1A/DIV
5ms/DIV
2mA LOAD
8494 TA05b
2µs/DIV
8494 TA05c
2mA LOAD
8494f
For more information www.linear.com/LT8494
21
LT8494
TYPICAL APPLICATIONS
1.5MHz, 12V Output SEPIC Converter
Efficiency, VIN = 12V
D1
•
SWEN
PG
RT
41.2k
1M
LT8494
SS
C2
10µF
×2
BIAS
GND
900
75
70
600
POWER LOSS
65
300
60
FB
1µF
EFFICIENCY (%)
SW
VIN
EFFICIENCY
80
4.7pF
C1
2.2µF
85
110k
POWER LOSS (mW)
L2
4.7µH
1200
90
VOUT
12V
0.5A
•
VIN
9V TO 16V
C3
2.2µF
L1
4.7µH
55
8494 TA08a
50
0
C1, C3: 2.2µF, 50V, X5R, 1206
C2: TAIYO YUDEN TMK325BJ106MM
D1: DENTRAL SEMI CMMSH2-40
L1, L2: COILTRONICS DRQ74-4R7
100
200
300
400
LOAD CURRENT (mA)
0
500
8498 TA08b
8494f
22
For more information www.linear.com/LT8494
LT8494
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
4.00 ±0.10
0.70 ±0.05
R = 0.05
TYP
R = 0.115
TYP
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
4.50 ±0.05
1
3.10 ±0.05
2.00 REF
2.45 ±0.05
19 20
2.00 REF
4.00 ±0.10
2.45 ±0.05
2.45 ±0.10
2
2.45 ±0.10
PACKAGE
OUTLINE
(UF20) QFN 01-07 REV A
0.200 REF
0.25 ±0.05
0.50 BSC
0.00 – 0.05
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
:
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev J)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP REV J 1012
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
8494f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT8494
23
LT8494
TYPICAL APPLICATION
450kHz, Wide Input Range 12V Output SEPIC Converter
Efficiency
90
•
D1
VOUT
12V
0.2A (VIN = 3V)
0.35A (VIN = 5V)
0.65A (VIN > 12V)
L2
10µH
(VOUT RIPPLE
MAY INCREASE
BELOW 6V VIN)
VIN
SW
SWEN
PG
C1
2.2µF
RT
169k
BIAS
1M
LT8494
VIN = 24V
80
EFFICIENCY (%)
C3
2.2µF
•
VIN
3V TO 55V
L1
10µH
75
70
65
60
0.0
C2
10µF
×3
0.2
0.3
0.4
LOAD CURRENT (A)
0.5
0.6
8494 TA06b
100
110k
1µF
0.1
No Load Supply Current
GND FB
SS
VIN = 12V
VIN = 5V
85
8494 TA06a
80
SUPPLY CURRENT (µA)
C1, C3: 2.2µF, 100V, X5R, 1210
C2: 10µF, 25V, X5R, 1210
D1: ONSEMI MBRA2H100
L1, L2: COILTRONICS DRQ125-100-R
60
40
20
0
0
10
20
30
40
INPUT VOLTAGE (V)
50
60
8494 TA06c
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT8495
70V, 2A Boost/SEPIC 1.5MHz High Efficiency DC/DC Converter with VIN: 2.5V to 32V, VOUT(MAX) = 70V, IQ = 9µA, ISD < 1µA,
POR and Watchdog Timer
4mm × 4mm QFN20, TSSOP-20E Packages
LT3580
42V, 2A Boost/Inverting 2.5MHz High Efficiency DC/DC Converter
VIN: 2.5V to 32V, VOUT(MAX) = ±40V, IQ = 1mA, ISD < 1µA,
3mm × 3mm DFN-8, MSOP-8E Packages
LT8580
65V, 1A Boost/Inverting DC/DC Converter
VIN: 2.55V to 40V, VOUT(MAX) = ±60V, IQ = 1.2mA, ISD < 1µA,
3mm × 3mm DFN-8, MSOP-8E Packages
LT8570/
LT8570-1
65V, 500mA/250mA Boost/Inverting DC/DC Converter
VIN: 2.55V to 40V, VOUT(MAX) = ±60V, IQ = 1.2mA, ISD < 1µA,
3mm × 3mm DFN-8, MSOP-8E Packages
LT8582
40V, Dual 3A, 2.5MHz High Efficiency Boost Converter
VIN: 2.5V to 40V, VOUT(MAX) = ±40V, IQ = 2.8mA, ISD < 1µA,
7mm × 4mm DFN-24 Package
LT8471
40V, Dual 3A, Multitopology High Efficiency DC/DC Converter
VIN: 2.6V to 50V, VOUT(MAX) = ±45V, IQ = 2.4mA, ISD < 1µA,
TSSOP-20E Package
LT3581
40V, 3.3A, 2.5MHz High Efficiency Boost Converter
VIN: 2.5V to 40V, VOUT(MAX) = ±40V, IQ = 1mA, ISD < 1µA,
4mm × 3mm DFN-14, MSOP-16E Packages
LT8582
40V, Dual 3A Boost, Inverter, SEPIC, 2.5MHz High Efficiency Boost VIN: 2.5V to 40V, VOUT(MAX) = ±40V, IQ = 2.1mA, ISD < 1µA,
Converter
7mm × 4mm DFN-24 Package
LT3579/
LT3579-1
40V, 3.3A Boost, Inverter, SEPIC, 2.5MHz High Efficiency Boost
Converter
VIN: 2.5V to 40V, VOUT(MAX) = ±40V, IQ = 1mA, ISD < 1µA,
4mm × 5mm QFN-20, TSSOP-20E Packages
8494f
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LT8494
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LT8494
LT 0715 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015