DICE/DWF SPECIFICATION LTC6269 500MHz Ultra-Low Bias Current FET Input Op Amp 1 2 3 4 PAD FUNCTION 5 6 9 8 7 12 11 10 13 14 15 18 17 1. 2. 3. 4. 5. 6. 7. 8. 9. V–A +INA –INA SHDNA V+A V+A OUTA V–A SHDNA 10. 11. 12. 13. 14. 15. 16. 17. 18. V–B +INB –INB SHDNB V+B V+B OUTB V–B SHDNB 50mils × 58mils, 28mils thick. Backside metal: None Backside potential: V– DIE CROSS REFERENCE LTC® Finished Part Number LTC®6269 Order Part Number LTC6269 DICE/DWF Please refer to LTC standard product data sheet for other applicable product information. *DWF = DICE in wafer form. Pins 1 and 8 are connected internally Pins 5 and 6 are connected internally Pins 4 and 9 are connected internally Pins 10 and 17 are connected internally Pins 14 and 15 are connected internally Pins 13 and 18 are connected internally L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 16 Absolute Maximum Ratings (Note 1) Supply Voltage V+ to V–............................................5.5V Input Voltage ................................V– – 0.2V to V+ + 0.2V Input Current (+IN, –IN) (Note 2)............................±1mA Dice/DWF Electrical Test Limits VCM = mid-supply), RL = 1kΩ, CL = 10pF, VSHDN is unconnected. SYMBOL PARAMETER Input Offset Voltage VOS IB Input Bias Current (Notes 3, 4) IOS CMRR Input Offset Current (Notes 3, 4) Common Mode Rejection Ratio IVR PSRR Input Voltage Range Power Supply Rejection Ratio Supply Voltage Range Input Current (SHDN).............................................±1mA Output Current (IOUT) (Notes 4, 5)........................135mA Specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V– = 0V, CONDITIONS VCM = 2.75V VCM = 4.0V VCM = 2.75V VCM = 4.0V VCM = 2.75V VCM = 0.5V to 3.2V (PNP Side) VCM = 0V to 4.5V Guaranteed by CMRR VCM = 1.0V, VSUPPLY Ranges from 3.1V to 5.25V Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. MIN –0.7 –1.0 –20 –20 –40 72 64 0 78 3.1 MAX 0.7 1.0 20 20 40 4.5 UNITS mV mV fA fA fA dB dB V dB 5.25 1 DICE/DWF SPECIFICATION LTC6269 Dice/DWF Electrical Test Limits VCM = mid-supply), RL = 1kΩ, CL = 10pF, VSHDN is unconnected. SYMBOL PARAMETER Open Loop Voltage Gain AV ISHDN Output Short Circuit Current (Note 5) Supply Current Per Amplifier Supply Current in Shutdown (Per Amplifier) Shutdown Pin Current VIL VIH ILEAK SHDN Input Low Voltage SHDN Input High Voltage Output Leakage Current in Shutdown ISC IS CONDITIONS VOUT = 0.5V to 4.5V VCM = mid-supply), RL = 1kΩ, CL = 10pF, VSHDN is unconnected. SYMBOL PARAMETER Input Offset Voltage VOS Input Bias Current (Notes 3, 4) IOS CMRR Input Offset Current (Notes 3, 4) Common Mode Rejection Ratio IVR AV Input Voltage Range Open Loop Voltage Gain ISC IS ISHDN Output Short Circuit Current (Note 5) Supply Current per Amplifier Supply Current in Shutdown (Per Amplifier) Shutdown Pin Current VIL VIH SHDN Input Low Voltage SHDN Input High Voltage RLOAD = 10k RLOAD = 100 VSHDN = 0.75V VSHDN =1.50V Disable Enable. If SHDN is Unconnected, Amp is Enabled VSHDN = 0V, VOUT = 0V VSHDN = 0V, VOUT = 5V Dice/DWF Electrical Test Limits IB Specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V– = 0V, MAX –12 –12 12 12 0.75 18 0.85 1.5 400 400 UNITS V/mV V/mV mA mA mA µA µA V V nA nA Specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V– = 0V, CONDITIONS VCM = 1.0V VCM = 2.3V VCM = 1.0V VCM = 2.3V VCM = 1.0V VCM = 0.5V to 1.2V (PNP Side) VCM = 0V to 2.8V (Full Range) Guaranteed by CMRR VOUT = 0.5V to 2.8V RLOAD = 10k RLOAD = 100 VSHDN = 0.75V VSHDN = 1.5V Disable Enable. If SHDN is Unconnected, Amp Is Enabled Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The inputs are protected by two series connected ESD protection diodes to each power supply. The input current should be limited to less than 1mA. The input voltage should not exceed 200mV beyond the power supply. MIN 125 10 60 15 MIN –0.7 –1.0 –20 –20 –40 63 60 0 80 10 50 14.5 MAX 0.7 1.0 20 20 40 –12 –12 12 12 0.75 1.5 2.8 17.5 0.6 UNITS mV mV fA fA fA dB dB V V/mV V/mV mA mA mA µA µA V V Note 3: The input bias current is the average of the currents into the positive and negative input pins. Note 4: This parameter is specified by design and/or characterization and is not tested in production. Note 5: The LTC6269 is capable of producing peak output currents in excess of 135mA. Current density limitations within the IC require the continuous current supplied by the output (sourcing or sinking) over the operating lifetime of the part be limited to under 135mA (Absolute Maximum). Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information on dice performance and lot qualifications via lot sampling test procedures. Dice data sheet subject to change. Please consult factory for current revision in production. 2 I.D.No. 16-33-6269 Linear Technology Corporation LT 0715 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2015