DICE/DWF SPECIFICATION 1 1 RH1016 UltraFast™ Precision 10ns Comparator 8 PAD FUNCTION 1 1 7 2 6 3 4 1. 2. 3. 4. 5. 6. 7. 8. V+ +IN –IN V– LATCH ENABLE GND Q OUT Q OUT DIE CROSS REFERENCE LTC Finished Part Number Order Part Number RH1016M RH1016M RH1016 DICE RH1016 DWF* *DWF = DICE in wafer form. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. 5 56mils × 58mils Backside Connection is V– DICE ELECTRICAL TEST LIMITS + – TA = 25°C. V = 5V, V = –5V, VOUT(Q) = 1.4V, VLATCH = 0V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage RS ≤ 100Ω (Note 1) ±3 mV IOS Input Offset Current (Note 1) 1 μA IB Input Bias Current (Note 2) 10 μA Input Voltage Range (Note 3) Single 5V Supply (Note 3) 3.5 3.5 V V Common Mode Rejection –3.75V ≤ VCM ≤ 3.5V 80 dB PSRR Supply Voltage Rejection Positive Supply 4.6V ≤ V+ ≤5.4V Negative Supply –7V ≤ V– ≤ –2V 60 80 dB dB AV Small-Signal Voltage Gain 1V ≤ VOUT ≤ 2V 1400 V/V VOH Output High Voltage V+ ≥ 4.6V, IOUT = 1mA IOUT = 10mA 2.80 2.60 V V VOL Output Low Voltage ISINK = 4mA 0.5 V I+ Positive Supply Current 35 mA I– Negative Supply Current 5 mA CMRR VIH Latch Pin High Input Voltage VIL Latch Pin Low Input Voltage IIL Latch Pin Current MIN –3.75 1.25 MAX UNITS 2.0 VLATCH = 0V Note 1: Input offset voltage is defined as the average of the two voltages measured by forcing first one output, then the other to 1.4V. Input offset current is defined in the same way. Note 2: Input bias current (IB) is defined as the average of the two input currents. V 0.8 V 500 μA Note 3: Input voltage range is guaranteed in part by CMRR testing and in part by design and characterization. See the LT1016 data sheet for discussion of input voltage range for supplies other than ±5V or 5V. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 DICE/DWF SPECIFICATION RH1016 Rad Hard die require special handling as compared to standard IC chips. Rad Hard die are susceptible to surface damage because there is no silicon nitride passivation as on standard die. Silicon nitride protects the die surface from scratches by its hard and dense properties. The passivation on Rad Hard die is silicon dioxide that is much “softer” than silicon nitride. LTC recommends that die handling be performed with extreme care so as to protect the die surface from scratches. If the need arises to move the die around from the chip tray, use a Teflon-tipped vacuum wand. This wand can be made by pushing a small diameter Teflon tubing onto the tip of a steel-tipped wand. The inside diameter of the Teflon tip should match the die size for efficient pickup. The tip of the Teflon should be cut square and flat to ensure good vacuum to die surface. Ensure the Teflon tip remains clean from debris by inspecting under stereoscope. During die attach, care must be exercised to ensure no tweezers touch the top of the die. Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information on dice performance and lot qualifications via lot sampling test procedures. Dice data sheet subject to change. Please consult factory for current revision in production. I.D.No. 66-13-1016 2 Linear Technology Corporation LT 1008 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008