LTC4233 - 10A Guaranteed SOA Hot Swap Controller

LTC4233
10A Guaranteed SOA
Hot Swap Controller
FEATURES
DESCRIPTION
Allows Safe Board Insertion into a Live Backplane
nn Small Footprint
nn 10mΩ MOSFET Including R
SENSE
nn Safe Operating Area Guaranteed at 41W, 30ms
nn Wide Operating Voltage Range: 2.9V to 15V
nn Adjustable, 11% Accurate Current Limit
nn Current and Temperature Monitor Outputs
nn Overtemperature Protection
nn Adjustable Current Limit Timer Before Fault
nn Power Good and Fault Outputs
nn Adjustable Inrush Current Control
nn 2.5% Accurate Undervoltage and Overvoltage
Protection
nn Available in 38-Lead (5mm × 9mm) QFN Package
nn Pin Compatible with LTC4234
The LTC®4233 is an integrated solution for Hot Swap™
applications that allows a board to be safely inserted and
removed from a live backplane. The part integrates a Hot
Swap controller, power MOSFET and current sense resistor in a single package for small form factor applications.
The MOSFET Safe Operating Area is production tested
and guaranteed for the stresses in Hot Swap applications.
nn
The LTC4233 provides separate inrush current control
and an 11% accurate 11.2A current limit with output
dependent foldback. The current limit threshold can be
adjusted dynamically using the ISET pin. Additional features
include a current monitor output that amplifies the sense
resistor voltage for ground referenced current sensing
and a MOSFET temperature monitor output. Thermal limit,
overvoltage, undervoltage and power good monitoring
are also provided. For a 20A pin compatible version see
LTC4234.
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot
Swap and PowerPath are trademarks of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
High Availability Servers
nn Solid State Drives
nn Industrial
nn Network Routers and Switches
nn
TYPICAL APPLICATION
12V, 10A Card Resident Application with Auto-Retry
12V
150k
LTC4233
107k
UV
FB
FLT
SENSE–
GATE
TIMER
ISET
IMON
GND
VIN
10V/DIV
CONTACT
BOUNCE
IIN
0.2A/DIV
VOUT
10V/DIV
PG
SENSE
INTVCC
*TVS: DIODES INC. SMAJ17A
680µF
10k
OV
1µF
+
20k
5.23k
10k
VOUT
12V
10A
OUT
VDD
*
Power-Up Waveforms
ADC
PG
10V/DIV
20k
20ms/DIV
4233 TA01b
4233 TA01a
4233f
For more information www.linear.com/LTC4233
1
LTC4233
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
UV
1
38
ISET
OV
2
37
FB
IMON
3
36
FLT
TIMER
4
35
PG
INTVCC
5
34
SENSE–
VDD (DNC)
6
33
VDD (DNC)
GND
7
32
GATE
SENSE (DNC)
8
31
SENSE
OUT
9
30
OUT
OUT
10
29
OUT
28
OUT
27
OUT
39
VDD
40
SENSE
24
OUT
OUT
16
23
OUT
22
15
21
OUT
OUT
OUT
25
20
14
OUT
OUT
OUT
OUT
26
19
13
18
OUT
OUT
12
17
11
OUT
OUT
OUT
OUT
Supply Voltage (VDD).................................. –0.3V to 28V
Input Voltages
FB, OV, UV...............................................–0.3V to 12V
TIMER.................................................... –0.3V to 3.5V
SENSE–, SENSE......VDD − 10V or –0.3V to VDD + 0.3V
Output Voltages
ISET, IMON.................................................. –0.3V to 3V
PG, FLT .................................................. –0.3V to 35V
OUT............................................. –0.3V to VDD + 0.3V
INTVCC................................................... –0.3V to 3.5V
GATE (Note 3)......................................... –0.3V to 33V
Operating Ambient Temperature Range
LTC4234C................................................. 0°C to 70°C
LTC4234I..............................................–40°C to 85°C
LTC4234H........................................... –40°C to 125°C
Junction Temperature (Note 4, 5).......................... 150°C
Storage Temperature Range................... –65°C to 150°C
WHH PACKAGE
38-LEAD PLASTIC QFN (5mm × 9mm)
TJMAX = 150°C, θJA = 15°C/W
EXPOSED PAD (PINS 39 AND 40) ARE VDD AND SENSE,
θJA = 15°C/W SOLDERED, OTHERWISE θJA = 50°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4233CWHH#PBF
LTC4233CWHH#TRPBF
4233
38-Lead (5mm × 9mm) Plastic QFN
0°C to 70°C
LTC4233IWHH#PBF
LTC4233IWHH#TRPBF
4233
38-Lead (5mm × 9mm) Plastic QFN
–40°C to 85°C
LTC4233HWHH#PBF
LTC4233HWHH#TRPBF
4233
38-Lead (5mm × 9mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4233f
2
For more information www.linear.com/LTC4233
LTC4233
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Characteristics
VDD
Input Supply Range
IDD
Input Supply Current
MOSFET On, No Load
l
15
V
VDD(UVL)
Input Supply Undervoltage Lockout
VDD Rising
l
2.63
1.6
3
mA
2.73
2.85
V
IOUT
OUT Leakage Current
VOUT = VGATE = 0V, VDD = 15V
VOUT = VGATE = 12V
l
l
1
0
2
±300
4
µA
µA
dVGATE /dt
OUT Turn-on Ramp Rate
Gate Open
l
0.15
0.3
0.6
V/ms
RON
MOSFET + Sense Resistor
On-Resistance
C-Grade, I-Grade
H-Grade
l
l
4.5
4.5
10
10
14.5
16.5
mΩ
mΩ
ILIM(TH)
Current Limit Threshold
VFB = 1.35V, ISET Open
VFB = 0V, ISET Open
VFB = 1.35V, RSET = 20k
l
l
l
10
2.0
4.7
11.2
2.8
5.6
12.4
3.7
6.4
A
A
A
SOA
MOSFET Safe Operating Area
VDS = 13.5V, 3A Folded Back, 50W2s (Note 6)
VDS = 7.5V, 11A Onset of Foldback, 50W2s (Note 7)
IIN
OV, UV, FB Input Current
V = 1.2V
ISENSE−(IN)
SENSE− Input Current
VSENSE
l
VTH
OV, UV, FB Threshold Voltage
VPIN Rising
l
1.205
ΔVOV(HYST)
OV Hysteresis
l
10
20
30
mV
ΔVUV(HYST)
UV Hysteresis
VUV(RTH)
UV Reset Threshold Voltage
ΔVFB(HYST)
RISET
l
2.9
30
7
ms
ms
Inputs
– = 12V
0
l
±1
µA
4
±10
µA
1.235
1.265
V
l
50
80
110
mV
l
0.55
0.62
0.7
V
FB Power Good Hysteresis
l
10
20
30
mV
ISET Internal Resistor
l
19
20
21
kΩ
2.8
VUV Falling
Outputs
VINTVCC
INTVCC Output Voltage
VDD = 5V,15V, ISINK = 0mA, –10mA
l
3.1
3.3
VOL
PG, FLT Pin Output Low Voltage
ISINK = 2mA
l
0.4
0.8
V
IOH
PG , FLT Pin Input Leakage Current
V = 30V
l
0
±10
µA
VTIMER(H)
TIMER High Threshold
VTIMER Rising
l
1.2
1.235
1.28
V
VTIMER(L)
TIMER Low Threshold
VTIMER falling
l
0.1
0.21
0.3
V
ITIMER(UP)
TIMER Pull Up Current
VTIMER = 0V
l
–80
–100
–120
µA
ITIMER(DN)
TIMER Pull Down Current
VTIMER = 1.2V
l
1.4
2
2.6
µA
ITIMER(RATIO)
TIMER Current Ratio
ITIMER(DN)/ITIMER(UP)
l
1.6
2
2.7
%
AIMON
IMON Current Gain
l
9
10
10.5
µA/A
BWIMON
IMON Bandwidth
250
kHz
IOFF(IMON)
IMON Offset Current
IOUT = 300mA
l
0
±9
µA
IGATE(UP)
Gate Pull-Up Current
Gate Drive On, VGATE = VOUT = 12V
l
–18
–24
–29
µA
IGATE(DN)
Gate Pull-Down Current
Gate Drive Off, VGATE = 18V, VOUT = 12V
l
180
250
500
µA
IGATE(FST)
Gate Fast Pull-Down Current
Fast Turn Off, VGATE = 18V, VOUT = 12V
140
mA
4233f
For more information www.linear.com/LTC4233
3
LTC4233
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
8
20
µs
l
1
5
µs
72
ms
AC Characteristics
tPHL(GATE)
Input High (OV), Input Low (UV) to
GATE Low Propagation Delay
VGATE < 17.8V Falling
tPHL(ILIM)
Short Circuit to GATE Low
VFB = 0, Step VDD − SENSE− to 50mV,
VGATE < 15V Falling
tD(ON)
Turn-On Delay
Step VUV to 2V, VGATE > 13V
l
24
48
tD(FAULT)
UV Low to Clear Fault Latch Delay
tD(CB)
Circuit Breaker Filter Delay Time
(Internal)
VFB = 0, Step VDD − SENSE– to 50mV
l
1.2
2
2.7
ms
tD(COOL-DOWN)
Cool Down Delay (Internal)
l
600
900
1200
ms
1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V
above OUT. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
µs
Note 5: TJ is calculated from the ambient temperature, TA, and power
dissipation, PD, according to the formula:
TJ = TA + (PD • 15°C/W)
Note 6: SOA tested at room temperature, SOA (i.e. P2t) is reduced at
elevated temperatures according to the following formula:
 150°C − TJ 
P 2 t(TJ ) = 50 W 2s • 

 150°C − 25°C 
2
Note 7: Guaranteed by design and extrapolated from P2t limit of 50W2s.
4233f
4
For more information www.linear.com/LTC4233
LTC4233
TYPICAL PERFORMANCE CHARACTERISTICS
IDD vs VDD
TA = 25°C, VDD = 12V unless otherwise noted.
UV Low-High Threshold
vs Temperature
INTVCC Load Regulation
2.2
3.5
1.240
3.0
125°C
2.5
1.8
INTVCC (V)
IDD (mA)
25°C
–40°C
1.4
UV LOW-HIGH THRESHOLD (V)
VDD = 5V
VDD = 3.3V
2.0
1.5
1.0
0.5
0
5
10
15
VDD (V)
20
25
0
30
–2
–4
4233 G01
–6
–8
ILOAD (mA)
–10
0.08
0.06
0.04
–50 –25
0
–95
–90
–50 –25
0
10
10
4
0.2
0.4
0.6
0.8
FB VOLTAGE (V)
0
10
40
20
30
OUTPUT CURRENT (A)
50
60
4233 G06
RISET Resistor vs Temperature
22
8
6
4
21
20
19
2
>30ms SOA GUARANTEED
0
1
0.1
25 50 75 100 125 150
TEMPERATURE (°C)
ISET RESISTOR (kΩ)
12
6
10
Current Limit Adjustment
(IOUT vs RSET)
12
8
100
4233 G05
CURRENT LIMIT VALUE (A)
CURRENT LIMIT VALUE (A)
4233 G03
1000
–100
Current Limit Threshold Foldback
25 50 75 100 125 150
TEMPERATURE (°C)
Current Limit Delay
(tPHL(ILIM) vs Overdrive)
–105
25 50 75 100 125 150
TEMPERATURE (°C)
0
4233 G02
4233 G04
2
1.228
1.224
–50 –25
–14
–110
TIMER PULL-UP CURRENT (µA)
0.10
0
–12
1.232
Timer Pull-Up Current
vs Temperature
UV Hysteresis vs Temperature
UV HYSTERESIS (V)
0
CURRENT PROPAGATION DELAY (µs)
1.0
1.236
1
1.2
4233 G07
0
1k
10k
100k
RSET (Ω)
1M
10M
4233 G08
18
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
4233 G09
4233f
For more information www.linear.com/LTC4233
5
LTC4233
TYPICAL PERFORMANCE CHARACTERISTICS
SOA Constant vs Junction
Temperature
RON vs Temperature
16
Guaranteed MOSFET SOA Curve
1.0
VDD = 3.3V TO 12V
100
0.8
NORMALIZED P2t
12
8
10
0.6
0.4
0.2
0
–50 –25
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
25
50
75
100
125
JUNCTION TEMPERATURE (°C)
4233 G10
150
–24.5
IGATE PULL-UP (µA)
IMON (µA)
PG, FLT VOL (V)
95
90
4
85
2
VDD = 3.3V, 12V
ILOAD = 10A
0
2
4
6
8
CURRENT (mA)
10
80
–50 –25
12
0
25 50 75 100 125 150
TEMPERATURE (°C)
4233 G12
4
VDD = 3.3V
2
1
–5
–10
–15
–20
IGATE (µA)
–25
–30
4233 G15
0
25 50 75 100 125 150
TEMPERATURE (°C)
4233 G14
VISET vs Temperature
0.9
0.8
6.0
0.7
5.8
VISET (V)
∆VGATE (VGATE – VOUT) (V)
5
0
–23.0
–50 –25
6.2
VDD = 12V
3
–23.5
Gate Drive vs VDD
7
6
–24.0
4233 G13
Gate Drive vs Gate Pull-Up
Current
5.6
0.6
0.5
5.4
5.2
4233 G12
–25.0
100
6
100
GATE Pull-Up Current
vs Temperature
10
8
10
VDS (V)
105
12
DC
1
0.1
IMON vs Temperature
14
∆VGATE (VGATE – VOUT) (V)
0.1
TA = 25°C
SINGLE PULSE
4233 G11
PG, FLT Output Low vs ISINK
0
30ms
1
4
0
3ms
>30ms SOA
GUARANTEED
ID (A)
RON (mΩ)
TA = 25°C, VDD = 12V unless otherwise noted.
0.4
0
5
10
15
VDD (V)
20
25
30
4233 G16
0.3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
4233 G18
4233f
6
For more information www.linear.com/LTC4233
LTC4233
PIN FUNCTIONS
DNC: Do Not Connect. Leave open.
FB: Foldback and Power Good Input. Connect this pin to
an external resistive divider from OUT. If the voltage falls
below 0.6V, the current limit is reduced using a foldback
profile (see the Typical Performance Characteristics section). If the voltage falls below 1.21V, the PG pin will pull
low to indicate the power is bad
FLT: Overcurrent fault indicator. Open-drain output pulls
low when an overcurrent fault has occurred and the circuit
breaker trips. For overcurrent auto-retry tie to UV pin (see
Applications Information section for details).
GATE: Gate Drive for internal N-Channel MOSFET. An
internal 24µA current source charges the gate of the
N-channel MOSFET. At start-up the GATE pin ramps up at
a 0.35V/ms rate determined by internal circuitry. During an
undervoltage or overvoltage condition a 250µA pull-down
current turns the MOSFET off. During a short circuit or
undervoltage lockout condition, a 140mA pull-down current source between GATE and OUT is activated.
GND: Device Ground.
IMON: Current Monitor Output. The current in the internal
MOSFET switch is divided by 100,000 and sourced from
this pin. Placing a 20k resistor on this pin allows a 0 to
2V voltage swing when current ranges from 0A to 10A.
INTVCC: Internal 3.1V Supply Decoupling Output. This pin
must have a 1µF or larger bypass capacitor. Overloading
this pin can disrupt internal operation.
ISET: Current Limit Adjustment Pin. For 11.2A current limit
value open this pin. This pin is driven by a 20k resistor
in series with a voltage source. The pin voltage is used
to generate the current limit threshold. The internal 20k
resistor (RISET) and an external resistor (RSET) between
ISET and ground create an attenuator that lowers the
current limit value. Due to circuit tolerance RSET should
not be less than 2k. In order to match the temperature
variation of the sense resistor, the voltage on this pin is
made proportional to temperature of the MOSFET switch.
OUT: Output of internal MOSFET switch. Connect this pin
directly to the load.
OV: Overvoltage Comparator Input. Connect this pin to an
external resistive divider from VDD. If the voltage at this
pin rises above 1.235V, an overvoltage is detected and
the switch turns off. Tie to GND if unused.
PG: Power good indicator. Open drain output pulls low
when the FB pin drops below 1.21V indicating the power is
bad. If the voltage at FB rises above 1.235V and the GATE
to OUT voltage exceeds 4.2V, the open-drain pull-down
releases the PG pin to go high.
SENSE: Current Sense Node and MOSFET Drain. One
exposed pad on the UH package is connected to SENSE
and should be soldered to an electrically isolated printed
circuit board trace to properly transfer the heat out of the
package. Connect the SENSE Pin 31 to the SENSE– Pin 34.
SENSE–: Current Limit and Current Monitor Amplifier
Input. The current limit circuit controls the GATE pin to
limit the voltage between the VDD and SENSE– pins to
15mV (11.2A) or less depending on the voltage at the FB
pin. This pin must be connected to SENSE pin on the right
side (connect pin 34 to pin 31).
TIMER: Current Limit Timer Input. Connect a capacitor
between this pin and ground to set a 12 ms/µF duration
for current limit before the switch is turned off. If the UV
pin is toggled low while the MOSFET switch is off, the
switch will turn on again following cool-down time of
4.14s/µF duration. Tie this pin to INTVCC for a fixed 2ms
overcurrent delay and 900ms cool-down time.
UV: Undervoltage Comparator Input. Tie high to INTVCC
if unused. Connect this pin to an external resistive divider
from VDD. If the UV pin voltage falls below 1.15V, an undervoltage is detected and the switch turns off. Pulling this
pin below 0.62V resets the overcurrent fault and allows
the switch to turn back on (see Application Information
section for details). If overcurrent auto-retry is desired
then tie this pin to the FLT pin.
VDD: Supply Voltage and Current Sense Input. This exposed pad must be soldered to input power. VDD has an
undervoltage lockout threshold of 2.73V.
4233f
For more information www.linear.com/LTC4233
7
LTC4233
FUNCTIONAL BLOCK DIAGRAM
SENSE
(EXPOSED PAD)
VDD
(EXPOSED PAD)
1.4mΩ SENSE
RESISTOR
GATE
6.1V
8.6mΩ
MOSFET
OUT
IMON
SENSE–
–
CS
+–
CLAMP
CHARGE
PUMP
AND GATE
DRIVER
f = 2MHz
+
INRUSH
0.6V POSITIVE
TEMPERATURE
COEFFICIENT
REFERENCE
0.35V/ms
ISET
RISET
20k
X1
FB
CM
FOLDBACK
0.6V
+
+
1.235V
UV
PG
–
–
UV
LOGIC
1.235V
PG
0.62V
+
RST
–
0.21V
FLT
+
INTVCC
TM1
OV
–
+
100µA
OV
1.235V
–
2µA
+
VDD
TM2
VDD
–
1.235V
–
+
–
2.73V
INTVCC
3.1V
GEN
UVLO1
TIMER
UVLO2
2.65V
+
GND
4233 BD
4233f
8
For more information www.linear.com/LTC4233
LTC4233
OPERATION
The Functional Block Diagram displays the main circuits
of the device. The LTC4233 is designed to turn a board’s
supply voltage on and off in a controlled manner allowing
the board to be safely inserted and removed from a live
backplane. The LTC4233 includes a 8.6mΩ MOSFET and
a 1.4mΩ current sense resistor. During normal operation, the charge pump and gate driver turn on the pass
MOSFET’s gate to provide power to the load. The inrush
current control is accomplished by the INRUSH circuit. This
circuit limits the GATE ramp rate to 0.35V/ms and hence
controls the voltage ramp rate of the output capacitor.
0.21V (Comparator TM1) which completes one timer cycle.
After eight TIMER pin cycles (ramping to 1.235V and then
below 0.21V) the logic starts the internal 48ms timer. At
this point, the pass transistor has cooled and it is safe
to turn it on again. It is suitable in many applications to
use an internal 2ms overcurrent timer with a 900ms cool
down period. Tying the TIMER pin to INTVCC sets this
default timing. Latchoff is the normal operating condition
following overcurrent turnoff. Retry is initiated by pulling
the UV pin low for a minimum of 1µs then high. Auto-retry
is implemented by tying the FLT to the UV pin.
The current sense (CS) amplifier monitors the load current
using the voltage sensed across the current sense resistor.
The CS amplifier limits the current in the load by reducing the GATE-to-OUT voltage in an active control loop. It
is simple to adjust the current limit threshold using the
current limit adjustment (ISET) pin. This allows a different
threshold during other times such as startup. Note there
must be a connection between SENSE to SENSE− (Pin 34
to Pin 31) in order to monitor current.
The output voltage is monitored using the FB pin and the
PG comparator to determine if the power is available for
the load. The power good condition is signaled by the PG
pin using an open-drain pull-down transistor.
A short circuit on the output to ground causes significant
power dissipation during active current limiting. To limit
this power, the foldback amplifier reduces the current
limit value from 11.2A to 2.8A in a linear manner as the
FB pin drops below 0.6V (see the Typical Performance
Characteristics).
If an overcurrent condition persists, the TIMER pin ramps
up with a 100µA current source until the pin voltage
exceeds 1.235V (comparator TM2). This indicates to the
logic that it is time to turn off the pass MOSFET to prevent
overheating. At this point the TIMER pin ramps down using the 2µA current source until the voltage drops below
The Functional Block Diagram shows the monitoring blocks
of the LTC4233. The two comparators on the left side
include the UV and OV comparators. These comparators
are used to determine if the external conditions are valid
prior to turning on the MOSFET. But first the undervoltage lockout circuits UVLO1 and UVLO2 must validate the
input supply and the internally generated 3.1V supply
(INTVCC) and generate the power up initialization to the
logic circuits. If the external conditions remain valid for
48ms the MOSFET is allowed to turn on.
Other monitoring features include MOSFET current and
temperature monitoring. The current monitor (CM) outputs
a current proportional to the sense resistor current. This
current can drive an external resistor or other circuits for
monitoring purposes. A voltage proportional to the MOSFET temperature is output to the ISET pin. The MOSFET is
protected by a thermal shutdown circuit.
4233f
For more information www.linear.com/LTC4233
9
LTC4233
APPLICATIONS INFORMATION
12V
VDD
R3
140k
CCOMP
3.3nF
Z1*
LTC4233
UV
R1
226k
R2
20k
OUT
FB
GATE
FLT
OV
R4
20k
RGATE
100k
CGATE
0.1µF
R5
150k
VOUT
12V
5A
+
CL
330µF
R6
20k
UV = 9.88V
OV = 15.2V
PG = 10.5V
R7
10k
PG
SENSE–
ISET
SENSE
RSET
20k
TIMER
CT
0.1µF
C1
1µF
INTVCC
ADC
IMON
RMON
20k
GND
4233 F01
*TVS Z1: DIODES INC. SMAJ17A
Figure 1. 5A, 12V Card Resident Application
The typical LTC4233 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. The complete application circuit
is shown in Figure 1. External component selection is
discussed in detail in the following sections.
VDD + 6.15V
GATE
SLOPE = 0.35[V/ms]
VDD
OUT
Turn-On Sequence
Several conditions must be present before the internal
pass MOSFET can be turned on. First the supply VDD must
exceed its undervoltage lockout level. Next the internally
generated supply INTVCC must cross its 2.65V undervoltage threshold. This generates a 25µs power-on-reset pulse
which clears the fault register and initializes internal latches.
After the power-on-reset pulse, the UV and OV pins must
indicate that the input voltage is within the acceptable
range. All of these conditions must be satisfied for a duration of 48ms to ensure that any contact bounce during
the insertion has ended.
The MOSFET is turned on by charging up the GATE with a
charge pump generated 24µA current source whose value
is adjusted by shunting a portion of the pull-up current to
ground. The charging current is controlled by the INRUSH
circuit that maintains a constant slope of GATE voltage
t1
t2
4233 F02
Figure 2. Supply Turn-On
versus time (Figure 2). The voltage at the GATE pin rises
with a slope of 0.35[V/ms] and the supply inrush current
is set at:
IINRUSH = CL • 0.35[V/ms]
This gate slope is designed to charge up a 1000µF capacitor to 12V in 34ms, with an inrush current of 350mA. This
allows the inrush current to stay under the folded back
current limit threshold (2.8A) for capacitors less than 5mF.
Included in the Typical Performance Characteristics section
is a graph of the Safe Operating Area for the MOSFET. It
is evident from this graph that the power dissipation at
12V, 350mA for 34ms is in the safe region.
4233f
10
For more information www.linear.com/LTC4233
LTC4233
APPLICATIONS INFORMATION
Adding a capacitor and a 100k series resistor from GATE to
ground will lower the inrush current below the default value
set by the INRUSH circuit. The 3.3nF capacitor, CCOMP, is
necessary to compensate the current limit regulation loop
when the RGATE and CGATE network is on the GATE pin.
The GATE is charged with a 24µA current source (when
INRUSH circuit is not driving the GATE). The voltage at
the GATE pin rises with a slope equal to 24µA/CGATE and
the supply inrush current is set at:
IINRUSH=
CL
CGATE
LTC4233
GATE
CP
2.2nF
OPTIONAL
RC TO LOWER
INRUSH CURRENT
4233 F03
Figure 3. Compensation for Small CLOAD
Turn-Off Sequence
• 24µA
When the GATE voltage reaches the MOSFET threshold
voltage, the switch begins to turn on and the OUT voltage follows the GATE voltage as it increases. Once OUT
reaches VDD, the GATE will ramp up until clamped by the
6.1V Zener between GATE and OUT.
As the OUT voltage rises, so will the FB pin which is monitoring it. Once the FB pin crosses its 1.235V threshold
and the GATE to OUT voltage exceeds 4.2V, the PG pin
will cease to pull low and indicate that the power is good.
Parasitic MOSFET Oscillation
When the N-channel MOSFET ramps up the output during
power-up it operates as a source follower. The source follower configuration may self-oscillate in the range of 25kHz
to 300kHz when the load capacitance is less than 10µF,
especially if the wiring inductance from the supply to VDD
pin is greater than 3µH. The possibility of oscillations will
increase as the load current (during power-up) increases.
There are two ways to prevent this type of oscillation. The
simplest way is to avoid load capacitances below 10µF.
For wiring inductances larger than 20µH, the minimum
load capacitance may extend to 100µF. A second choice
is to connect an external gate capacitor CP > 1.5nF as
shown in Figure 3.
The switch can be turned off by a variety of conditions. A
normal turn-off is initiated by the UV pin going below its
1.235V threshold. Additionally, several fault conditions
will turn off the switch. These include an input overvoltage (OV pin), overcurrent circuit breaker (SENSE pin) or
overtemperature. Normally the switch is turned off with a
250µA current pulling down the GATE pin to ground. With
the switch turned off, the OUT voltage drops which pulls
the FB pin below its threshold. The PG then pulls low to
indicate output power is no longer good.
If VDD drops below 2.65V for greater than 5µs or INTVCC
drops below 2.5V for greater than 1µs, a fast shutdown
of the switch is initiated. The GATE is pulled down with a
140mA current to the OUT pin.
Overcurrent Fault
The LTC4233 features an adjustable current limit with
foldback that protects against short-circuits and excessive load current. To protect against excessive power
dissipation in the switch during active current limit, the
available current is reduced as a function of the output
voltage sensed by the FB pin. A graph in the Typical Performance Characteristics curves shows the current limit
threshold foldback.
4233f
For more information www.linear.com/LTC4233
11
LTC4233
APPLICATIONS INFORMATION
An overcurrent fault occurs when the current limit circuitry
has been engaged for longer than the timeout delay set
by the TIMER. Current limiting begins when the MOSFET
current reaches 2.8A to 11.2A (depending on the foldback).
The GATE pin is then brought down with a 140mA GATEto-OUT current. The voltage on the GATE is regulated in
order to limit the current to 11.2A. At this point, a circuit
breaker time delay starts by charging the external timing
capacitor with a 100µA pull-up current from the TIMER
pin. If the TIMER pin reaches its 1.235V threshold, the
internal switch turns off (with a 250µA current from
GATE to ground). Included in the Typical Performance
Characteristics curves is a graph of the Safe Operating
Area for the MOSFET. From this graph one can determine
the MOSFET’s maximum time in current limit for a given
output power.
Tying the TIMER pin to INTVCC will force the part to use
the internally generated (circuit breaker) delay of 2ms.
In either case the FLT pin is pulled low to indicate an
overcurrent fault has turned off the pass MOSFET. For a
given circuit breaker time delay, the equation for setting
the timing capacitor’s value is as follows:
CT = tCB • 0.083[µF/ms]
After the switch is turned off, the TIMER pin begins discharging the timing capacitor with a 2µA pull-down current. When the TIMER pin reaches its 0.21V threshold, it
completes one timer cycle. After eight TIMER pin cycles
(ramping to 1.235V and then below 0.21V) plus the 48ms
debounce time the switch is allowed to turn on again if the
overcurrent fault latch has been cleared. Bringing the UV
pin below 0.6V for a minimum of 1µs and then high will
clear the fault latch. If the TIMER pin is tied to INTVCC then
the switch is allowed to turn on again (after an internal
900ms cool down time plus the 48ms debounce time), if
the overcurrent fault latch is cleared.
Tying the FLT pin to the UV pin allows the part to self-clear
the fault and turn the MOSFET on as soon as TIMER pin
has ramped below 0.21V for the eighth time followed by
the 48ms debounce time. In this auto-retry mode the
LTC4233 repeatedly tries to turn on after an overcurrent
at a period determined by the capacitor on the TIMER pin.
The auto retry mode also functions when the TIMER pin
is tied to INTVCC.
The waveform in Figure 4 shows how the output latches
off following a short circuit. The current in the MOSFET
is 2.8A as the TIMER ramps up.
VOUT
10V/DIV
IOUT
2A/DIV
∆VGATE
10V/DIV
TIMER
2V/DIV
1ms/DIV
4233 F04
Figure 4. Short-Circuit Waveform
Current Limit Adjustment
The default value of the active current limit is 11.2A. The
current limit threshold can be adjusted lower by placing
a resistor between the ISET pin and ground. As shown in
the Functional Block Diagram the voltage at the ISET pin
(via the clamp circuit) sets the CS amplifier’s built-in offset
voltage. This offset voltage directly determines the active
current limit value. With the ISET pin open, the voltage
at the ISET pin is determined by a positive temperature
coefficient reference. This voltage is set to 0.618V which
corresponds to a 11.2A current limit at room temperature.
4233f
12
For more information www.linear.com/LTC4233
LTC4233
APPLICATIONS INFORMATION
An external resistor RSET placed between the ISET pin and
ground forms a resistive divider with the internal 20k RISET
sourcing resistor. The divider acts to lower the voltage at
the ISET pin and therefore lower the current limit threshold.
The overall current limit threshold precision is reduced to
±15% when using a 20k resistor to halve the threshold.
Using a switch (connected to ground) in series with RSET
allows the active current limit to change only when the
switch is closed. This feature can be used to program a
reduced running current while the maximum available
current limit is used at startup.
Monitor MOSFET Temperature
The voltage at the ISET pin increases linearly with increasing temperature. The temperature profile of the ISET pin is
shown in the Typical Performance Characteristics section.
Using a comparator or ADC to measure the ISET voltage
provides an accurate indication of the MOSFET temperature.
The ISET voltage follows the formula:
VISET =
RSET
• ( T + 273°C) • 2.093[mV/°C]
RSET + RISET
The MOSFET temperature is calculated using RISET of 20k.
T=
(RSET + 20k ) • VISET
RSET • 2.093[mV/°C]
− 273°C
The current in the MOSFET passes through an internal
1.4mΩ sense resistor. The voltage on the sense resistor is
converted to a current that is sourced out of the IMON pin.
The gain of ISENSE amplifier is 10µA/A referenced from the
MOSFET current. This output current can be converted to
a voltage using an external resistor to drive a comparator
or ADC. The voltage compliance for the IMON pin is from
0V to INTVCC − 0.7V.
A microcontroller with a built-in comparator can build a
simple integrating single-slope ADC by resetting a capacitor that is charged with this current. When the capacitor
voltage trips the comparator and the capacitor is reset, a
timer is started. The time between resets will indicate the
MOSFET current.
Monitor OV and UV Faults
Protecting the load from an overvoltage condition is the
main function of the OV pin. In Figure 1 an external resistive divider (driving the OV pin) connects to a comparator
to turn off the MOSFET when the VDD voltage exceeds
15.2V. If the VDD pin subsequently falls back below 14.9V,
the switch will be allowed to turn on immediately. In the
LTC4233 the OV pin threshold is 1.235V when rising, and
1.215V when falling out of overvoltage.
The UV pin functions as an undervoltage protection pin or
as an ON pin. In the Figure 1 application the MOSFET turns
off when VDD falls below 9.23V. If the VDD pin subsequently
rises above 9.88V for 48ms, the switch will be allowed to
turn on again. The LTC4233 UV turn-on/off threshold are
1.235V (rising) and 1.155V (falling).
When RSET is not present, T becomes:
T=
Monitor MOSFET Current
VISET
− 273°C
2.093[mV/°C]
There is an overtemperature circuit in the LTC4233 that
monitors an internal voltage similar to the ISET pin voltage.
When the die temperature exceeds 155°C the circuit turns
off the MOSFET until the temperature drops to 135°C.
In the case of an undervoltage or overvoltage the MOSFET
turns off and there is indication on the PG status pin. When
the overvoltage is removed, the MOSFET’s gate ramps up
immediately at the rate determined by the INRUSH circuit.
4233f
For more information www.linear.com/LTC4233
13
LTC4233
APPLICATIONS INFORMATION
Power Good Indication
In addition to setting the foldback current limit threshold,
the FB pin is used to determine a power good condition.
The Figure 1 application uses an external resistive divider
on the OUT pin to drive the FB pin. On the LTC4233 the
PG comparator drives high when the FB pin rises above
1.235V and low when it falls below 1.215V.
Once the PG comparator is high the GATE pin voltage is
monitored with respect to the OUT pin. Once the GATE
minus OUT voltage exceeds 4.2V the PG pin goes high.
This indicates to the system that it is safe to load the OUT
pin while the MOSFET is completely turned on. The PG
pin goes low when the GATE is commanded off (using
the UV, OV or SENSE– pins) or when the PG comparator
drives low.
Design Example
Consider the following design example (Figure 5):
TA = 60°C, VIN = 12V, IMAX = 10A. IINRUSH = 240mA, CL =
680µF, VUVON = 9.88V, VOVOFF = 15.2V, VPGTHRESHOLD =
10.5V. A current limit fault triggers an automatic restart
of the power up sequence.
The inrush current is defined by the current required to
charge the output capacitor using the fixed 0.35V/ms GATE
charge up rate. The inrush current is defined as:
IINRUSH = CL • 0.35[V/ms] =
680µF • 0.35[V/ms] = 240mA
As mentioned previously the charge-up time is the output
voltage (12V) divided by the output rate of 0.35V/ms
resulting in 34ms. The peak power dissipation of 12V
at 240mA (or 2.9W) must not exceed the SOA of the
pass MOSFET for 34ms (see MOSFET SOA graph in the
Typical Performance Characteristics section). On the SOA
graph the 30ms line crosses the 10V VDS vertical line at
4A. This verifies that the 40W for 30ms is safe at room
temperature. Each single point on the 3ms and 30ms lines
represent a power (voltage times current) and time that
follow a constant P2t relationship of 50W2s. If the MOSFET
junction temperature is elevated then the P2t constant
must be derated. At TJ = 60° the new constant becomes:
P2 t (TJ = 60°C) =
2
12V
VDD
R3
140k
 150°C − 60°C 
= 26  W2s 
50  W2s  • 
 150°C − 25°C 
OUT
LTC4233
Z1*
FB
R6
20k
UV
R1
226k
R5
150k
FLT
OV
R2
20k
R4
20k
SENSE–
CL
680µF
UV = 9.88V
OV = 15.2V
PG = 10.5V
R7
10k
PG
GATE
SENSE
C1
1µF
+
VOUT
12V
10A
TIMER
ISET
INTVCC
IMON
GND
ADC
RMON
20k
*TVS Z1: DIODES INC. SMAJ17A
4233 F05
Figure 5. 10A, 12V Card Resident Application
4233f
14
For more information www.linear.com/LTC4233
LTC4233
APPLICATIONS INFORMATION
The maximum power for 34ms can be calculated from
the derated constant:
PMAX
26  W2s 
P2 t(TJ = 60°C)

 = 28W
=
=
t
34ms
Therefore, the power dissipation at charge-up is within
the MOSFET SOA.
Next the power dissipated in the MOSFET during overcurrent must be limited. The active current limit uses a timer
to prevent excessive energy dissipation in the MOSFET.
The worst-case power dissipation occurs when the voltage versus current profile of the foldback current limit is
at the maximum. This occurs when the current is 12.4A
and the voltage is half of VIN or 6V. See the Current Limit
Threshold Foldback in the Typical Performance Characteristics section to view this profile. In order to survive
74W, the MOSFET SOA dictates a maximum current limit
timeout. If the MOSFET operating temperature is elevated
prior to current limit the SOA constant must be derated
according to the formula:
 150°C − TJ 
P2 t(TJ ) = P2 t(25°C) • 
 150°C − 25°C 
2
TJ is calculated from the ambient temperature, package
thermal impedance (θJA) and the I2R heating.
TJ = (θJA • I2 • RON) + TA = 15°C/W • (10A)2 •
14.5mΩ + 60°C = 82˚C
Using the SOA derating formula:
2
 150°C − 82°C 
P t(TJ = 82°C) = 50  W2s  • 
=
 150°C − 25°C 
2
15  W2s 


So the SOA constant is derated to 15W2s. The maximum
current limit timeout is calculated from the revised constant
and the 74W dissipated in current limit.
tMAX =
2
P2 t ( TJ = 82°C) 15  W s 
=
= 2.7ms
P2
(74W )2
Invoke the internal 2ms timer by tying the TIMER pin to
INTVCC. To configure the LTC4233 for auto-retry after
overcurrent fault, connect the FLT to the UV pin. After the
2ms timeout the FLT pin pulls down on the UV pin restart
the power-up sequence.
The values for overvoltage, undervoltage and power good
thresholds using the resistive dividers on the UV, OV and
FB pins match the requirements of turn-on at 9.88V and
turn-off at 15.2V.
The final schematic in Figure 5 results in very few external
components. The pull-up resistor, R7, connects to the PG
pin while the 20k (RMON) converts the IMON current to a
voltage at a ratio:
VIMON = 10[µA/A] • 20k • IOUT = 0.2[V/A] • IOUT
In addition there is a 1µF bypass (C1) on the INTVCC pin
and note the connection between SENSE to SENSE− (Pin
34 to Pin 31).
4233f
For more information www.linear.com/LTC4233
15
LTC4233
APPLICATIONS INFORMATION
Layout Considerations
In Hot Swap applications where load currents can be 10A,
narrow PCB tracks exhibit more resistance than wider tracks
and operate at elevated temperatures. The minimum trace
width requirement for 1oz copper foil is 0.02" per amp to
make sure the trace stays at a reasonable temperature.
Using 0.03" per amp or wider is recommended. Note that
1oz copper exhibits a sheet resistance of about 0.5mΩ/
square. Small resistances add up quickly in high current
applications.
The input supply should be tied to the VDD exposed pad
through a PCB trace that enters between Pin 1 and Pin 38.
The VDD pad connects to the sense resistor and MOSFET.
VDD
VDD
Globally, there are three DNC pins that are unconnected
and left open (Pins 6, 8, 33). Connect the SENSE– pin (Pin
34) to the SENSE pin (Pin 31). Figure 6 shows a recommended layout for the LTC4233.
During normal operation the power dissipated in the
MOSFET could be as high as 1.5W. To remove this heat,
solder the SENSE exposed pad to a copper trace that
contains vias underneath the pad. The OUT pins also
conduct substantial heat from the MOSFET. Connect all
the OUT pins to a plane of 1oz copper. Since the trace that
connects OUT pins must accommodate high current, this
area of copper is usually present. It is also important to
put C1, the bypass capacitor for the INTVCC pin as close
as possible between INTVCC and GND.
SENSE
OUT
C1
GND
4233 F06
Figure 6. Recommended Layout
4233f
16
For more information www.linear.com/LTC4233
LTC4233
APPLICATIONS INFORMATION
Thermal Considerations
The LTC4233 junction to board temperature rise in still
air when the load current is 5A, 7.5A and 10A is shown in
curves of Figures 7 and 8. The junction temperature was
measured at the package and the board temperature was
measured at the board edge. This temperature rise falls as
the board area is increases from 6.45 cm2 to 103 cm2. Two
different SENSE pad areas are shown as separate figures.
The curves demonstrate that the heat from the MOSFET
can be effectively transferred out of the package through
the OUT pins and only requires a minimum sized SENSE
pad under the package. However for small boards the
larger SENSE area does reduce the junction temperature
when sourcing higher currents.
120
120
100
100
80
80
5A
60
7.5A
10A
AB (cm2)
AB (cm2)
This thermal test board uses 2oz copper on the top layer
divided equally between VDD and OUT traces similar to
Figure 6. The second layer is 1oz copper connected to
the vias to the SENSE pad on the top layer. Two versions
of the second layer are considered. One uses a minimum
sized SENSE pad that only covers the vias for the top
layer while the remainder of the second layer is empty
(see Figure 7). The other version fills the second layer
with SENSE connected copper (see Figure 8). The third
layer is 1oz copper tied to ground while the bottom layer
is 2oz copper tied to ground except for a few signal traces.
40
40
20
20
0
0
5
10
15
20
∆TJB (°C)
25
30
35
SMALL SENSE PAD (2ND LAYER)
5A
7.5A
5
10
10A
60
0
0
15
20
∆TJB (°C)
25
30
35
LARGE SENSE PAD (2ND LAYER)
4233 F07
Figure 7. Temperature Rise for Small SENSE Pad
4233 F08
Figure 8. Temperature Rise for Large SENSE Pad
4233f
For more information www.linear.com/LTC4233
17
LTC4233
APPLICATIONS INFORMATION
Additional Applications
The LTC4233 has a wide operating range from 2.9V to 15V.
The UV, OV and PG thresholds are set with few resistors.
All other functions are independent of supply voltage.
Figure 10 shows a 3.3V application with a UV threshold
of 2.87V, an OV threshold of 3.77V and a PG threshold
of 3.05V.
In addition to Hot Swap applications, the LTC4233 also
functions as a backplane resident switch for removable
load cards (see Figure 9).
The last page shows a 20A parallel application where the
two LTC4233 parts each provide 10A to the load. The
PNPs prevent one LTC4233 from faulting off in current
limit until both parts hit the 11.2A limit. The PNPs are
disconnected when power good is false via the series
MOSFETs M1 and M2.
VDD
12V
Z1*
R1
226k
OUT
LTC4233
R7
10k
FB
R6
20k
PG
OV
R2
20k
R5
150k
12V
R4
20k
FLT
SENSE
–
UV
UV = 9.88V
OV = 15.2V
PG = 10.5V
R3
140k
LOAD
GATE
SENSE
C1
1µF
VOUT
12V
10A
TIMER
ISET
INTVCC
IMON
ADC
RMON
20k
GND
*TVS Z1: DIODES INC. SMAJ17A
4233 F09
Figure 9. 12V, 10A Backplane Resident Application with Insertion Activated Turn-On
3.3V
VDD
R1
17.4k
R4
14.7k
Z1*
LTC4233
UV
R2
3.16k
+
FB
FLT
CL
680µF
UV = 2.87V
OV = 3.77V
PG = 3.05V
R5
10k
OV
R3
10k
VOUT
3.3V
10A
OUT
R7
10k
SENSE–
PG
SENSE
C1
1µF
GATE
TIMER
ISET
INTVCC
IMON
GND
ADC
RMON
20k
*TVS Z1: DIODES INC. SMAJ17A
4233 F10
Figure 10. 3.3V, 10A Card Resident Application with Auto-Retry
4233f
18
For more information www.linear.com/LTC4233
LTC4233
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
WHH Package
WHH Package
Variation:
WHH38MA
Variation:
38-Lead
PlasticWHH38MA
QFN (5mm × 9mm)
38-Lead
Plastic
QFN#(5mm
× 9mm)
(Reference
LTC DWG
05-08-1934
Rev Ø)
(Reference LTC DWG # 05-08-1934 Rev Ø)
0.70 ±0.05
1.22 REF
0.72 REF
3.59 ±0.05
0.35 REF
5.5 ±0.05
3.59 ±0.05
4.1 ±0.05
0.7
2.7 ±0.05
BSC
0.5 REF
2.93 ±0.05
PACKAGE
OUTLINE
4.14 ±0.05
0.70 ±0.05
0.25 ±0.05
0.5 BSC
7.5 REF (2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ±0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.30
0.350 REF
0.9 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
2.93 ±0.10
3.59 ±0.10
0.50 REF
7.50
REF
9.00 ±0.10
(2 SIDES)
4.14 ±0.10
1.22 0.72
REF REF
0.25 ±0.05
3.59 ±0.10
0.5 BSC
(WHH36MA) QFN 1212 REV Ø
0.7 BSC
0.203 REF
0.00 – 0.05
0.90 ±0.10
0.40 ±0.10
2.7 REF
BOTTOM VIEW—EXPOSED PAD
SEATING PLANE
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4233f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC4233
19
LTC4233
TYPICAL APPLICATION
12V, 20A Parallel Application
12V
OUT
VDD
Z1*
107k
150k
LTC4233
FB
UV
+
FLT
1000µF
VOUT
12V
20A
100k
20k
5.23k
PG
OV
10k
1µF
SENSE–
TIMER
SENSE
GATE
INTVCC
ISET
GND
VDD
107k
0.1µF
IMON
OUT
150k
LTC4233
UV
FB
FLT
20k
5.23k
PG
OV
10k
1µF
SENSE–
TIMER
SENSE
GATE
INTVCC
ISET
GND
0.1µF
IMON
4233 TA02
*TVS Z1: DIODES INC. SMAJ17A
M2
VN2222LLG
M1
VN2222LLG
Q2
2N5087
Q1
2N5087
RELATED PARTS
PART NUMBER
LTC4210
LTC4211
LTC4212
LTC4214
LTC4215
LTC4217
LTC4218
LTC4221
LTC4227
DESCRIPTION
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Single Channel Hot Swap Controller
Negative Voltage Hot Swap Controller
Hot Swap Controller with I2C Compatible Monitoring
2A Integrated Hot Swap Controller
Hot Swap Controller with 5% Accurate 15mV
Current Limit
5A Integrated Hot Swap Controller
Positive and Negative Voltage, Dual Channel,
Hot Swap Controller
Dual Hot Swap Controller/Sequencer
Dual Ideal Diode and Single Hot Swap Controller
LTC4228
Dual Ideal Diode and Hot Swap Controller
LTC4230
LTC4232
LTC4234
Triple Channel Hot Swap Controller
5A Integrated Hot Swap Controller
20A Guaranteed SOA Hot Swap Controller
LTC4219
LT®4220
COMMENTS
Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6
Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10
Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10
Operates from 0V to –16V, MSOP-10
Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage
Operates from 2.9V to 26.5V, Adjustable 5% Accurate Current Limit
Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16, DFN-16
12V and 5V Preset Versions, 10% Accurate Current Limit
Operates from ±2.7V to ±16.5V, SSOP-16
Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16
Operates from 2.9V to 18V, PowerPath™ and Inrush Current Control for
Redundant Supplies
Operates from 2.9V to 18V, PowerPath and Inrush Current Control for Two Rails,
MicroTCA, Redundant Power Supplies, and Supply Holdup Applications
Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20
Operates from 2.9V to 15V, Adjustable 10% Accurate Current Limit
Operates from 2.9V to 15V, Adjustable 11% Accurate Current Limit
4233f
20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC4233
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC4233
LT 0715 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015