HA5023 Data Sheet September 30, 2015 Dual 125MHz Video Current Feedback Amplifier FN3393.9 Features • Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . 125MHz The HA5023 is a wide bandwidth high slew rate dual amplifier optimized for video applications and gains between 1 and 10. It is a current feedback amplifier and thus yields less bandwidth degradation at high closed loop gains than voltage feedback amplifiers. The low differential gain and phase, 0.1dB gain flatness, and ability to drive two back terminated 75cables, make this amplifier ideal for demanding video applications. The current feedback design allows the user to take advantage of the amplifier’s bandwidth dependency on the feedback resistor. By reducing RF, the bandwidth can be increased to compensate for decreases at higher closed loop gains or heavy output loads. The performance of the HA5023 is very similar to the popular Intersil HA-5020. • Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475V/s • Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . 800V • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03% • Differential Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03° • Supply Current (per Amplifier) . . . . . . . . . . . . . . . . 7.5mA • ESD Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V • Guaranteed Specifications at 5V Supplies • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Video Gain Block • Video Distribution Amplifier/RGB Amplifier • Flash A/D Driver Ordering Information • Current to Voltage Converter PART PART NUMBER MARKING TEMP. RANGE (°C) HA5023IPZ (Note) (No longer available, recommended replacement: HA5023IBZ) HA5023IPZ -40 to 85 HA5023IBZ (Note) 5023IBZ -40 to 85 8 Ld SOIC (Pb-free) HA5023IBZ96 (Note) 5023IBZ -40 to 85 M8.15 8 Ld SOIC Tape and Reel (Pb-free) PACKAGE 8 Ld PDIP* (Pb-free) PKG. DWG. # E8.3 • Medical Imaging • Radar and Imaging Systems • Video Switching and Routing Pinout HA5023 (PDIP, SOIC) TOP VIEW M8.15 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. OUT1 1 -IN1 2 +IN1 3 V- 4 -+ +- 8 V+ 7 OUT2 6 -IN2 5 +IN2 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC Copyright Intersil Americas LLC 1998, 2005-2006, 2015. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA5023 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .36V DC Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V Output Current (Note 4) . . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating (Note 3) Human Body Model (Per MIL-STD-883 Method 3015.7). . . 2000V Thermal Resistance (Typical, Note 2) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . 4.5V to 15V JA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Package, Note 1) . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175°C for die, and below 150°C for plastic packages. See Application Information section for safe operating area information. 2. JA is measured with the component mounted on an evaluation PC board in free air. 3. The non-inverting input of unused amplifiers must be connected to GND. 4. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle) output current should not exceed 15mA for maximum reliability. Electrical Specifications VSUPPLY = 5V, RF = 1k AV = +1, RL = 400 CL 10pF, Unless Otherwise Specified (NOTE 9) TEST LEVEL TEMP. (°C) MIN TYP MAX UNITS A 25 - 0.8 3 mV A Full - - 5 mV Delta VIO Between Channels A Full - 1.2 3.5 mV Average Input Offset Voltage Drift B Full - 5 - V/°C A 25 53 - - dB A Full 50 - - dB A 25 60 - - dB A Full 55 - - dB A Full 2.5 - - V A 25 - 3 8 A A Full - - 20 A A 25 - - 0.15 A/V A Full - - 0.5 A/V A 25 - - 0.1 A/V A Full - - 0.3 A/V A 25, 85 - 4 12 A A -40 - 10 30 A A 25, 85 - 6 15 A A -40 - 10 30 A PARAMETER TEST CONDITIONS INPUT CHARACTERISTICS Input Offset Voltage (VIO) VIO Common Mode Rejection Ratio VIO Power Supply Rejection Ratio Input Common Mode Range Note 5 3.5V VS 6.5V Note 5 Non-Inverting Input (+IN) Current +IN Common Mode Rejection Note 5 (+IBCMR = 1 ) +RIN 3.5V VS 6.5V +IN Power Supply Rejection Inverting Input (-IN) Current Delta -IN BIAS Current Between Channels 2 FN3393.9 September 30, 2015 HA5023 Electrical Specifications VSUPPLY = 5V, RF = 1k AV = +1, RL = 400 CL 10pF, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS -IN Common Mode Rejection Note 5 3.5V VS 6.5V -IN Power Supply Rejection (NOTE 9) TEST LEVEL TEMP. (°C) MIN TYP MAX UNITS A 25 - - 0.4 A/V A Full - - 1.0 A/V A 25 - - 0.2 A/V A Full - - 0.5 A/V Input Noise Voltage f = 1kHz B 25 - 4.5 - nV/Hz +Input Noise Current f = 1kHz B 25 - 2.5 - pA/Hz -Input Noise Current f = 1kHz B 25 - 25.0 - pA/Hz Note 11 A 25 1.0 - - M A Full 0.85 - - M A 25 70 - - dB A Full 65 - - dB A 25 50 - - dB A Full 45 - - dB A 25 2.5 3.0 - V A Full 2.5 3.0 - V TRANSFER CHARACTERISTICS Transimpedence RL = 400, VOUT = 2.5V Open Loop DC Voltage Gain RL = 100, VOUT = 2.5V Open Loop DC Voltage Gain OUTPUT CHARACTERISTICS Output Voltage Swing RL = 150 Output Current RL = 150 B Full 16.6 20.0 - mA Output Current, Short Circuit VIN = 2.5V, VOUT = 0V A Full 40 60 - mA Supply Voltage Range A 25 5 - 15 V Quiescent Supply Current A Full - 7.5 10 mA/Op Amp POWER SUPPLY CHARACTERISTICS AC CHARACTERISTICS (AV = +1) Slew Rate Note 6 B 25 275 350 - V/s Full Power Bandwidth Note 7 B 25 22 28 - MHz Rise Time Note 8 B 25 - 6 - ns Fall Time Note 8 B 25 - 6 - ns Propagation Delay Note 8 B 25 - 6 - ns B 25 - 4.5 - % Overshoot -3dB Bandwidth VOUT = 100mV B 25 - 125 - MHz Settling Time to 1% 2V Output Step B 25 - 50 - ns Settling Time to 0.25% 2V Output Step B 25 - 75 - ns 3 FN3393.9 September 30, 2015 HA5023 Electrical Specifications VSUPPLY = 5V, RF = 1k AV = +1, RL = 400 CL 10pF, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS (NOTE 9) TEST LEVEL TEMP. (°C) MIN TYP MAX UNITS AC CHARACTERISTICS (AV = +2, RF = 681 Slew Rate Note 6 B 25 - 475 - V/s Full Power Bandwidth Note 7 B 25 - 26 - MHz Rise Time Note 8 B 25 - 6 - ns Fall Time Note 8 B 25 - 6 - ns Propagation Delay Note 8 B 25 - 6 - ns B 25 - 12 - % Overshoot -3dB Bandwidth VOUT = 100mV B 25 - 95 - MHz Settling Time to 1% 2V Output Step B 25 - 50 - ns Settling Time to 0.25% 2V Output Step B 25 - 100 - ns Gain Flatness 5MHz B 25 - 0.02 - dB 20MHz B 25 - 0.07 - dB AC CHARACTERISTICS (AV = +10, RF = 383) Slew Rate Note 6 B 25 350 475 - V/s Full Power Bandwidth Note 7 B 25 28 38 - MHz Rise Time Note 8 B 25 - 8 - ns Fall Time Note 8 B 25 - 9 - ns Propagation Delay Note 8 B 25 - 9 - ns B 25 - 1.8 - % Overshoot -3dB Bandwidth VOUT = 100mV B 25 - 65 - MHz Settling Time to 1% 2V Output Step B 25 - 75 - ns Settling Time to 0.1% 2V Output Step B 25 - 130 - ns Differential Gain (Note 10) RL = 150 B 25 - 0.03 - % Differential Phase (Note 10) RL = 150 B 25 - 0.03 - ° VIDEO CHARACTERISTICS NOTES: 5. VCM = 2.5V. At -40°C Product is tested at VCM = 2.25V because Short Test Duration does not allow self heating. 6. VOUT switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points. Slew Rate 7. FPBW = ----------------------------- ; V = 2V . 2V PEAK PEAK 8. RL = 100, VOUT = 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay. 9. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only. 10. Measured with a VM700A video tester using an NTC-7 composite VITS. 11. VOUT = 2.5V. At -40°C Product is tested at VOUT = 2.25V because Short Test Duration does not allow self heating. 4 FN3393.9 September 30, 2015 HA5023 Test Circuits and Waveforms + - DUT 50 HP4195 NETWORK ANALYZER 50 FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS (NOTE 12) 100 (NOTE 12) 100 VIN + VIN DUT VOUT - 50 RL 100 RF, 1k FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT + DUT VOUT - 50 RI 681 RF, 681 RL 400 FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT NOTE: 12. A series input resistor of 100 is recommended to limit input currents in case input signals are present before the HA5023 is powered up. Vertical Scale: VIN = 100mV/Div., VOUT = 100mV/Div. Horizontal Scale: 20ns/Div. FIGURE 4. SMALL SIGNAL RESPONSE 5 Vertical Scale: VIN = 1V/Div., VOUT = 1V/Div. Horizontal Scale: 50ns/Div. FIGURE 5. LARGE SIGNAL RESPONSE FN3393.9 September 30, 2015 Schematic Diagram (One Amplifier of Two) V+ R2 800 R5 2.5K R10 820 QP8 R15 400 QP9 R19 400 QP11 QP1 QP5 QP14 R11 1K R17 280 QN5 6 QP15 QN12 R1 60K QP4 R28 20 QP17 QN13 +IN QN17 C2 1.4pF QN2 QN4 R14 280 R13 1K QN7 R25 20 QN15 R21 140 QN10 QP7 HA5023 QP13 QN3 QP20 R20 140 -IN R12 280 R3 6K D1 QP16 QP12 QP6 QN6 QN1 R24 140 C1 1.4pF QN8 QP2 QP19 R31 5 R18 280 QP10 R29 9.5 R27 200 R22 280 QN21 R25 140 QN18 QN14 QN16 R16 400 R23 400 R26 200 R32 5 QN19 R30 7 OUT R4 800 V- R33 800 R9 820 QN9 QN11 FN3393.9 September 30, 2015 HA5023 traces connected to -IN, and that connections to -IN be kept as short as possible to minimize the capacitance from this node to ground. Application Information Optimum Feedback Resistor The plots of inverting and non-inverting frequency response, see Figure 8 and Figure 9 in the typical performance section, illustrate the performance of the HA5023 in various closed loop gain configurations. Although the bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF. The HA5023 design is optimized for a 1000 RF at a gain of +1. Decreasing RF in a unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the amplifier is more stable, so RF can be decreased in a tradeoff of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. Driving Capacitive Loads Capacitive loads will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases the oscillation can be avoided by placing an isolation resistor (R) in series with the output as shown in Figure 6. 100 VIN R + VOUT - RT CL RF RI FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION RESISTOR, R The selection criteria for the isolation resistor is highly dependent on the load, but 27 has been determined to be a good starting value. Power Dissipation Considerations RF () BANDWIDTH (MHz) -1 750 100 +1 1000 125 +2 681 95 +5 1000 52 +10 383 65 -10 750 22 PC Board Layout The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. If leaded components are used the leads must be kept short especially for the power supply decoupling components and those components connected to the inverting input. Attention must be given to decoupling the power supplies. A large value (10F) tantalum or electrolytic capacitor in parallel with a small value (0.1F) chip capacitor works well in most cases. A ground plane is strongly recommended to control noise. Care must also be taken to minimize the capacitance to ground seen by the amplifier’s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. It is recommended that the ground plane be removed under 7 Due to the high supply current inherent in dual amplifiers, care must be taken to insure that the maximum junction temperature (TJ , see Absolute Maximum Ratings) is not exceeded. Figure 7 shows the maximum ambient temperature versus supply voltage for the available package styles (Plastic DIP, SOIC). At 5VDC quiescent operation both package styles may be operated over the full industrial range of -40°C to 85°C. It is recommended that thermal calculations, which take into account output power, be performed by the designer. MAX AMBIENT TEMPERATURE (°C) GAIN (ACL) 140 130 120 PDIP 110 100 90 SOIC 80 70 60 50 5 7 9 11 13 15 SUPPLY VOLTAGE (V) FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERATURE vs SUPPLY VOLTAGE FN3393.9 September 30, 2015 HA5023 Typical Performance Curves VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C, Unless Otherwise Specified 5 5 VOUT = 0.2VP-P CL = 10pF AV = 2, RF = 681 3 2 3 AV = 5, RF = 1k 1 0 -1 -2 -3 VOUT = 0.2VP-P CL = 10pF RF = 750 4 NORMALIZED GAIN (dB) AV = 10, RF = 383 -4 2 1 AV = -2 0 -1 -2 AV = -10 -3 AV = -5 -4 -5 10 100 -5 200 FREQUENCY (MHz) 2 180 AV = +1, RF = 1k 135 -45 -90 90 AV = -1, RF = 750 -135 45 AV = +10, RF = 383 -100 0 -225 -45 -270 -90 AV = -10, RF = 750 -315 2 140 VOUT = 0.2VP-P CL = 10pF AV = +1 130 120 100 5 GAIN PEAKING 500 200 700 FREQUENCY (MHz) 10 5 350 500 650 800 950 0 1100 GAIN PEAKING (dB) -3dB BANDWIDTH FEEDBACK RESISTOR () FIGURE 12. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE 8 -3dB BANDWIDTH (MHz) 95 GAIN PEAKING 0 1500 130 VOUT = 0.2VP-P CL = 10pF AV = +2 90 900 1100 1300 FEEDBACK RESISTOR () FIGURE 11. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE FIGURE 10. PHASE RESPONSE AS A FUNCTION OF FREQUENCY 100 10 -3dB BANDWIDTH -180 10 200 -135 VOUT = 0.2VP-P CL = 10pF -360 INVERTING PHASE (°) NONINVERTING PHASE (°) 0 100 FIGURE 9. INVERTING FREQUENCY RESPONSE -3dB BANDWIDTH (MHz) FIGURE 8. NON-INVERTING FREQENCY RESPONSE 10 FREQUENCY (MHz) GAIN PEAKING (dB) 2 -3dB BANDWIDTH (MHz) AV = -1 120 -3dB BANDWIDTH 110 6 100 4 90 GAIN PEAKING 80 0 200 400 VOUT = 0.2VP-P CL = 10pF AV = +1 600 800 2 GAIN PEAKING (dB) NORMALIZED GAIN (dB) 4 AV = +1, RF = 1k 0 1000 LOAD RESISTOR () FIGURE 13. BANDWIDTH AND GAIN PEAKING vs LOAD RESISTANCE FN3393.9 September 30, 2015 HA5023 Typical Performance Curves VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C, Unless Otherwise Specified (Continued) 16 VOUT = 0.1VP-P CL = 10pF VOUT = 0.2VP-P CL = 10pF AV = +10 60 VSUPPLY = 5V, AV = +2 OVERSHOOT (%) -3dB BANDWIDTH (MHz) 80 40 12 VSUPPLY = 15V, AV = +2 6 20 0 VSUPPLY = 5V, AV = +1 200 350 500 650 800 0 950 VSUPPLY = 15V, AV = +1 0 200 400 600 LOAD RESISTANCE () FEEDBACK RESISTOR () 0.08 0.10 FREQUENCY = 3.58MHz 0.08 DIFFERENTIAL PHASE (°) DIFFERENTIAL GAIN (%) FREQUENCY = 3.58MHz RL = 75 0.06 RL = 150 0.04 0.02 0.06 0.04 RL = 150 RL = 75 0.02 RL = 1k RL = 1k 0.00 3 5 7 9 11 13 3 15 5 SUPPLY VOLTAGE (V) -40 VOUT = 2.0VP-P CL = 30pF 0 REJECTION RATIO (dB) HD2 -60 3RD ORDER IMD HD2 HD3 -80 -90 0.3 13 15 AV = +1 -10 -50 -70 7 9 11 SUPPLY VOLTAGE (V) FIGURE 17. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE FIGURE 16. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE DISTORTION (dBc) 1000 FIGURE 15. SMALL SIGNAL OVERSHOOT vs LOAD RESISTANCE FIGURE 14. BANDWIDTH vs FEEDBACK RESISTANCE 0.00 800 FIGURE 18. DISTORTION vs FREQUENCY 9 -30 -40 -50 CMRR -60 NEGATIVE PSRR -70 -80 HD3 1 FREQUENCY (MHz) -20 10 0.001 POSITIVE PSRR 0.01 0.1 1 10 30 FREQUENCY (MHz) FIGURE 19. REJECTION RATIOS vs FREQUENCY FN3393.9 September 30, 2015 HA5023 Typical Performance Curves VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C, Unless Otherwise Specified (Continued) 12 8.0 RLOAD = 100 VOUT = 1.0VP-P PROPAGATION DELAY (ns) 7.5 7.0 6.5 6.0 -50 -25 0 25 50 75 100 10 AV = +10, RF = 383 8 AV = +2, RF = 681 6 AV = +1, RF = 1k 4 125 3 5 7 9 11 SUPPLY VOLTAGE (V) TEMPERATURE (C) FIGURE 20. PROPAGATION DELAY vs TEMPERATURE VOUT = 0.2VP-P CL = 10pF 0.6 + SLEW RATE NORMALIZED GAIN (dB) SLEW RATE (V/s) 0.8 VOUT = 2VP-P 400 350 - SLEW RATE 300 250 200 150 0.4 0.2 AV = +2, RF = 681 0 -0.2 -0.4 AV = +5, RF = 1k -0.6 AV = +1, RF = 1k -0.8 -1.0 100 -50 -25 0 25 50 75 100 AV = +10, RF = 383 -1.2 125 5 10 TEMPERATURE (°C) FIGURE 22. FIGURE 22. SLEW RATE vs TEMPERATURE VOLTAGE NOISE (nV/Hz) NORMALIZED GAIN (dB) 0 AV = -1 -0.2 -0.4 -0.6 AV = -5 -0.8 -1.2 10 1000 -INPUT NOISE CURRENT 80 800 600 60 +INPUT NOISE CURRENT 400 40 INPUT NOISE VOLTAGE 200 20 AV = -2 AV = -10 5 30 AV = +10, RF = 383 0.2 -1.0 25 100 VOUT = 0.2VP-P CL = 10pF RF = 750 0.4 15 20 FREQUENCY (MHz) FIGURE 23. NON-INVERTING GAIN FLATNESS vs FREQUENCY 0.8 0.6 15 FIGURE 21. PROPAGATION DELAY vs SUPPLY VOLTAGE 500 450 13 CURRENT NOISE (pA/Hz) PROPAGATION DELAY (ns) RL = 100 VOUT = 1.0VP-P AV = +1 15 20 25 30 FREQUENCY (MHz) FIGURE 24. INVERTING GAIN FLATNESS vs FREQUENCY 10 0 0.01 0.1 1 FREQUENCY (kHz) 10 0 100 FIGURE 25. INPUT NOISE CHARACTERISTICS FN3393.9 September 30, 2015 HA5023 Typical Performance Curves VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C, Unless Otherwise Specified (Continued) 1.5 BIAS CURRENT (A) 2 VIO (mV) 1.0 0.5 0.0 -60 -40 -20 0 20 40 60 80 100 120 0 -2 -4 -60 140 -40 -20 0 TEMPERATURE (°C) TRANSIMPEDANCE (k) BIAS CURRENT (A) 60 80 100 120 140 4000 22 20 18 16 -60 -40 -20 0 20 40 60 80 100 120 140 3000 2000 1000 -60 -40 -20 0 TEMPERATURE (°C) 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 28. -INPUT BIAS CURRENT vs TEMPERATURE FIGURE 29. TRANSIMPEDANCE vs TEMPERATURE 74 25 +PSRR 72 20 REJECTION RATIO (dB) 125°C ICC (mA) 40 FIGURE 27. +INPUT BIAS CURRENT vs TEMPERATURE FIGURE 26. INPUT OFFSET VOLTAGE vs TEMPERATURE 55°C 15 10 3 4 5 6 7 70 68 -PSRR 66 64 62 CMRR 60 25°C 5 20 TEMPERATURE (°C) 8 9 10 11 12 13 14 SUPPLY VOLTAGE (V) FIGURE 30. SUPPLY CURRENT vs SUPPLY VOLTAGE 11 15 58 -100 -50 0 50 100 150 200 250 TEMPERATURE (°C) FIGURE 31. REJECTION RATIO vs TEMPERATURE FN3393.9 September 30, 2015 HA5023 Typical Performance Curves VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C, Unless Otherwise Specified (Continued) 4.0 30 +15V +10V +5V OUTPUT SWING (V) SUPPLY CURRENT (mA) 40 20 3.8 10 0 0 1 2 3 4 5 6 7 8 9 3.6 -60 10 11 12 13 14 15 -40 -20 0 DISABLE INPUT VOLTAGE (V) 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 32. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE FIGURE 33. OUTPUT SWING vs TEMPERATURE 30 1.2 VCC = 15V 1.1 VIO (mV) VOUT (VP-P) 20 VCC = 10V 1.0 10 0.9 VCC = 4.5V 0.8 0 0.01 0.10 1.00 10.00 -60 -40 -20 LOAD RESISTANCE (k) 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 34. OUTPUT SWING vs LOAD RESISTANCE FIGURE 35. INPUT OFFSET VOLTAGE CHANGE BETWEEN CHANNELS vs TEMPERATURE -30 1.5 AV = +1 VOUT = 2VP-P 1.0 SEPARATION (dB) BIAS CURRENT (A) -40 0.5 -50 -60 -70 0.0 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 36. INPUT BIAS CURRENT CHANGE BETWEEN CHANNELS vs TEMPERATURE 12 140 -80 0.1 1 FREQUENCY (MHz) 10 30 FIGURE 37. CHANNEL SEPARATION vs FREQUENCY FN3393.9 September 30, 2015 HA5023 Typical Performance Curves VSUPPLY = 5V, AV = +1, RF = 1k RL = 400 TA = 25°C, Unless Otherwise Specified (Continued) -30 -40 -50 10 RL = 100 1 0.1 0.01 180 0.001 135 90 45 -60 0 -70 -45 -80 -90 1 FREQUENCY (MHz) 10 FIGURE 38. DISABLE FEEDTHROUGH vs FREQUENCY 20 0.001 0.01 0.1 1 FREQUENCY (MHz) 10 100 -135 FIGURE 39. TRANSIMPEDANCE vs FREQUENCY 10 RL = 400 1 0.1 0.01 180 0.001 135 90 45 0 -45 PHASE ANGLE (°) 0.1 PHASE ANGLE (°) -20 TRANSIMPEDANCE (M) FEEDTHROUGH (dB) -10 DISABLE = 0V VIN = 5VP-P RF = 750 TRANSIMPEDANCE (M) 0 -90 0.001 0.01 0.1 1 10 FREQUENCY (MHz) 100 -135 FIGURE 40. TRANSIMPEDENCE vs FREQUENCY 13 FN3393.9 September 30, 2015 HA5023 SUBSTRATE POTENTIAL (Powered Up): Die Characteristics V- DIE DIMENSIONS: PASSIVATION: 1650m x 2540m x 483m Type: Nitride Thickness: 4kÅ 0.4kÅ METALLIZATION: Type: Metal 1: AlCu (1%) Thickness: Metal 1: 8kÅ 0.4kÅ TRANSISTOR COUNT: 124 Type: Metal 2: AlCu (1%) Thickness: Metal 2: 16kÅ 0.8kÅ PROCESS: High Frequency Bipolar Dielectric Isolation Metallization Mask Layout HA5023 OUT NC V+ -IN1 +IN1 NC OUT2 NC V- +IN 14 -IN FN3393.9 September 30, 2015 HA5023 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION September 30, 2015 FN3393.9 CHANGE - Updated Ordering Information Table on page 1. - Added Revision History. - Added About Intersil Verbiage. - Updated POD M8.15 to latest revision changes are as follow: -Revision 1 to Revision 2 Changes: Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern -Revision 2 to Revision 3 Changes: Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) -Revision 3 to Revision 4 Changes: Changed Note 1 "1982" to "1994" About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN3393.9 September 30, 2015 HA5023 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 5 D1 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 8 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 16 FN3393.9 September 30, 2015 HA5023 Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. 17 FN3393.9 September 30, 2015