Application Note 1519 ISL28213/14SOICEVAL2Z Evaluation Board User’s Guide J11 Amplifier Configuration (Figure 2) The schematic of 1/2 of the op-amp with the components supplied is shown in Figure 2. The circuit implements a differential input amp with a closed loop gain of 10. The circuit can operate from a single supply or from dual supplies. The VREF pin must be connected to ground to establish a ground referenced input for dual supply operation, or can be externally set to any reference level for single supply operation. VREF should not be left floating. Power Supplies (Figure 1) External power connections are made through the +V, -V, VREF and Ground connections on the evaluation board. For single supply operation, the -V and Ground pins are tied together to the power supply negative terminal. For split supplies, +V and -V terminals connect to their RF 100k IN - VREF GND ISL28213, ISL28214 (1/2) VP V+ 10k VREF IN+ + 0Ω VOUT VVM 10k RREF+ 0Ω R31 0 R16 The ISL28213/14SOICEVAL2Z is designed to enable the IC to operate from a single supply, +2.4VDC to +5.5VDC or from split supplies, ±1.2VDC to ±2.75V. The board is configured for a dual op amp connected for differential input with a closed loop gain of 10. A single external reference voltage (VREF) pin and provisions for a user-selectable voltage divider - filter are included. VCM J14 Evaluation Board Key Features IN + J13 • ISL28214 Data Sheet, FN6800 IN+ 0.01µF respective power supply terminals. De-coupling capacitors C2 and C4 connect to their respective supplies through R16 and R31 0Ω resistors. These resistors are 0Ω, but can be changed by the user to provide additional power supply filtering. Two additional capacitors, C3 and C5, are connected close to the DUT to filter out high frequency noise. Anti-reverse diode D1 protects the circuit in the case of accidental polarity reversal. • ISL28213 Data Sheet, FN6728 RIN+ TO DUT C5 FIGURE 1. POWER SUPPLY CIRCUIT • ISL28213/14SOICEVAL2Z Evaluation Board User’s Guide IN- VREF D1 0.01µF IN- C4 1µF CLOSE C3 Reference Documents RIN- C2 1µF J12 The ISL28213 and ISL28214 CMOS operational amplifiers feature low power consumption, low input bias current, and rail-to-rail input and output drive capability. They are designed to operate with a single lithium cell or two Ni_Cd batteries. V+ J8 V- The ISL28213/14SOICEVAL2Z evaluation board is a design platform containing all the circuitry needed to characterize critical performance parameters of the ISL28213 and ISL28214 operational amplifiers, using a variety of user defined test circuits. 0 J6 Introduction 100k RL 10k 10k FIGURE 2. BASIC AMPLIFIER CONFIGURATION January 19, 2010 AN1519.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1519 User-selectable Options (Figures 3 and 4) The outputs (Figure 4) have a 10kΩ load resistor to ground and have additional resistor and capacitor placements for loading. Component pads are included to enable a variety of userselectable circuits to be added to the amplifier VREF, inputs, outputs, and the amplifier feedback loops. The inputs (Figure 3) have additional resistor, capacitor, and jumper placements for loading and/or measurement of frequency sensitive parameters. R13 0 10k 100k C1 DNP R3 OPEN R26 10k R11 C6 OPEN R28 R4 FROM OUTPUT R17 DNP DNP R12 DNP R6 J2 DNP R1 DNP OUT R10 R5 J1 NODE C8 IN+ DNP IN- NOTE: Operational amplifiers are sensitive to output capacitance and may oscillate. In the event of oscillation, reduce output capacitance by using shorter cables, or add a resistor in series with the output. 0 TO OUTPUT OPEN R14 TO INTO IN+ R2 10k DNP VREF R15 R18 DNP 100k FIGURE 3. INPUT STAGE (1/2) FIGURE 4. OUTPUT STAGE (1/2) ISL28213/14SOICEVAL2Z Components Parts List DEVICE # DESCRIPTION COMMENTS C2, C4 CAP-TANTALUM, SMD, 1.0µF, 50V, 10%, LOW ESR, ROHS Power Supply Decoupling C3, C5 CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R, ROHS Power Supply Decoupling CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS User Selectable Capacitors - not populated DIODE-SCHOTTKY BARRIER, SMD, SOT-23, 3P, 40V, ROHS Reverse Power Protection C1, C6-C10 D1 U1 (ISL28213FBZ) ISL28213FBZ-T7, IC-RAIL-TO-RAIL OP AMP, SOIC, ROHS U1 (ISL28214FBZ) ISL28214FBZ-T7, IC-RAIL-TO-RAIL OP AMP, SOIC, ROHS R30, R32, R34-R36 RESISTOR, SMD, 0603, 0.1%, MF, DNP-PLACE HOLDER User Selectable Resistors - not populated RES, SMD, 0603, 0Ω, 1/10W, TF, ROHS 0Ω User Selectable Resistors RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS Gain and Other User Selectable Resistors RES, SMD, 0603, 100k, 1/10W, 1%, TF, ROHS Gain Resistors R4, R16, R25-R27, R31 R11, R14, R21, R24, R28, R29 R13, R18, R19, R23 2 AN1519.0 January 19, 2010 Application Note 1519 ISL28213/14SOICEVAL2Z FIGURE 5. TOP VIEW (SOIC SHOWN) Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1519.0 January 19, 2010 ISL28213/14SOICEVAL2Z Schematic Diagram J11 R31 0 R16 C4 1µF VREF J14 4 C2 1µF J13 J12 J8 V+ 0 J6 V- D1 0.01µF 0.01µF C6 OPEN R14 10k 4 5 J24 OPEN C7 R21 OPEN R27 10k 0 R15 R18 R19 R22 DNP 100k 100k DNP R7 DNP R8 DNP AN1519.0 January 19, 2010 FIGURE 6. DNP C8 J16 DNP R30 U1 8 2 SOIC8 7 GENERIC 3 PACK. 6 1 0 DNP 10k 100k C1 DNP R36 R24 R13 10k VREF J4 J23 R23 100k C10 R11 R35 DNP DNP R34 DNP OPEN R26 IN- 0 R20 R32 DNP DNP R12 DNP DNP R10 DNP J3 IN+ J22 J21 J20 J19 J18 NODE R25 R5 R3 OUT C9 R2 OUT OPEN R29 J2 DNP DNP 0 NODE R17 R6 R1 DNP R4 J1 DNP J17 IN+ OPEN R28 J15 IN- Application Note 1519 CLOSE TO DUT C3 C5