Application Note 1520 ISL28113/14SOT23EVAL1Z Evaluation Board User’s Guide J8 V+ C2 C4 4.7µF D1 4.7µF D2 Evaluation Board Key Features The ISL28113/14SOT23EVAL1Z is designed to enable the IC to operate from a single supply, +2.4VDC to +5.5VDC or from split supplies, ±1.2VDC to ±2.75V. The board is configured for a single op amp connected for differential input with a closed loop gain of 10. A single external reference voltage (VREF) pin and provisions for a userselectable voltage divider - filter are included. Amplifier Configuration (Figure 2) The schematic of the op-amp with the components supplied is shown in Figure 2. The circuit implements a differential input amp with a closed loop gain of 10. The circuit can operate from a single supply or from dual supplies. The VREF pin can be connected to ground to establish a ground referenced input for split supply operation, or can be externally set to any reference level for single supply operation. Note: VREF should not be left floating. Power Supplies (Figure 1) External power connections are made through the +V, -V and Ground connections on the evaluation board. For single supply operation, the -V and Ground pins are tied together to the power supply negative terminal. For split supplies, +V and -V terminals connect to their respective power supply terminals. De-coupling capacitors C2 and RF 100k IN RININ- IN- RIN+ IN+ GND VP V+ IN+ + VOUT V- RREF+ 0Ω 0Ω VM 10k IN + ISL28113, ISL28114 - 10k VREF 0.1µF C4 can connect to ground through R4 and R16 resistors. These resistors are not populated, but can be used to provide additional power supply filtering. Four additional capacitors, C1 and C5 (0.01µF) and C7 and C8 (0.1µF) are connected close to the part to filter out high frequency noise. Anti-reverse diodes D1 and D2 protect the circuit in the case of accidental polarity reversal. • ISL28114 Data Sheet, FN6800 VREF C5 FIGURE 1. POWER SUPPLY CIRCUIT • ISL28113 Data Sheet, FN6728 VCM J11 S1AB 0.1µF C7 C1 Reference Documents 0.01µF S1AB J10 VREF J9 R16 J13 C8 R4 The ISL28113 and ISL28114 CMOS operational amplifiers feature low power consumption, low input bias current, and rail-to-rail input and output drive capability. They are designed to operate with a single lithium cell or two Ni_Cd batteries. DNP V- DNP J7 The ISL28113/14SOT23EVAL1Z evaluation board is a design platform containing all the circuitry needed to characterize critical performance parameters of the ISL28113 and ISL28114 operational amplifiers, using a variety of user defined test circuits. 0.01µF Introduction 100k RL 10k 10k FIGURE 2. BASIC AMPLIFIER CONFIGURATION January 19, 2010 AN1520.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1520 User-selectable Options (Figures 3 and 4) non-inverting inputs have additional resistor placements for adding input attenuation, or to establish input DC offsets through the VREF pin. Component pads are included to enable a variety of user-selectable circuits to be added to the amplifier inputs, the VREF input, the output and the amplifier feedback loop. The output (Figure 4) has additional resistor and capacitor placements for loading. NOTE: Operational amplifiers are sensitive to output capacitance and may oscillate. In the event of oscillation, reduce output capacitance by using shorter cables, or add a resistor in series with the output. A voltage divider and filter option (Figure 3) can be added to establish a power supply-tracking common mode reference at the VREF input. The inverting and R1 0 10k 100k DNP FROM OUT To IN - J12 R12 J2 R2 To IN + OPEN R17 0 + C6 IN R18 10k DNP R13 R15 DNP 100k OUTPUT DNP J1 OPEN R11 DNP - R9 R7 IN R5 VREF FIGURE 4. OUTPUT STAGE FIGURE 3. INPUT STAGE ISL28113/14SOT23EVAL1Z Components Parts List DEVICE # DESCRIPTION COMMENTS C2, C4 CAP-TANTALUM, SMD, 4.7µF, 50V, 10%, LOW ESR, ROHS Power Supply Decoupling C1, C5 CAP, SMD, 0603, 0.01µF, 25V, 10%, X7R, ROHS Power Supply Decoupling C7, C8 CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R, ROHS Power Supply Decoupling C3, C6 CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS User Selectable Capacitors - not populated D1, D2 DIODE-RECTIFIER, SMD, SOD-123, 2P, 40V, 0.5A, ROHS Reverse Power Protection U1 (ISL28113EVAL1Z) ISL28113FHZ-T7, IC-RAIL-TO-RAIL OP AMP, SOT-23, ROHS U1 (ISL28114EVAL1Z) ISL28114FHZ-T7, IC-RAIL-TO-RAIL OP AMP, SOT-23, ROHS R1-R4, R6-R8, R10, R13, R14, R16, R17, R19-R21 RESISTOR, SMD, 0603, 0.1%, MF, DNP-PLACE HOLDER User Selectable Resistors - not populated R5, R18 RES, SMD, 0603, 0Ω, 1/10W, TF, ROHS 0Ω User Selectable Resistors R9, R12 RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS Gain and Other User Selectable Resistors RES, SMD, 0603, 100k, 1/10W, 1%, TF, ROHS Gain Resistors R11, R15 2 AN1520.0 January 19, 2010 Application Note 1520 ISL28113/14SOT23EVAL1Z FIGURE 5. TOP VIEW Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1520.0 January 19, 2010 ISL28113/14SOT23EVAL1Z Schematic Diagram J8 J7 4.7µF D1 4.7µF D2 S1AB S1AB DNP C4 R16 DNP R4 VREF J11 J10 C2 J9 V+ J13 V- 4 100k 0 DNP R18 10k R13 R15 DNP 100k J14 R19 DNP DNP 2 S1 3 1 DNP R20 DNP R21 DNP AN1520.0 January 19, 2010 FIGURE 6. VREF 0.1µF SOT23_6 0.1µF C7 C1 0.01µF 10k C8 R2 DNP 0.01µF J2 ENABLE 6 GENERIC PACK. 5 3 4 2 R12 C5 + DNP OPEN R17 U1 1 IN J12 C6 R3 DNP J6 R9 0 C3 R14 R5 OPEN R11 R7 R1 J5 DNP R6 R10 DNP R8 DNP DNP J1 DNP - OUT OUTPUT Application Note 1520 IN NODE J4 IN+ J3 IN-