INTERSIL ISL28413FVZ-T13

ISL28113, ISL28213, ISL28413
Features
The ISL28113, ISL28213, and ISL28413 are single,
dual, and quad channel general purpose micropower,
rail-to-rail input and output operational amplifiers with
supply voltage range of 1.8V to 5.5V. Key features are
a low supply current of 130µA maximum per channel
at room temperature, a low bias current and a wide
input voltage range, which enables the ISL28x13
devices to be excellent general purpose op-amps for a
wide range of applications.
• Low Current Consumption . . . . . . . . . . . . . . 130µA
The ISL28113 is available in the SC70-5 and SOT23-5
packages, the ISL28213 is in the MSOP8, SOIC8,
SOT23-8 packages, and the ISL28413 is in the TSSOP14,
SOIC14 packages. All devices operate over the extended
temperature range of -40°C to +125°C.
• Wide Supply Range. . . . . . . . . . . . . . . 1.8V to 5.5V
• Gain Bandwidth Product . . . . . . . . . . . . . . . . 2MHz
• Input Bias Current . . . . . . . . . . . . . . . . 20pA, Max.
• Operating Temperature Range . . . .-40°C to +125°C
• Packages
- ISL28113 (Single) . . . . . . . . . . SC70-5, SOT23-5
- ISL28213 (Dual) . . . . . . MSOP8, SOIC8, SOT23-8
- ISL28413 (Quad). . . . . . . . . . . SOIC14, TSSOP14
Applications*(see page 15)
• Power Supply Control/Regulation
• Process Control
• Signal Gain/Buffers
• Active Filters
• Current Shunt Sensing
• Trans-impedance Amps
Related Literature*(see page 15)
• See AN1519 for “ISL28213/14SOICEVAL2Z
Evaluation Board User’s Guide”
• See AN1520 for “ISL28113/14SOT23EVAL1Z
Evaluation Board User’s Guide”
• See AN1542 for “ISL28213/14MSOPEVAL2Z
Evaluation Board User’s Guide”
Typical Application
RF
100kΩ
LOAD
RINRSENSE
IN-
10kΩ
RIN+
IN+
10kΩ
+5V
-
VOUT
V+
ISL28x13
V-
+
GAIN = 10
RREF+
100kΩ
VREF
SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER
March 25, 2010
FN6728.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL28113, ISL28213, ISL28413
Single, Dual, Quad General Purpose Micropower,
RRIO Operational Amplifier
ISL28113, ISL28213, ISL28413
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28113FEZ-T7 (Note 1)
BJA
5 Ld SC-70
P5.049
ISL28113FEZ-T7A (Note 1)
BJA
5 Ld SC-70
P5.049
ISL28113FHZ-T7 (Note 1)
BCYA
5 Ld SOT-23
MDP0038
ISL28113FHZ-T7A (Note 1)
BCYA
5 Ld SOT-23
MDP0038
ISL28213FUZ
8213Z
8 Ld MSOP
M8.118A
ISL28213FUZ-T7 (Note 1)
8213Z
8 Ld MSOP
M8.118A
ISL28213FBZ
28213 FBZ
8 Ld SOIC
M8.15E
ISL28213FBZ-T7 (Note 1)
28213 FBZ
8 Ld SOIC
M8.15E
ISL28213FBZ-T13 (Note 1)
28213 FBZ
8 Ld SOIC
M8.15E
Coming Soon
ISL28213FHZ
TBD
8 Ld SOT-23
P8.064
Coming Soon
ISL28213FHZ-T7 (Note 1)
TBD
8 Ld SOT-23
P8.064
ISL28413FVZ
28413 FVZ
14 Ld TSSOP
MDP0044
ISL28413FVZ-T7 (Note 1)
28413 FVZ
14 Ld TSSOP
MDP0044
ISL28413FVZ-T13 (Note 1)
28413 FVZ
14 Ld TSSOP
MDP0044
ISL28413FBZ
28413 FBZ
14 Ld SOIC
MDP0027
ISL28413FBZ-T7 (Note 1)
28413 FBZ
14 Ld SOIC
MDP0027
ISL28413FBZ-T13 (Note 1)
28413 FBZ
14 Ld SOIC
MDP0027
ISL28113SOT23EVAL1Z
Evaluation Board
ISL28213MSOPEVAL2Z
Evaluation Board
ISL28213SOICEVAL2Z
Evaluation Board
ISL28413TSSOPEVAL1Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28113, ISL28213, ISL28413. For more
information on MSL please see techbrief TB363.
Pin Configurations
ISL28113
(5 LD SC-70)
TOP VIEW
IN+
1
VS-
2
IN-
3
5
4
ISL28113
(5 LD SOT-23)
TOP VIEW
VS+
OUT
2
OUT
1
VS-
2
IN+
3
5
4
ISL28213
(8 LD MSOP, 8 LD SOIC, 8 LD SOT-23)
TOP VIEW
VS+
IN-
OUT_A
1
8
VS+
IN-_A
2
7
OUT_B
IN+_A
3
6
IN-_B
VS-
4
5
IN+_B
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Pin Configurations (Continued)
ISL28413
(14 LD TSSOP, 14 LD SOIC)
TOP VIEW
OUT_A 1
14 OUT_D
IN-_A 2
13 IN-_D
IN+_A 3
12 IN+_D
VS+ 4
11 VS-
IN+_B 5
10 IN+_C
IN-_B 6
9 IN-_C
OUT_B 7
8 OUT_C
Pin Descriptions
PIN NUMBER
5 LD
PIN NAME SC-70
OUT
OUT_A
OUT_B
OUT_C
OUT_D
4
14 LD
8 LD MSOP,
TSSOP,
8 LD SOIC,
5 LD
SOT-23 8 LD SOT-23 14 LD SOIC
DESCRIPTION
Output
1
1
7
V+
1
7
8
14
OUT
VCIRCUIT 1
VS-
2
2
4
11
Negative supply voltage
V
CAPACITIVELY
TRIGGERED
ESD CLAMP
VCIRCUIT 2
IN+
IN+_A
IN+_B
IN+_C
IN+_D
1
ININ-_A
IN-_B
IN-_C
IN-_D
3
VS+
5
Positive Input
3
3
5
3
5
10
12
V+
IN-
IN+
Negative Input
4
2
6
5
8
3
2
6
9
13
4
VCIRCUIT 3
Positive supply voltage
See Circuit 2
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Absolute Maximum Ratings (TA = +25°C)
Supply Voltage. . . . . . . . . . . . . .
Supply Turn-on Voltage Slew Rate
Differential Input Current . . . . . .
Differential Input Voltage . . . . . .
Input Voltage. . . . . . . . . . . . . . .
ESD Rating
Human Body Model . . . . . . . . .
Machine Model
ISL28113, ISL28213 . . . . . . .
ISL28413. . . . . . . . . . . . . . .
Charged Device Model . . . . . . .
.
.
.
.
.
.
.
.
.
.
............
............
............
............
. V- - 0.5V to V+
Thermal Information
Thermal Resistance (Typical)
. .6.5V
. 1V/µs
. 20mA
. 0.5V
+ 0.5V
θJA (°C/W)
θJC (°C/W)
5 Ld SC-70 (Notes 4, 5) . . . . . . . .
250
N/A
5 Ld SOT-23 (Notes 4, 5) . . . . . . .
225
N/A
8 Ld MSOP (Notes 4, 5) . . . . . . . .
180
100
8 Ld SOIC Package (Notes 4, 5) . .
126
90
8 Ld SOT-23 . . . . . . . . . . . . . . . .
TBD
TBD
14 Ld TSSOP Package (Notes 4, 5)
120
40
14 Ld SOIC Package (Notes 4, 5) .
90
50
Ambient Operating Temperature Range. . . . -40°C to +125°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
. . . . . . . . . . . . . . 4000V
. . . . . . . . . . . . . . . 350V
. . . . . . . . . . . . . . . 400V
. . . . . . . . . . . . . . 2000V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For θJC, the “case temp” location is the top of the package.
Electrical Specifications
PARAMETER
VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C,
unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-5
0.5
5
mV
6
mV
2
10
µV/°C
1
30
pA
3
20
pA
100
pA
20
pA
-50
50
pA
- 0.1V
+5.1V
V
DC SPECIFICATIONS
VOS
Input Offset Voltage
-6
TCVOS
Input Offset Voltage
Temperature Coefficient
IOS
Input Offset Current
IB
Input Bias Current
-40°C to +125°C
ISL28113
-20
-100
ISL28213, ISL28413
Common Mode Input
Voltage Range
-20
3
ZIN
Input Impedance
1012
Ω
CIN
Input Capacitance
1
pF
CMRR
Common Mode Rejection Ratio VCM = -0.1V to 5.1V
72
dB
70
dB
71
dB
70
dB
4.993
V
PSRR
VOH
Power Supply Rejection Ratio
Output Voltage Swing, High
Vs =1.8V to 5.5V
RL = 10kΩ
4.985
4.98
VOL
V+
Output Voltage Swing, Low
Supply Voltage
4
V
13
RL = 10kΩ
1.8
15
mV
20
mV
5.5
V
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Electrical Specifications
PARAMETER
IS
VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C,
unless otherwise specified.
DESCRIPTION
Supply Current per Amplifier
CONDITIONS
RL = OPEN
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
90
130
µA
170
µA
ISC+
Output Source Short Circuit
Current
RL = 10Ω to V-
-22
mA
ISC-
Output Sink Short Circuit
Current
RL = 10Ω to V+
16
mA
2
MHz
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
VS = ±2.5V
AV = 100, RF = 100kΩ,
RG = 1kΩ, RL = 10kΩ to
VCM
eN VP-P
Peak-to-Peak Input Noise
Voltage
VS = ±2.5V
f = 0.1Hz to 10Hz
14
µVP-P
eN
Input Noise Voltage Density
VS = ±2.5V
f = 1kHz
55
nV/√(Hz)
iN
Input Noise Current Density
VS = ±2.5V
f = 1kHz
5
fA/√(Hz)
Cin
Differential Input Capacitance
VS = ±2.5V
f = 1MHz
1.0
pF
1.3
pF
1
V/µs
100
ns
115
ns
7.5
µs
Common Mode Input
Capacitance
TRANSIENT RESPONSE
SR
Slew Rate 20% to 80% VOUT
VOUT = 0.5V to 4.5V
tr, tf, Small Signal
Rise Time, tr 10% to 90%
VS = ±2.5V
AV = +1, VOUT = 0.05VP-P,
RF = 0Ω, RL = 10kΩ,
CL = 15pF
Fall Time, tf 10% to 90%
ts
Settling Time to 0.1%, 4VP-P
Step
VS = ±2.5V
AV = +1, RF = 0Ω,
RL = 10kΩ, CL = 1.2pF
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
5
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Typical Performance Curves
VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise
specified.
INPUT NOISE VOLTAGE (nV/√Hz)
50
40
30
10
0
-10
-20
-30
-40
SIMULATION
-50
-40
-20
0
20
40
60
80
100
120
140
V+ = ±2.5V
AV = 1
1000
100
10
1
10
100
TEMPERATURE (°C)
10k
100k
FIGURE 2. INPUT NOISE VOLTAGE SPECTRAL
DENSITY
20
120
20
100
0
100
0
-20
80
GAIN
60
-40
40
-60
20
-80
0
-100
-20 V+ = ±0.9V
RL = 100k
-40
CL = 10pF
-60 SIMULATION
-80
0.1
1
10
-120
PHASE
-140
OPEN LOOP GAIN (dB)
120
PHASE (°)
OPEN LOOP GAIN (dB)
FIGURE 1. INPUT BIAS CURRENT vs TEMPERATURE
-160
100
1k
10k 100k
FREQUENCY (Hz)
1M
80
-60
20
-80
0
-20
-40
60
60
50
50
PSRR (dB )
70
10
0
0.01
SIMULATION
0.1
1
10
100 1k 10k 100k 1M
FREQUENCY (Hz)
10M 100M
FIGURE 5. CMRR vs FREQUENCY, VS = ±2.5
6
1
10
-120
PHASE
RL = 100k
CL = 10pF
SIMULATION
-140
-160
100
1k
10k 100k
FREQUENCY (Hz)
1M
-180
10M 100M
FIGURE 4. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
RL = 100kΩ, CL = 100F, VS = ±2.5V
70
20
-100
V+ = ±2.5V
-80
0.1
80
30
-40
40
80
40
-20
GAIN
60
-60
-180
10M 100M
FIGURE 3. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
RL = 100kΩ, CL = 10pF, VS = ±0.9V
CMRR (dB)
1k
FREQUENCY (Hz)
PHASE (°)
IBIAS (pA)
20
10,000
PSRR- VS = ±2.5V
PSRR- VS = ±0.9V
PSRR+ VS = ±0.9V
40
30
PSRR+ VS = ±2.5V
RL = INF
20 C = 4pF
L
10 AV = +1
VCM = 100mVP-P
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 6. PSRR vs FREQUENCY, VS = ±0.9V, ±2.5V
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Typical Performance Curves
70
GAIN (dB)
V+ = ±2.5V
CL = 4pF
RL = 10k
VOUT = 50mVP-P
AV = 100
30
20
AV = 10
Rg = 10k, Rf = 100k
10
0
0
Rg = 1k, Rf = 100k
50
40
1
Rg = 100, Rf = 100k
AV = 1000
NORMALIZED GAIN (dB)
60
VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
AV = 1
1k
100
10k
100k
1M
FREQUENCY (Hz)
10M
VOUT = 10mVP-P
-4
VOUT = 50mVP-P
-7
6
0
5
RL = 49.9k
-2
RL = 10k
-3
-4
RL = 4.99k
-5
-6
-7
-8
V+ = ±2.5V
RL = 1k
CL = 4pF
AV = +1
VOUT = 50mVP-P
-9
100
1k
RL = 499
RL = 100
10k
100k
FREQUENCY (Hz)
1M
1k
VOUT = 200mVP-P
VOUT = 500mVP-P
VOUT = 1VP-P
10k
100k
FREQUENCY (Hz)
4
1M
10M
10M
CL = 1004pF
3
CL = 474pF
2
CL = 224pF
1
0
-1 VS = ±2.5V
RL = 10k
-2
AV = +1
-3 VOUT = 50mVP-P
-4
10k
1k
CL = 104pF
CL = 26pF
CL = 4pF
100k
FREQUENCY (Hz)
1M
10M
FIGURE 10. GAIN vs FREQUENCY vs CL
FIGURE 9. GAIN vs FREQUENCY vs RL
1
140
0
120
CROSS-TALK (dB)
-1
-2
-3
-4
-5
VS = ±2.5V
-6 CL = 4pF
RL = 10k
-7
AV = +1
-8 VOUT = 50mVP-P
VS = ±1.75V
-9
10k
VS = ±2.5V
CL = 4pF
AV = +1
RL = 10k
-6
1
-1
VOUT = 100mVP-P
-5
FIGURE 8. FREQUENCY RESPONSE vs VOUT
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
-3
-9
100
100M
FIGURE 7. FREQUENCY RESPONSE vs CLOSED LOOP
GAIN
NORMALIZED GAIN (dB)
-2
-8
Rg = OPEN, Rf = 0
-10
10
-1
VS = ±1.25V
FIGURE 11. GAIN vs FREQUENCY vs SUPPLY
VOLTAGE
7
80
VS = ±2.5V
60
RL-DRIVER = INF
RL-RECEIVER = 10k
CL = 4pF
AV = +1
VSOURCE = 1VP-P
40
20
VS = ±0.9V
100k
1M
FREQUENCY (Hz)
100
10M
0
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 12. CROSSTALK, VS = ±2.5V
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
3
20
2
LARGE SIGNAL (V)
30
10
VS = ±2.5V
RL = 10k
CL = 15pF
AV = +1
VOUT = 50mVP-P
-10
-20
-30
1
VS = ±0.9V
0
RL = 10k
CL = 15pF
AV = +1
VOUT = RAIL
-1
-2
0
200
400
600
-3
800 1000 1200 1400 1600 1800 2000
TIME (ns)
0.5
INPUT
0
RL = INF
CL = 15pF
AV =10
Rf = 9.09k, Rg = 1k
-0.1
-0.2
-0.3
OUTPUT @ VS = ±2.5V
-0.4
0
0.5
-0.5
0.4
-1.0
-1.5
OUTPUT @ VS=±0.9V
-0.5
2
4
6
8
10
12
TIME (ms)
14
16
18
20
0.6
OUTPUT (V)
0.1
0
FIGURE 14. LARGE SIGNAL TRANSIENT RESPONSE vs
RL VS = ±0.9V, ±2.5V
FIGURE 13. SMALL SIGNAL TRANSIENT RESPONSE,
VS = ±2.5V
INPUT (V)
VS = ±2.5V
3.0
OUTPUT @ VS = ±2.5V
-2.5
0
1.5
RL = INF
CL = 15pF
AV =10
Rf = 9.09k, Rg = 1k
0.2
0.1
2.0
OUTPUT @ VS=±0.9V
0.3
-2.0
2.5
OUTPUT (V)
0
INPUT (V)
SMALL SIGNAL (mV)
Typical Performance Curves
1.0
0.5
0
INPUT
-0.6
0
1
2
3
4
5
6
TIME (ms)
7
8
9
-3.0
10
FIGURE 15. NEGATIVE OUTPUT OVERLOAD
RESPONSE TIME, VS = ±0.9V, ±2.5V
-0.1
0
1
2
3
4
5
6
TIME (ms)
7
8
9
-0.5
10
FIGURE 16. POSITIVE OUTPUT OVERLOAD
RESPONSE TIME, VS = ±0.9V, ±2.5V
VS = ±2.5V
80 RL = 10k
AV = 1
70 V
OUT = 50mVP-P
60
50
40
30
20
O
V
ER
O
SH
V
ER
O
O
SH
T
O
+
O
T
-
OVERSHOOT (%)
90
10
0
10
100
1k
CAPACITANCE (pF)
10k
FIGURE 17. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±2.5V
8
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Applications Information
Functional Description
The ISL28113, ISL28213 and ISL28413 are single, dual
and quad, CMOS rail-to-rail input, output (RRIO)
micropower operational amplifiers. They are designed to
operate from single supply (1.8V to 5.5V) or dual supply
(±0.9V to ±2.75V). The parts have an input common
mode range that extends 100mV above and below the
power supply voltage rails. The output stage can swing to
within 15mV of the supply rails with a 10kΩ load.
Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load, power supply
conditions and ambient temperature conditions. It is
therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if
power supply voltages, load conditions, or package type
need to be modified to remain in the safe operating area.
These parameters are related using Equation 1:
(EQ. 1)
T JMAX = T MAX + θ JA xPD MAXTOTAL
Input ESD Diode Protection
where:
All input terminals have internal ESD protection diodes
to both positive and negative supply rails, limiting the
input voltage to within one diode beyond the supply
rails. They also contain back-to-back diodes across the
input terminals (see “Pin Descriptions - Circuit 1” on
page 3). For applications where the input differential
voltage is expected to exceed 0.5V, an external series
resistor must be used to ensure the input currents
never exceed 20mA (see Figure 18).
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using
Equation 2:
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------R
L
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
VIN
RIN
VOUT
RL
+
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
FIGURE 18. INPUT CURRENT LIMITING
• IqMAX = Maximum quiescent supply current of 1
amplifier
Although the amplifier is fully protected, high input slew
rates that exceed the amplifier slew rate (±1V/µs) may
cause output distortion.
• VOUTMAX = Maximum output voltage swing of the
application
Output Phase Reversal
• RL = Load resistance
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28113, ISL28213
and ISL28413 are immune to output phase reversal,
even when the input voltage is 1V beyond the supplies.
ISL28113, ISL28213 and ISL28413 SPICE
Model
Unused Channels
If the application requires less than all amplifiers one
channel, the user must configure the unused channel(s)
to prevent it from oscillating. The unused channel(s) will
oscillate if the input and output pins are floating. This will
result in higher than expected supply currents and
possible noise injection into the channel being used. The
proper way to prevent this oscillation is to short the
output to the inverting input and ground the positive
input (as shown in Figure 19).
Figure 20 shows the SPICE model schematic and
Figure 21 shows the net list for the SPICE model. The
model is a simplified version of the actual device and
simulates important AC and DC parameters. AC
parameters incorporated into the model are: 1/f and
flatband noise, Slew Rate, CMRR, Gain and Phase. The
DC parameters are IOS, total supply current and output
voltage swing. The model uses typical parameters given
in the “Electrical Specifications” Table beginning on
page 4. The AVOL is adjusted for 85dB with the
dominate pole at 100Hz. The CMRR is set 72dB,
f = 35kHz). The input stage models the actual device to
present an accurate AC representation. The model is
configured for ambient temperature of +25°C.
Figures 22 through 31 show the characterization vs
simulation results for the Noise Voltage, Closed Loop
Gain vs Frequency, Large Signal 5V Step Response,
CMRR and Open Loop Gain Phase.
+
FIGURE 19. PREVENTING OSCILLATIONS IN
UNUSED CHANNELS
9
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
LICENSE STATEMENT
The information in this SPICE model is protected under
the United States copyright laws. Intersil Corporation
hereby grants users of this macro-model hereto referred
to as “Licensee”, a nonexclusive, nontransferable licence
to use this model as long as the Licensee abides by the
terms of this agreement. Before using this macro-model,
the Licensee should read this license. If the Licensee
does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to
anyone outside the Licensee’s company. The Licensee
may modify the macro-model to suit his/her specific
applications, and the Licensee may make copies of this
macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND
WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED
OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with
or arising out of the use of this macro-model. Intersil
reserves the right to make changes to the product and
the macro-model without prior notice.
10
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
En
Vin+
+
Voltage Noise Stage
+
R21
800E3
28
V++
29 DN
D13
+
+
-
0.00035V
En
R22
5E11
+
CinDiff
R23
5E11
-
2
+
-
EOS
1.02pF
R2
R1
1.0004 1.0004
3
Vc
Vmid
1
In+
I2
5E-3
V1
1E-6V
9
M16
5
M14
R4
10
6
11
R7
1
M15
Cin1
Cin2
1.26pF
1.26pF
100
25E-12
-
V--
4
15
DX
D2
5
RA2
1
G2A
+1E-6V
IOS
DX
D1
R9
14
13
I1
5E-3
R10
1E9
RA1
1
M17
R8
1
7
Vin-
+
-
R6
10
12
R5
10
4
R3
10
10
8
G1A
Vc
+
-
V9
V2
Vmid
V-VCM
1ST Gain Stage
Input Stage
V++
G1
17
+
-
4
5
D3
DX
+
V3
- 0.61V
G3
19
+
-
R11
1
318.329E3
D5
DX
+
V5
G5
R13
- 0.604V
+
-
C2
5.0nF
21
Vc
Vg
R12
1
G2
+
-
18
V--
-
V4
0.61V
+
-
+
G4
D4
DX
20
C3
0.604V
+
V6
5.0nF
-
R14
D6
DX
R16
1E6
G6
E4
+
-
Vg
Vmid
22
+
-
Vmid
4.5474
R15
1E6
Vmid
16
Vc
V++
L1
+
-
L2
4.5474
318.329E3
V-VCM
VCM
1ST Gain Stage (Cont)
2nd Gain Stage
Mid Supply Ref
Common Mode Gain Stage
V++
+
-
+
-
E2
D9
DX
D10
DX
26
R17
5305.32
ISY
90uA
Vg
C4
10pF
D7
DX
27
24
G11
+
V7
0.08V
23
DX
R18
V8
25
+
D8
-
Vmid
V-
V--
+
+
E3
V-
C3
G8
Supply Isolation Stage
10pF
Pole Stage
0.08V
G12
5305.32
+
D11
DY
+
G9
+
-
R19
50
-
+
-
+
V+
D12
DY
VOUT
VOUT
R20
50
+
-
G7
V+
G10
Output Stage
FIGURE 20. SPICE SCHEMATIC
11
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
* source ISL28113_SPICEmodel
* Revision D, LaFontaine February 22, 2010 Improved noise
performance
* Model for Noise, supply currents, CMRR 72dB f=35kHz ,AVOL 85dB
f=100Hz
* SR = 1.0V/us, GBWP 2MHz, 2nd pole 3MHz Output voltage clamp
and short ckt I limit
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections:
+input
*
|
-input
*
|
|
+Vsupply
*
|
|
|
-Vsupply
*
|
|
|
|
output
*
|
|
|
|
|
.subckt ISL28113subckt
Vin+ Vin- V+
VVOUT
* source ISL28113_DS rev1
*
*Voltage Noise
E_En
VIN+ EN 28 0 1
D_D13
29 28 DN
V_V9
29 0 0.45
R_R21
28 0 30
*
*Input Stage
M_M14
3 1 5 5 NCHANNELMOSFET
M_M15
4 VIN- 6 6 NCHANNELMOSFET
M_M16
11 VIN- 9 9 PMOSISIL
M_M17
12 1 10 10 PMOSISIL
I_I1
7 V-- DC 5e-3
I_I2
V++ 8 DC 5e-3
I_IOS
VIN- 1 DC 25e-12
G_G1A
V++ 14 4 3 1404
G_G2A
V-- 14 11 12 1404
V_V1
V++ 2 1e-6
V_V2
13 V-- 1e-6
R_R1
3 2 1.0004
R_R2
4 2 1.0004
R_R3
5 7 10
R_R4
7 6 10
R_R5
9 8 10
R_R6
8 10 10
R_R7
13 11 1
R_R8
13 12 1
R_RA1
14 V++ 1
R_RA2
V-- 14 1
C_CinDif
VIN- EN 1.02E-12
C_Cin1
V-- EN 1.26e-12
C_Cin2
V-- VIN- 1.26e-12
*
*1st Gain Stage
G_G1
V++ 16 15 VMID 334.753e-3
G_G2
V-- 16 15 VMID 334.753e-3
V_V3
17 16 .61
V_V4
16 18 .61
D_D1
15 VMID DX
D_D2
VMID 15 DX
D_D3
17 V++ DX
D_D4
V-- 18 DX
R_R9
15 14 100
R_R10
15 VMID 1e9
R_R11
16 V++ 1
R_R12
V-- 16 1
*
*2nd Gain Stage
G_G3
V++ VG 16 VMID 24.893e-3
G_G4
V-- VG 16 VMID 24.893e-3
V_V5
19 VG .604
V_V6
VG 20 .604
D_D5
19 V++ DX
D_D6
V-- 20 DX
R_R13
VG V++ 318.329e3
R_R14
V-- VG 318.329e3
C_C2
VG V++ 5E-09
C_C3
V-- VG 5E-09
*
*Mid supply Ref
E_E4
VMID V-- V++ V-- 0.5
E_E2
V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
I_ISY
V+ V- DC 90e-6
*
*Common Mode Gain Stage with Zero
G_G5
V++ VC VCM VMID 0.25118
G_G6
V-- VC VCM VMID 0.25118
E_EOS
1 EN VC VMID 1
R_R15
VC 21 0.001
R_R16
22 VC 0.001
R_R22
EN VCM 5e11
R_R23
VCM VIN- 5e11
L_L1
21 V++ 4.547418E-09
L_L2
22 V-- 4.547418E-09
*
*Pole Stage
G_G7
V++ 23 VG VMID 0.18849
G_G8
V-- 23 VG VMID 0.18849
R_R17
23 V++ 5.30532
R_R18
V-- 23 5.30532
C_C4
23 V++ 1e-8
C_C5
V-- 23 1e-8
*
*Output Stage with Correction Current Sources
G_G9
26 V-- VOUT 23 0.02
G_G10
27 V-- 23 VOUT 0.02
G_G11
VOUT V++ V++ 23 0.02
G_G12
V-- VOUT 23 V-- 0.02
V_V7
24 VOUT .08
V_V8
VOUT 25 .08
D_D7
23 24 DX
D_D8
25 23 DX
D_D9
V++ 26 DX
D_D10
V++ 27 DX
D_D11
V-- 26 DY
D_D12
V-- 27 DY
R_R19
VOUT V++ 50
R_R20
V-- VOUT 50
.model pmosisil pmos (kp=16e-3 vto=-0.6)
.model NCHANNELMOSFET nmos (kp=3e-3 vto=0.6)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28113subckt
FIGURE 21. SPICE NET LIST
12
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Characterization vs Simulation Results
10,000
10,000
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
V+ = ±2.5V
AV = 1
1000
100
10
1
10
100
1k
FREQUENCY (Hz)
10k
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 23. SIMULATED INPUT NOISE VOLTAGE
(A) AC sims.dat (active)
60
AV = 10
20
GAIN (dB)
30
40
20
Rg = 10k, Rf = 100k
10
AV = 1
0
0
Rg = OPEN, Rf = 0
-10
10
1k
100
10k
100k
1M
FREQUENCY (Hz)
10M
-10
100M
FIGURE 24. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
10
100
VS = ±2.5V
LARGE SIGNAL (V)
VS = ±0.9V
RL = 10k
CL = 15pF
AV = +1
VOUT = RAIL
-1
-2
0
2
4
6
8
10
14
16
TIME (ms)
FIGURE 26. CHARACTERIZED LARGE SIGNAL
TRANSIENT RESPONSE vs RL,
VS = ±0.9V, ±2.5V
13
18
20
100M
VS = ±2.5V
1
VIN
-0
RL = 10k
CL = 15pF
AV = +10
VOUT = RAIL
-1
-2
12
10M
VOUT
2
1
0
10k
100k
1.0M
FREQUENCY (Hz)
(A) AC sims.dat (active)
3
2
1.0k
FIGURE 25. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
3
LARGE SIGNAL (V)
10
70
V+ = ±2.5V
CL = 4pF
RL = 10k
VOUT = 50mVP-P
AV = 100
40
-3
1
Rg = 1k, Rf = 100k
50
GAIN (dB)
10
Rg = 100, Rf = 100k
AV = 1000
60
100
100k
FIGURE 22. CHARACTERIZED INPUT NOISE VOLTAGE
70
1000
-3
0
5
10
15
TIME (µs)
20
25
30
FIGURE 27. SIMULATED LARGE SIGNAL TRANSIENT
RESPONSE vs RL, VS = ±0.9V, ±2.5V
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
20
100
0
80
-20
GAIN
60
-40
40
-60
20
-80
0
-100
-20 V+ = ±2.5V
RL = 100k
-40
CL = 10pF
-60 SIMULATION
-80
0.1
1
10
PHASE (°)
OPEN LOOP GAIN (dB)
120
-120
PHASE
-140
-160
100
1k
10k 100k
FREQUENCY (Hz)
1M
-180
10M 100M
FIGURE 28. SIMULATED (DESIGN) OPEN-LOOP GAIN,
PHASE vs FREQUENCY
OPEN LOOP GAIN (dB)/PHASE (°)
Characterization vs Simulation Results (Continued)
(A) AC sims.dat (active)
200
160
120
80
40
0
0.01
0.1
1.0
10
100 1.0k 10k 100k 1.0M 10M 100M
FREQUENCY (Hz)
FIGURE 29. SIMULATED (SPICE) OPEN-LOOP GAIN,
PHASE vs FREQUENCY
(A) AC sims.dat (active)
80
80
70
60
50
CMRR (dB )
CMRR (dB)
60
40
30
40
20
20
10
SIMULATION
0
0.01
0.1
1
10
100 1k 10k 100k 1M
FREQUENCY (Hz)
10M 100M
FIGURE 30. SIMULATED (DESIGN) CMRR
14
0
0.01
0.1
1.0
10
100 1.0k 10k 100k 1.0M 10M 100M
FREQUENCY (Hz)
FIGURE 31. SIMULATED (SPICE) CMRR
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
Web to make sure you have the latest Rev.
DATE
REVISION
3/23/10
FN6728.4
CHANGE
Page 1, 2nd paragraph - Added “...SOT23-8 packages...” and changed “SO8” to “SOIC8”.
Also global, changed S08 to SOIC8
On page 2, Ordering Information table: Part Number ISL28213FEZ changed to ISL28213FHZ and Part
Marking changed to "TBD"
3/22/10
-Added Related Literature on page 1, updated ordering information by adding Eval boards.
-Added to ordering information part number ISL28213FHZ 8 Ld SOT-23 Package as coming soon.
-Replaced Figure 23 Simulated Input Noise Voltage with following changes:
Y-axis from “10 to 100” to “10,000 to 10”
Removed (A) AC sims.dat (active) from top of graph
Curve changed to improve noise performance
Made changes to Spice Net List as follows:
-Changed Revision from “C” to “D” and added improved noise performance to Revision line.
-Changed in Voltage Noise
“V_V9 29 0 .00035” to “V_V9 29 0 0.45”
“R_R21
28 0 800E3 TC=0,0” to “R_R21
28 0 30”
-Removed TC=0 in Input Stage from R_R1 through C_Cin2
-Removed TC=0 in 1st Gain Stage from R_R9 through R_R12
-Removed TC=0 in 2nd Gain Stage from R_R13 through C_C3
-Changed in Common Mode Gain Stage with Zero
“G_G5
V++ VC VCM VMID 2.5118E-10” to “G_G5
V++ VC VCM VMID 0.25118”
“G_G6
V-- VC VCM VMID 2.5118E-10” to “G_G6
V-- VC VCM VMID 0.25118”
Removed TC=0 from R_R16 through R_R23
-Changed in Pole Stage
“G_G7
V++ 23 VG VMID 188.49e-6” to ‘G_G7
V++ 23 VG VMID 0.18849”
“G_G8
V-- 23 VG VMID 188.49e-6” to “G_G8
V-- 23 VG VMID 0.18849”
Removed TC=0 from R_R17 through C_C5
Removed TC=0 in Output Stage with Correction Current Sources from R_R19 and R_R20
Made changes to Spice Schematic Figure 20 as follows:
-Input Stage - Modified connection to the EOS (voltage control voltage source)
-Added to Thermal Information 8 LD SOT-23 as TBD
-Added to pin configuration for the ISL28213 8 Ld SOT-23
12/16/09
FN6728.3
Removed “Coming Soon” from MSOP package options in the “Ordering Information” on page 2.
Updated the Theta JA for the MSOP package option from 170°C/W to 180°C/W on page 4.
11/17/09
FN6728.2
Removed “Coming Soon” from SC70 and SOT-23 package options in the “Ordering Information” on
page 2.
11/12/09
FN6728.1
Changed theta Ja to 250 from 300. Added license statement (page 10) and reference in spice model
(page 12).
10/26/09
FN6728.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL28113, ISL28213, ISL28413
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
15
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Small Outline Transistor Plastic Packages (SC70-5)
P5.049
D
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
INCHES
5
SYMBOL
4
E
CL
1
2
CL
3
e
E1
b
CL
0.20 (0.008) M
C
C
CL
A
A2
SEATING
PLANE
A1
-C-
PLATING
b1
0.043
0.80
1.10
-
0.004
0.00
0.10
-
A2
0.031
0.039
0.80
1.00
-
b
0.006
0.012
0.15
0.30
-
b1
0.006
0.010
0.15
0.25
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.009
0.08
0.20
6
D
0.073
0.085
1.85
2.15
3
E
0.071
0.094
1.80
2.40
-
E1
0.045
0.053
1.15
1.35
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0512 Ref
1.30 Ref
-
L2
c1
NOTES
0.031
0.010
0.018
0.017 Ref.
0.26
0.46
4
0.420 Ref.
0.006 BSC
0o
N
c
MAX
0.000
α
WITH
MIN
A
L
b
MILLIMETERS
MAX
A1
L1
0.10 (0.004) C
MIN
-
0.15 BSC
8o
0o
5
8o
-
5
5
R
0.004
-
0.10
-
R1
0.004
0.010
0.15
0.25
Rev. 3 7/07
NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
α
L2
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
4X θ1
VIEW C
0.4mm
0.75mm
2.1mm
0.65mm
TYPICAL RECOMMENDED LAND PATTERN
16
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
TOLERANCE
Rev. F 2/07
NOTES:
C
A2
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
NX
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
17
0.25
0° +3°
-0°
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
3.0±0.1
8
A
0.25
CAB
3.0±0.1
4.9±0.15
DETAIL "X"
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
0.18 ± 0.05
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
H
GAUGE
PLANE
C
0.25
SEATING PLANE
0.33 +0.07/ -0.08
0.08 C A B
0.10 ± 0.05
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
4.40
3.00
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
4.
Plastic interlead protrusions of 0.25mm max per side are not
included.
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
6.
This replaces existing drawing # MDP0043 MSOP 8L.
0.65
0.40
1.40
TYPICAL RECOMMENDED LAND PATTERN
18
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
19
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
20
FN6728.4
March 25, 2010
ISL28113, ISL28213, ISL28413
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
MILLIMETERS
(N/2)+1
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
E
E1
1
(N/2)
B
0.20 C B A
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
SEATING
PLANE
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
0.10 M C A B
b
0.10 C
N LEADS
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
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21
FN6728.4
March 25, 2010