INTEGRATED CIRCUITS DATA SHEET 74LVC1G80 Single D-type flip-flop; positive-edge trigger Product specification Supersedes data of 2004 Jun 29 2004 Sep 10 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 V to 5.5 V The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. • High noise immunity • Complies with JEDEC standard: Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V). This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. • ±24 mA output drive (VCC = 3.0 V) • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop. – MM EIA/JESD22-A115-A exceeds 200 V. • CMOS low power consumption Information on the data input is transferred to the Q output pin on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V • Multiple package options • Specified from −40 °C to +85 °C and −40 °C to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay CP to Q fmax maximum frequency CI input capacitance CPD power dissipation capacitance per buffer CONDITIONS UNIT VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ 3.4 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.3 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.5 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.4 ns VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 1.8 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 350 MHz 5.0 pF VCC = 3.3 V; notes 1 and 2 17 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2004 Sep 10 TYPICAL 2 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 FUNCTION TABLE See note 1. INPUT OUTPUT CP D Q ↑ L H ↑ H L L X q Note 1. H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care; q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING 74LVC1G80GW −40 °C to +125 °C 5 SC-88A plastic SOT353-1 VT 74LVC1G80GV −40 °C to +125 °C 5 SC-74A plastic SOT753 V80 74LVC1G80GM −40 °C to +125 °C 6 XSON6 plastic SOT886 VT PIN TSSOP5; SC-74A PIN XSON6 SYMBOL 1 1 D input D 2 2 CP clock pulse input CP 3 3 GND ground (0 V) 4 4 Q output Q - 5 n.c. not connected 5 6 VCC supply voltage PINNING 2004 Sep 10 3 DESCRIPTION Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 80 D 1 CP 2 GND 3 5 VCC 80 4 Q D 1 6 VCC CP 2 5 n.c. GND 3 4 Q 001aab662 001aab663 Transparent top view Fig.1 Pin configuration TSSOP5 and SC-74A. Fig.2 Pin configuration XSON6. handbook, halfpage handbook, halfpage 1 D Q 4 1 4 2 2 CP MNA650 MNA649 Fig.3 Logic symbol. 2004 Sep 10 Fig.4 IEE/IEC logic symbol. 4 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger handbook, full pagewidth CP 74LVC1G80 C C D C C TG TG C C C Q C TG TG C C Fig.5 Logic diagram. 2004 Sep 10 5 MNA651 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage active mode 0 VCC V VCC = 0 V; Power-down mode 0 5.5 V Tamb operating ambient temperature −40 +125 °C tr, tf input rise and fall times VCC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 5.5 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. −0.5 MAX. VCC supply voltage IIK input diode current VI < 0 V − −50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 V − ±50 mA VO output voltage IO output source or sink current +6.5 UNIT V active mode; note 1 −0.5 VCC + 0.5 V Power-down mode; note 1 −0.5 +6.5 V VO = 0 V to VCC − ±50 mA ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 250 mW Tamb = −40 °C to +125 °C Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2004 Sep 10 6 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = −40 °C to +85 °C; note 1 VIH VIL VOL VOH 1.65 to 1.95 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V 2.7 to 3.6 2.0 − − V 4.5 to 5.5 0.7 × VCC − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V 4.5 to 5.5 − − 0.3 × VCC V IO = 100 µA 1.65 to 5.5 − − 0.1 V IO = 4 mA 1.65 − − 0.45 V IO = 8 mA 2.3 − − 0.3 V IO = 12 mA 2.7 − − 0.4 V IO = 24 mA 3.0 − − 0.55 V IO = 32 mA 4.5 − − 0.55 V HIGH-level input voltage LOW-level input voltage LOW-level output voltage HIGH-level output voltage VI = VIH or VIL VI = VIH or VIL IO = −100 µA 1.65 to 5.5 VCC − 0.1 − − V IO = −4 mA 1.65 1.2 − − V IO = −8 mA 2.3 1.9 − − V IO = −12 mA 2.7 2.2 − − V IO = −24 mA 3.0 2.3 − − V IO = −32 mA 4.5 3.8 − − V ILI input leakage current VI = 5.5 V or GND 5.5 − ±0.1 ±5 µA Ioff power OFF leakage current VI or VO = 5.5 V 0 − ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − 0.1 10 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 0.6 V; IO = 0 A 2.3 to 5.5 − 5 500 µA 2004 Sep 10 7 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 °C to +125 °C VIH VIL VOL VOH 1.65 to 1.95 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V 2.7 to 3.6 2.0 − − V 4.5 to 5.5 0.7 × VCC − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V 4.5 to 5.5 − − 0.3 × VCC V IO = 100 µA 1.65 to 5.5 − − 0.1 V IO = 4 mA 1.65 − − 0.7 V IO = 8 mA 2.3 − − 0.45 V IO = 12 mA 2.7 − − 0.60 V IO = 24 mA 3.0 − − 0.80 V IO = 32 mA 4.5 − − 0.80 V IO = −100 µA 1.65 to 5.5 VCC − 0.1 − − V IO = −4 mA 1.65 0.95 − − V IO = −8 mA 2.3 1.7 − − V IO = −12 mA 2.7 1.9 − − V IO = −24 mA 3.0 2.0 − − V HIGH-level input voltage LOW-level input voltage LOW-level output voltage HIGH-level output voltage VI = VIH or VIL VI = VIH or VIL IO = −32 mA 4.5 3.4 − − V ILI input leakage current VI = 5.5 V or GND 5.5 − − ±100 µA Ioff power OFF leakage current VI or VO = 5.5 V 0 − − ±200 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − − 200 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 0.6 V; IO = 0 A 2.3 to 5.5 − − 5000 µA Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2004 Sep 10 8 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 °C to +85 °C; note 1 tPHL/tPLH tsu th tW fmax propagation delay CP to Q set-up time D to CP hold time D to CP see Figs 6 and 8 see Figs 7 and 8 see Figs 7 and 8 clock pulse with HIGH or LOW see Figs 7 and 8 maximum clock pulse frequency 2004 Sep 10 see Figs 7 and 8 9 1.65 to 1.95 1.0 3.4 9.9 ns 2.3 to 2.7 0.5 2.3 7.0 ns 2.7 0.5 2.5 6.0 ns 3.0 to 3.6 0.9 2.4 5.0 ns 4.5 to 5.5 0.5 1.8 4.5 ns 1.65 to 1.95 2.3 0.8 − ns 2.3 to 2.7 1.5 0.6 − ns 2.7 1.5 0.5 − ns 3.0 to 3.6 1.3 0.4 − ns 4.5 to 5.5 1.1 0.5 − ns 1.65 to 1.95 0 −0.6 − ns 2.3 to 2.7 0 −0.4 − ns 2.7 +0.5 −0.2 − ns 3.0 to 3.6 0.9 0.2 − ns 4.5 to 5.5 +0.5 −0.1 − ns 1.65 to 1.95 3.0 1.1 − ns 2.3 to 2.7 2.5 0.7 − ns 2.7 2.5 0.6 − ns 3.0 to 3.6 2.5 0.6 − ns 4.5 to 5.5 2.0 0.5 − ns 1.65 to 1.95 160 300 − MHz 2.3 to 2.7 160 350 − MHz 2.7 160 350 − MHz 3.0 to 3.6 160 350 − MHz 4.5 to 5.5 200 400 − MHz Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 °C to +125 °C tPHL/tPLH tsu th tW fmax propagation delay CP to Q set-up time D to CP hold time D to CP see Figs 6 and 8 see Figs 7 and 8 see Figs 7 and 8 clock pulse with HIGH or LOW see Figs 7 and 8 maximum clock pulse frequency see Figs 7 and 8 Note 1. All typical values are measured at Tamb = 25 °C. 2004 Sep 10 10 1.65 to 1.95 1.0 − 13.0 ns 2.3 to 2.7 0.5 − 9.0 ns 2.7 0.5 − 8.0 ns 3.0 to 3.6 0.9 − 6.5 ns 4.5 to 5.5 0.5 − 6.0 ns 1.65 to 1.95 2.3 − − ns 2.3 to 2.7 1.5 − − ns 2.7 1.5 − − ns 3.0 to 3.6 1.3 − − ns 4.5 to 5.5 1.1 − − ns 1.65 to 1.95 0 − − ns 2.3 to 2.7 0 − − ns 2.7 0.5 − − ns 3.0 to 3.6 0.9 − − ns 4.5 to 5.5 0.5 − − ns 1.65 to 1.95 3.0 − − ns 2.3 to 2.7 2.5 − − ns 2.7 2.5 − − ns 3.0 to 3.6 2.5 − − ns 4.5 to 5.5 2.0 − − ns 1.65 to 1.95 160 − − MHz 2.3 to 2.7 160 − − MHz 2.7 160 − − MHz 3.0 to 3.6 160 − − MHz 4.5 to 5.5 200 − − MHz Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 AC WAVEFORMS VI handbook, full pagewidth D input GND VI CP input VM VM GND t PHL t PLH VOH VM Q output VM VOL MNA652 INPUT VCC VM 1.65 V to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns VI tr = tf 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 V to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5 × VCC VCC ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 Clock (CP) to output (Q) propagation delay times. 2004 Sep 10 11 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 VI handbook, full pagewidth VM D input GND th th t su t su 1/fmax VI CP input VM GND tW t PHL t PLH VOH VM Q output VOL MNA653 INPUT VCC VM VI tr = tf 1.65 V to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 V to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5 × VCC VCC ≤ 2.5 ns The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 Clock (CP) to output (Q) propagation delays, clock pulse width, D to CP set-up times, the D to CP hold times and maximum clock pulse frequency. 2004 Sep 10 12 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 VEXT VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL mna616 VCC VI CL RL VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ 1.65 V to 1.95 V VCC 30 pF 1 kΩ open GND 2 × VCC 2.3 V to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6V 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 6V 4.5 V to 5.5 V VCC 50 pF 500 Ω open GND 2 × VCC Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.8 Load circuitry for switching times. 2004 Sep 10 13 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 PACKAGE OUTLINES TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 2004 Sep 10 REFERENCES IEC JEDEC JEITA MO-203 SC-88A 14 EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 Plastic surface mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION SOT753 2004 Sep 10 REFERENCES IEC JEDEC JEITA SC-74A 15 EUROPEAN PROJECTION ISSUE DATE 02-04-16 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 2004 Sep 10 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 16 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74LVC1G80 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Sep 10 17 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/06/pp18 Date of release: 2004 Sep 10 Document order number: 9397 750 13767