INTEGRATED CIRCUITS DATA SHEET 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger Product specification Supersedes data of 2004 Sep 09 2005 Feb 01 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 V to 5.5 V The 74LVC1G74 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. • 5 V tolerant inputs for interfacing with 5 V logic • High noise immunity The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V). This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the output, preventing damaging backflow current through the device when it is powered down. • ±24 mA output drive (VCC = 3.0 V) • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. – MM EIA/JESD22-A115-A exceeds 200 V. • CMOS low power consumption • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times. • Multiple package options • Specified from −40 °C to +85 °C and −40 °C to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPHL/tPLH PARAMETER CONDITIONS UNIT propagation delay CP to Q, Q CL = 50 pF; VCC = 3.3 V 3.5 ns SD to Q, Q CL = 50 pF; VCC = 3.3 V 3.0 ns RD to Q, Q CL = 50 pF; VCC = 3.3 V 3.0 ns CL = 50 pF; VCC = 3.3 V 280 MHz 4.0 pF VCC = 3.3 V; notes 1 and 2 15 pF fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2005 Feb 01 TYPICAL 2 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 FUNCTION TABLES Table 1 Asynchronous operation. See note 1. INPUT OUTPUT SD RD CP D Q Q L H X X H L H L X X L H L L X X H H Table 2 Synchronous operation. See note 1. INPUT OUTPUT SD RD CP D Qn+1 Qn+1 H H ↑ L L H H H ↑ H H L Note to Tables 1 and 2 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING 74LVC1G74DP −40 °C to +125 °C 8 TSSOP8 plastic SOT505-2 V74 74LVC1G74DC −40 °C to +125 °C 8 VSSOP8 plastic SOT765-1 V74 74LVC1G74GT −40 °C to +125 °C 8 XSON8 plastic SOT833-1 V74 PINNING SYMBOL PIN DESCRIPTION CP 1 clock input (LOW-to-HIGH, edge-triggered) D 2 data input Q 3 complement flip-flop output GND 4 ground (0 V) Q 5 true flip-flop output RD 6 asynchronous reset-direct input (active LOW) SD 7 asynchronous set-direct input (active LOW) VCC 8 supply voltage 2005 Feb 01 3 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 74 CP 1 8 VCC D 2 7 SD Q 3 6 RD GND 4 5 Q 74 001aab659 CP 1 8 VCC D 2 7 SD Q 3 6 RD GND 4 5 Q 001aab658 Transparent top view Fig.1 Pin configuration TSSOP8 and VSSOP8. Fig.2 Pin configuration XSON8. 7 handbook, halfpage SD 2 1 D CP SD Q D Q handbook, halfpage 5 7 1 2 CP FF Q Q 6 3 S 5 C1 1D 3 R MNB140 RD RD 6 MNB139 Fig.3 Logic symbol. 2005 Feb 01 Fig.4 IEC logic symbol. 4 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 handbook, full pagewidth Q C C C C C C D Q C C RD SD CP MNA421 C C Fig.5 Logic diagram. 2005 Feb 01 5 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage active mode 0 VCC V VCC = 0 V; Power-down mode 0 5.5 V Tamb ambient temperature −40 +125 °C tr, tf input rise and fall times VCC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 5.5 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. −0.5 MAX. VCC supply voltage IIK input diode current VI < 0 V − −50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 V − ±50 mA VO output voltage active mode; notes 1 and 2 −0.5 VCC + 0.5 V Power-down mode; notes 1 and 2 −0.5 IO output source or sink current VO = 0 V to VCC − +6.5 UNIT V +6.5 V ±50 mA ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 250 mW Tamb = −40 °C to +125 °C Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. 2005 Feb 01 6 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = −40 °C to +85 °C; note 1 VIH VIL VOH VOL 1.65 to 1.95 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V 2.7 to 3.6 2.0 − − V 4.5 to 5.5 0.7 × VCC − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V 4.5 to 5.5 − − 0.3 × VCC V IO = −100 µA 1.65 to 5.5 VCC − 0.1 − − V IO = −4 mA 1.65 1.2 1.54 − V IO = −8 mA 2.3 1.9 2.15 − V IO = −12 mA 2.7 2.2 2.50 − V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −24 mA 3.0 2.3 2.62 − V IO = −32 mA 4.5 3.8 4.11 − V IO = 100 µA 1.65 to 5.5 − - 0.10 V IO = 4 mA 1.65 − 0.07 0.45 V IO = 8 mA 2.3 − 0.12 0.30 V IO = 12 mA 2.7 − 0.17 0.40 V IO = 24 mA 3.0 − 0.33 0.55 V IO = 32 mA 4.5 − 0.39 0.55 V VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 5.5 − ±0.1 ±5 µA Ioff power OFF leakage current VI or VO = 5.5 V 0 − ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − 0.1 10 µA ∆ICC additional quiescent supply current per pin VI = VCC − 0.6 V; IO = 0 A 2.3 to 5.5 − 5 500 µA 2005 Feb 01 7 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 °C to +125 °C VIH VIL VOH VOL 1.65 to 1.95 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V 2.7 to 3.6 2.0 − − V 4.5 to 5.5 0.7 × VCC − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V 4.5 to 5.5 − − 0.3 × VCC V IO = −100 µA 1.65 to 5.5 VCC − 0.1 − − V IO = −4 mA 1.65 0.95 − − V IO = −8 mA 2.3 1.7 − − V IO = −12 mA 2.7 1.9 − − V IO = −24 mA 3.0 2.0 − − V IO = −32 mA 4.5 3.4 − − V IO = 100 µA 1.65 to 5.5 − − 0.10 V IO = 4 mA 1.65 − − 0.70 V IO = 8 mA 2.3 − − 0.45 V IO = 12 mA 2.7 − − 0.60 V IO = 24 mA 3.0 − − 0.80 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL 4.5 − − 0.80 V ILI input leakage current VI = 5.5 V or GND 5.5 − − ±20 µA Ioff power OFF leakage current VI or VO = 5.5 V 0 − − ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA ∆ICC additional quiescent supply current per pin VI = VCC − 0.6 V; IO = 0 2.3 to 5.5 − − 5000 µA IO = 32 mA Note 1. All typical values are measured at Tamb = 25 °C. 2005 Feb 01 8 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) WAVEFORMS Tamb = −40 °C to +85 °C; note 1 tPHL/tPLH propagation delay CP to Q, Q propagation delay SD to Q, Q propagation delay RD to Q, Q tW tsu 2005 Feb 01 1.5 6.0 13.4 ns 2.3 to 2.7 1.0 3.5 7.1 ns 2.7 1.0 3.5 7.1 ns 3.0 to 3.6 1.0 3.5(2) 5.9 ns 4.5 to 5.5 1.0 2.5 4.1 ns 1.5 6.0 12.9 ns see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 1.0 3.5 7.0 ns 2.7 1.0 3.5 7.0 ns 3.0 to 3.6 1.0 3.0(2) 5.9 ns 4.5 to 5.5 1.0 2.5 4.1 ns 1.5 5.0 12.9 ns 2.3 to 2.7 1.0 3.5 7.0 ns 2.7 1.0 3.5 7.0 ns 3.0 to 3.6 1.0 3.0(2) 5.9 ns 4.5 to 5.5 1.0 2.5 4.1 ns 6.2 − − ns 2.3 to 2.7 2.7 − − ns 2.7 2.7 − − ns 3.0 to 3.6 2.7 1.3(2) − ns 4.5 to 5.5 2.0 − − ns 6.2 − − ns 2.3 to 2.7 2.7 − − ns 2.7 2.7 − − ns 3.0 to 3.6 2.7 1.6(2) − ns 4.5 to 5.5 2.0 − − ns see Figs 7 and 8 1.65 to 1.95 clock pulse width HIGH or LOW see Figs 6 and 8 1.65 to 1.95 set or reset pulse width LOW trem see Figs 6 and 8 1.65 to 1.95 removal time set or reset set-up time D to CP see Figs 7 and 8 1.65 to 1.95 1.9 − − ns 2.3 to 2.7 1.4 − − ns 2.7 1.3 − − ns 3.0 to 3.6 1.2 −3.0(2) − ns 4.5 to 5.5 1.0 − − ns 2.9 − − ns 2.3 to 2.7 1.7 − − ns 2.7 1.7 − − ns 3.0 to 3.6 1.3 0.5(2) − ns 4.5 to 5.5 1.1 − − ns see Figs 7 and 8 1.65 to 1.95 see Figs 6 and 8 1.65 to 1.95 9 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS th fmax hold time D to CP TYP. MAX. UNIT VCC (V) 0.0 − − ns 2.3 to 2.7 0.3 − − ns 2.7 0.5 − − ns 3.0 to 3.6 1.2 0.6(2) − ns 4.5 to 5.5 0.5 − − ns 80 − − MHz 2.3 to 2.7 175 − − MHz 2.7 175 − − MHz 3.0 to 3.6 175 280(2) − MHz 4.5 to 5.5 200 − − MHz 1.5 − 13.4 ns see Figs 6 and 8 1.65 to 1.95 maximum clock pulse frequency see Figs 6 and 8 1.65 to 1.95 Tamb = −40 °C to +125 °C tPHL/tPLH propagation delay CP to Q, Q propagation delay SD to Q, Q propagation delay RD to Q, Q tW 2.3 to 2.7 1.0 − 7.1 ns 2.7 1.0 − 7.1 ns 3.0 to 3.6 1.0 − 5.9 ns 4.5 to 5.5 1.0 − 4.1 ns 1.5 − 12.9 ns 2.3 to 2.7 1.0 − 7.0 ns 2.7 1.0 − 7.0 ns 3.0 to 3.6 1.0 − 5.9 ns 4.5 to 5.5 1.0 − 4.1 ns 1.5 − 12.9 ns 2.3 to 2.7 1.0 − 7.0 ns 2.7 1.0 − 7.0 ns 3.0 to 3.6 1.0 − 5.9 ns 4.5 to 5.5 1.0 − 4.1 ns 6.2 − − ns 2.3 to 2.7 2.7 − − ns 2.7 2.7 − − ns 3.0 to 3.6 2.7 − − ns 4.5 to 5.5 2.0 − − ns 6.2 − − ns 2.3 to 2.7 2.7 − − ns 2.7 2.7 − − ns 3.0 to 3.6 2.7 − − ns 4.5 to 5.5 2.0 − − ns see Figs 7 and 8 1.65 to 1.95 see Figs 7 and 8 1.65 to 1.95 clock pulse width HIGH or LOW see Figs 6 and 8 1.65 to 1.95 set or reset pulse width LOW 2005 Feb 01 see Figs 6 and 8 1.65 to 1.95 see Figs 7 and 8 1.65 to 1.95 10 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS trem tsu th fmax removal time set or reset set-up time D to CP hold time D to CP 2005 Feb 01 1.9 − − ns − − ns 2.7 1.3 − − ns 3.0 to 3.6 1.2 − − ns 4.5 to 5.5 1.0 − − ns 2.9 − − ns 2.3 to 2.7 1.7 − − ns 2.7 1.7 − − ns 3.0 to 3.6 1.3 − − ns 4.5 to 5.5 1.1 − − ns 0.0 − − ns 2.3 to 2.7 0.3 − − ns 2.7 0.5 − − ns 3.0 to 3.6 1.2 − − ns 4.5 to 5.5 0.5 − − ns 80 − − MHz 2.3 to 2.7 175 − − MHz 2.7 175 − − MHz 3.0 to 3.6 175 − − MHz 4.5 to 5.5 200 − − MHz see Figs 6 and 8 1.65 to 1.95 maximum clock pulse frequency see Figs 6 and 8 1.65 to 1.95 2. These typical values are measured at VCC = 3.3 V. 11 UNIT 1.4 see Figs 6 and 8 1.65 to 1.95 1. All typical values are measured at Tamb = 25 °C. MAX. 2.3 to 2.7 see Figs 7 and 8 1.65 to 1.95 Notes TYP. VCC (V) Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 AC WAVEFORMS VI handbook, full pagewidth VM D input GND th th t su t su 1/fmax VI VM CP input GND tW t PHL t PLH VOH VM Q output VOL VOH Q output VM VOL t PLH t PHL MNB141 The shaded areas indicate when the input is permitted to change for predictable output performance. INPUT VCC VM VI tr = tf 0.5 × VCC VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 V to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5 × VCC VCC ≤ 2.5 ns 1.65 V to 1.95 V VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times and the maximum clock pulse frequency. 2005 Feb 01 12 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 VI handbook, full pagewidth VM CP input GND t rem VI VM SD input GND tW tW VI VM RD input GND t PHL t PLH VOH Q output VM VOL VOH VM Q output VOL t PHL t PLH MNB142 INPUT VCC VM VI tr = tf 1.65 V to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 V to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5 × VCC VCC ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and the RD to CP removal time. 2005 Feb 01 13 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 VEXT VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL mna616 VCC VI CL RL VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ 1.65 V to 1.95 V VCC 30 pF 1 kΩ open GND 2 × VCC 2.3 V to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6V 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 6V 4.5 V to 5.5 V VCC 50 pF 500 Ω open GND 2 × VCC Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.8 Load circuitry for switching times. 2005 Feb 01 14 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 PACKAGE OUTLINES TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 2005 Feb 01 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- 15 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 2005 Feb 01 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 16 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- 2005 Feb 01 17 EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Philips Semiconductors Product specification Single D-type flip-flop with set and reset; positive edge trigger 74LVC1G74 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2005 Feb 01 18 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/03/pp19 Date of release: 2005 Feb 01 Document order number: 9397 750 14529