INTEGRATED CIRCUITS 74LVC377 Octal D-type flip-flop with data enable; positive-edge trigger Product specification Supersedes data of 1996 Jun 06 IC24 Data Handbook 1998 Jul 29 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger FEATURES 74LVC377 DESCRIPTION • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface with TTL levels • Output drive capability 50Ω transmission lines @ 85°C The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC377 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable E is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf 2.5 ns SYMBOL PARAMETER CONDITIONS CL = 50pF VCC = 3.3V TYPICAL UNIT 6.0 ns tPHL/tPLH Propagation delay CP to Qn; fmax Maximum clock frequency 230 MHz CI Input capacitance 5.0 pF CPD Power dissipation capacitance per flip-flop 22 pF VI = GND to VCC1 NOTES: 1 CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 20-Pin Plastic SO –40°C to +85°C 74LVC377 D 74LVC377 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74LVC377 DB 74LVC377 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC377 PW 74LVC377PW DH SOT360-1 PIN CONFIGURATION PIN DESCRIPTION E 1 20 VCC PIN NUMBER SYMBOL Q0 2 19 Q7 1 E D0 3 18 D7 D1 4 17 D6 2, 5, 6, 9, 12, 15, 16, 19 Q0 – Q7 Flip-flop outputs Q1 5 16 Q6 Q2 6 15 Q5 D0 – D7 Data inputs D2 7 14 D5 3, 4, 7, 8, 13, 14, 17, 18 D3 8 13 D4 10 GND Ground (0V) Q3 9 12 Q4 11 CP Clock input (LOW-to-HIGH, edge-triggered) GND 10 11 CP 20 VCC Positive power supply SY00058 1998 Jul 29 2 FUNCTION Data enable input (active LOW) Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74LVC377 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 11 CP 11 E 1 1C2 G1 CP 3 D0 Q0 2 D0 3 2 Q0 4 D1 Q1 5 D1 4 5 Q1 6 D2 7 6 Q2 8 9 D4 13 12 D5 14 15 D6 17 16 Q6 D7 18 19 Q7 7 D2 8 Q2 D3 13 Q3 D4 D3 9 Q4 12 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 2D Q3 Q4 Q5 SY00060 E 1 SY00059 FUNCTION TABLE INPUTS OUTPUT OPERATING MODES CP E Dn Qn Load ‘1’ l h H Load ‘0’ l l L hold (do nothing) X h H X X no change no change H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW-to-HIGH transition X = Don’t care RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN MAX VCC DC supply voltage (for max. speed performance) 2.7 3.6 V VCC DC supply voltage (for low-voltage applications) 1.2 3.6 V DC Input voltage range 0 5.5 V VI/O DC Input voltage range for I/Os 0 VCC V VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V VI Tamb Operating free-air temperature range tr, tf Input rise and fall times 1998 Jul 29 VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V 3 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74LVC377 ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC CONDITIONS DC supply voltage IIK DC input diode current VI t0 VI DC input voltage Note 2 VI/O DC input voltage range for I/Os IOK DC output diode current VO uVCC or VO t 0 VOUT DC output voltage Note 2 IOUT DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT RATING –0.5 to +6.5 V –50 mA –0.5 to +5.5 V –0.5 to VCC +0.5 V "50 mA –0.5 to VCC +0.5 V "50 mA "100 mA –60 to +150 °C 500 500 mW DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) UNIT above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VOL VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 TYP1 LOW level output voltage VCC = 1.2V GND V 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*1.0 VCC 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA 0.20 0.55 "5 µA "0.1 "15 µA VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 "10 µA Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA Additional quiescent supply current VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA 6V; VI = 5 5V or GND VCC = 3 3.6V; 5.5V IIHZ/IILZ Input current for common I/O pins VCC = 3.6V; VI = VCC or GND IOZ 3-State output OFF-state current ICC NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Jul 29 V "0 1 "0.1 Input leakage current ∆ICC V VCC = 2.7V; VI = VIH or VIL; IO = 12mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA II MAX V VCC = 2.7 to 3.6V HIGH level output voltage UNIT 4 Not for I/O pins Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74LVC377 AC CHARACTERISTICS GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM MIN TYP1 MAX 6.0 10.2 VCC = 2.7V MIN UNIT TYP MAX 6.6 11.2 tPHL tPLH Propagation delay CP to Qn 1 tW Clock pulse width HIGH or LOW 1 4 1.0 5 1.6 ns tsu Set-up time E to CP 2 4 2.3 5 2.9 ns th Hold time E to CP 2 0 –2.2 0 –2.8 ns tsu Set-up time Dn to CP 3 2 1.3 3 1.8 ns th Hold time Dn to CP 3 0 –1.2 0 –1.6 ns Maximum clock pulse frequency 1 125 fmax ns 100 MHz NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C. AC WAVEFORMS VM = 1.5V at VCC 2.7V. VM = 0.5 VCC at VCC 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. 1/fMAX VCC VI CP INPUT E Input VM GND VCC tw Qn OUTPUT VM tsu GND VOH ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ tPHL tPLH Dn Input GND VM VCC SW00078 CP Input Waveform 1. Clock (CP) to output (Qn) propagation delays the clock pulse width and the maximum clock pulse frequency. tsu th th STABLE VM tsu VOL ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ th tW VM GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SY00061 Waveform 2. Data set-up and hold times from the data input (Dn) and from the enable input (E) to the clock (CP). 1998 Jul 29 5 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74LVC377 TEST CIRCUIT tW 90% S1 Vcc VS1 Open GND NEGATIVE PULSE 90% VM VI VM 10% 10% 0V Vl RL = 1k VO PULSE GENERATOR D.U.T. RL = 1k RT CL= 50pF tTHL (tf) tTLH (tr) tTLH (tr) tTHL (tf) 90% POSITIVE PULSE VI 90% VM VM 10% tW Test Circuit for Outputs 10% 0V VM = 1.5V Input Pulse Definition DEFINITIONS SWITCH POSITION TEST S1 tPLH/tPHL Open < 2.7V VCC 2 VCC tPLZ/tPZL VS1 2.7–3.6V 2.7V 2 VCC tPHZ/tPZH GND ≥ 4.5 V VCC 2 VCC VCC VI RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VS1 SY00044 Waveform 3. Load circuitry for switching times. 1998 Jul 29 6 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger SO20: plastic small outline package; 20 leads; body width 7.5 mm 1998 Jul 29 7 74LVC377 SOT163-1 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1998 Jul 29 8 74LVC377 SOT339-1 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1998 Jul 29 9 74LVC377 SOT360-1 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74LVC377 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04508