INTEGRATED CIRCUITS 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Product specification IC24 Data Handbook 1998 Jun 17 Philips Semiconductors Product Specification Dual D-type flip-flop with set and reset; positive-edge trigger FEATURES 74LVC74A DESCRIPTION • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output drive capability 50 transmission lines @ 85°C The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC74A is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in all data inputs makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns PARAMETER SYMBOL CONDITIONS Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ tPHL/tPLH fmax TYPICAL 3.6 3.5 3.5 CL = 50 pF; VCC = 3.3 V Maximum clock frequency CI Input capacitance CPD Power dissipation capacitance per flip-flop UNIT Notes 1 and 2 ns 250 MHz 5.0 pF 30 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) + (VO2/RL) × duty factor LOW, where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 14-Pin Plastic SO PACKAGES –40°C to +85°C 74LVC74A D 74LVC74A D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +85°C 74LVC74A DB 74LVC74A DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC74A PW 74LVC74APW DH SOT402-1 PIN CONFIGURATION LOGIC SYMBOL (IEEE/IEC) 1RD 1 14 VCC 4 1D 2 13 2RD 3 1CP 3 12 2D 2 1D 1SD 4 11 2CP 1 R 1Q 5 10 2SD 1Q 6 9 2Q 10 S GND 7 8 2Q 11 SV00491 S 5 C1 6 9 C2 12 2D 13 R 8 SV00332 1998 Jun 17 2 853-2070 19589 Philips Semiconductors Product Specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A PIN DESCRIPTION PIN NUMBER SYMBOL 1, 13 1RD, 2RD 2, 12 1D, 2D FUNCTION TABLE INPUTS NAME AND FUNCTION OUTPUTS SD RD CP D Q Q L H X X H L Data inputs H L X X L H L L X X H H Asynchronous reset-direct input (active LOW) 3, 11 1CP, 2CP Clock input (LOW-to-HIGH, edge triggered) 4, 10 1SD, 2SD Asynchronous set-direct input (active LOW) SD RD CP D Qn+1 Qn+1 5, 9 1Q, 2Q True flip-flop outputs H H ° L L H 6, 8 1Q, 2Q Complement flip-flop outputs H H ° H H L 7 GND Ground (0 V) 14 VCC Positive supply voltage INPUTS NOTES: H = HIGH voltage level L = LOW voltage level X = don“t care ° = LOW-to-HIGH CP transition Qn+1 = state after the next LOW-to-HIGH CP transition LOGIC SYMBOL 4 10 1SD 2SD SD 2 1D 1Q D Q 12 2D 2Q 3 1CP FF CP 11 2CP 1Q Q 2Q OUTPUTS FUNCTIONAL DIAGRAM 5 9 5 9 RD 4 1S D 2 1D 3 1CP D SD Q 1Q 5 1Q 6 2Q 9 2Q 8 CP FF1 Q 1RD 2RD 1 13 RD 1 1R D SV00492 10 2S D 12 2D 11 2CP D SD Q CP FF2 Q RD 13 2RD SV00494 1998 Jun 17 3 Philips Semiconductors Product Specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A LOGIC DIAGRAM (ONE FLIP-FLOP) Q C C C C C C D Q C C RD SD C CP C SV00495 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS LIMITS MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 UNIT V VI DC input voltage range 0 5.5 V VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V Tamb tr, tf Operating free-air temperature range VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V Input rise and fall times ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC PARAMETER CONDITIONS UNIT –0.5 to +6.5 V IIK DC input diode current VI t 0 –50 mA VI DC input voltage Note 2 –0.5 to +5.5 V IOK DC output diode current VO uVCC or VO t 0 VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT DC supply voltage RATING DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K "50 mA –0.5 to VCC +0.5 V "50 mA "100 mA –65 to +150 °C 500 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jun 17 4 Philips Semiconductors Product Specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 TYP1 V VCC = 1.2V GND V VCC = 2.7 to 3.6V HIGH level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –18mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*1.0 VCC VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage II ∆ICC V 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND VCC = 3.0V; VI = VIH or VIL; IO = 24mA ICC UNIT MAX 0.20 V 0.55 Input leakage current VCC = 3 3.6V; 6V; VI = 5 5.5V 5V or GND Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 "0 1 "0.1 "5 µA 0.1 10 µA 5 500 µA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC CHARACTERISTICS GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500; Tamb = –40C to +85C LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM VCC = 2.7V MIN TYP1 MAX MIN MAX UNIT Propagation delay nCP to nQ, nQ Figures 1, 3 1.5 3.6 5.2 – 6.0 ns Propagation delay nSD to nQ, nQ Figures 2, 3 1.5 3.5 5.4 – 6.4 ns Propagation delay nRD to nQ, nQ Figures 2, 3 1.5 3.5 5.4 – 6.4 ns Clock pulse width HIGH or LOW Figure 1 3.3 1.3 – – – Set or reset pulse width LOW Figure 2 3.3 1.7 – – – trem Removal time set or reset Figure 2 1 –3 – – – ns tsu Set-up time nD to nCP Figure 1 2.0 0.8 – – – ns th Hold time nD to nCP Figure 1 1 –0.7 – – – ns Maximum clock pulse frequency Figure 1 150 250 – – – MHz tPHL/ tPLH tW fmax NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Jun 17 5 ns Philips Semiconductors Product Specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A AC WAVEFORMS TEST CIRCUIT VM = 1.5 V at VCC 2.7 V VM = 0.5 S VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load. S1 VCC 2 * VCC Open GND 500Ω nD INPUT PULSE GENERATOR VM GND th t su 1/f max nCP INPUT TEST t PHL nQ OUTPUT tPLH/tPHL t PLH VOL VM t PHL t PLH NOTE: The shaded areas indicate when the inputis permitted to change for predictable output performance. SV00489 Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays, clock pulse width, nD to nCP set-up times, the nCP to nD hold times, output transition times and maximum clock pulse frequency. VI nCP INPUT VM GND trem VI VM tW tW nR D INPUT VM GND nQ OUTPUT tPLH tPHL VM VOL VOH nQ OUTPUT VOL VM tPHL tPLH SV00490 Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD to nCP removal time. 1998 Jun 17 VI VCC 2.7–3.6V 2.7V SV00903 VOL VOH VCC < 2.7V Figure 3. Load circuitry for switching times. nQ OUTPUT VI S1 Open VM VOH GND 500Ω SWITCH POSITION tW VOH 50pF CL t su VM GND D.U.T. RT th VI nS D INPUT VO VI VI 6 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A SO14: plastic small outline package; 14 leads; body width 3.9 mm 1998 Jun 17 7 SOT108-1 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm 1998 Jun 17 8 SOT337-1 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 1998 Jun 17 9 SOT402-1 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 06-96 9397-750-04487