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1GHz, 4x1 Multiplexing Amplifier with Synchronous
Controls
ISL59444
Features
The ISL59444 is a single-output 4:1 MUX-amp. The MUX-amp
has a fixed gain of 1 and a 1GHz bandwidth. The ISL59444 is
ideal for professional video switching, HDTV, computer display
routing, and other high performance applications.
• 1GHz (-3dB) Bandwidth (VOUT = 200mVP-P)
• 220MHz (-3dB) Bandwidth (VOUT = 2VP-P)
The device contains logic inputs for channel selection (S0,
S1), latch control signals (LE1, LE2), and a three-state output
control (HIZ) for individual selection of MUX amps that share
a common video output line. All logic inputs have pull-downs
to ground and may be left floating.
HIZ
S1
S0
OUT
0
0
0
0
IN0
0
0
0
1
IN1
0
0
1
0
IN2
0
0
1
1
IN3
X
1
X
X
HiZ
EN0
DL Q
C
DL Q
C
EN1
DL Q
C
DL Q
C
S0
DECODE
S1
EN2
HIZ
EN3
LE1
LE2
DL Q
C
DL Q
C
DL Q
C
• Slew Rate (RL = 500ΩVOUT = 5V) . . . . . . . . . . . . . . . .1155V/µs
• High Speed Three-State Output (HIZ)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
TABLE 1. TRUTH TABLE
LE1/LE2
• Slew Rate (RL = 500ΩVOUT = 4V) . . . . . . . . . . . . . . . .1515V/µs
•
•
•
•
•
•
•
HDTV/DTV Analog Inputs
Video Projectors
Computer Monitors
Set-top Boxes
Security Video
Broadcast Video Equipment
RGB Video Distribution Systems
IN0
IN1
OUT
LE1
IN2
LE2
IN3
DL Q
C
S0, S1, HIZ
OUT
CHX
CHX
CHY
CHZ
CHX
CHY
CHX
CHZ
CHZ
100kΩ
100kΩ
FIGURE 1. FUNCTIONAL DIAGRAM
August 16, 2012
FN7451.3
1
FIGURE 2. TIMING DIAGRAM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2005, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL59444
Pin Configuration
ISL59444 (16 LD SO)
TOP VIEW
IN0 1
16 V+
NIC 2
15 S0
IN1 3
14 S1
GND 4
13 HIZ
IN2 5
12 OUT
NIC 6
11 LE2
IN3 7
10 LE1
NIC 8
9 V-
Pin Descriptions
PIN NUMBER
PIN NAME
EQUIVALENT
CIRCUIT
1
IN0
Circuit 1
2, 6, 8
NIC
3
IN1
Circuit 1
Input for channel 1
4
GND
Circuit 4
Ground pin
5
IN2
Circuit 1
Input for channel 2
7
IN3
Circuit 1
Input for channel 3
9
V-
Circuit 4
Negative Power Supply
10
LE1
Circuit 2
Synchronized channel switching: When LE1 is low, the master control latch loads the
next switching address. The Mux Amp is configured for this address when LE2 goes low.
Synchronized operation results when LE2 is the inverse of LE1. Channel selection is
asynchronous (changes with any control signal change) if both LE1 and LE2 are
both low.
11
LE2
Circuit 2
Synchronized channel switching: When LE2 is low, the newly selected channel, stored
in the master latch via LE1 is selected. Synchronized operation results when LE2 is the
inverse of LE1. Channel selection is asynchronous (changes with any control signal
change) if both LE1 and LE2 are both low.
12
OUT
Circuit 3
Output
13
HIZ
Circuit 2
Output disable (active high); there are internal pull-down resistors, so the device will be
active with no connection; “HI” puts the output in high impedance state.
14
S1
Circuit 2
Channel selection pin MSB (binary logic code)
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DESCRIPTION
Input for channel 0
Not Internally Connected; it is recommended this pin be tied to ground to minimize
crosstalk.
2
FN7451.3
August 16, 2012
ISL59444
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
EQUIVALENT
CIRCUIT
15
S0
Circuit 2
Channel selection pin LSB (binary logic code)
16
V+
Circuit 4
Positive power supply
DESCRIPTION
V+
V+
21k
1.2V
LOGICPIN
IN
+
-
GND.
33k
V-
V-
CIRCUIT 2
CIRCUIT 1
V+
V+
GND
OUT
CAPACITIVELY
COUPLED
ESD CLAMP
VV-
CIRCUIT 4
CIRCUIT 3
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
TAPE &
REEL
PACKAGE
(Note 4)
PKG.
DWG. #
ISL59444IBZ
59444IBZ
-
16 Ld SO (Pb-free)
MDP0027
ISL59444IBZ-T13
59444IBZ
7”
16 Ld SO (Pb-free)
MDP0027
ISL59444IBZ-T7
59444IBZ
13”
16 Ld SO (Pb-free)
MDP0027
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL59444. For more information on MSL please see tech brief TB363.
4. SO16 (0.150”)
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3
FN7451.3
August 16, 2012
ISL59444
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital and Analog Input Current (Note 5) . . . . . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . . . . 3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figures 21 and 22
JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figures 21 and 22
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
5. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, RL = 500Ω to GND, VHIZ = 0.8V, unless otherwise specified.
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
No load, VHIZ = 0.8V
14.5
18
20
mA
No load, VHIZ = 2.0V
12.5
16
18
mA
DESCRIPTION
CONDITIONS
GENERAL
IS
Supply Current (VOUT = 0V)
VOUT
Positive and Negative Output Swing
VIN = ±3.5V, RL = 500Ω
±3.2
±3.44
IOUT
Output Current
RL = 10Ω to GND
±80
±120
±180
mA
VOS
Output Offset Voltage
-2
9
20
mV
Ib
Input Bias Current
VIN = 0V
-5
-2.5
-1
µA
Rout
Output Resistance
HIZ = logic high, (DC), AV = 1
1.4
MW
HIZ = logic low, (DC), AV = 1
0.2
Ω
VIN = ±3.5V
10
MΩ
1.1
pF
RIN
Input Resistance
CIN
Input Capacitance
ACL or AV
Voltage Gain
VIN = ±1.5V, RL = 500Ω
ITRI
Output Current in Three-state
VOUT = 0V
V
0.999
1.001
1.003
V/V
-35
6
+35
µA
LOGIC
VH
Input High Voltage (Logic Inputs)
VL
Input Low Voltage (Logic Inputs)
IIH
Input High Current (Logic Inputs)
IIL
tLE
2
V
0.8
V
50
150
µA
Input Low Current (Logic Inputs)
-10
5
µA
LE1, LE2 Minimum Pulse Width
-
-
ns
4
AC GENERAL
-3dB BW
0.1dB BW
dG
-3dB Bandwidth
0.1dB Bandwidth
Differential Gain Error
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4
VOUT = 200mVP-P, CL = 1.6pF
1.0
GHz
VOUT = 2VP-P, CL = 23.6pF,
RS = 25Ω
230
MHz
VOUT = 200mVP-P, CL = 1.6pF
80
MHz
VOUT = 2VP-P, CL = 23.6pF,
RS = 25Ω
50
MHz
0.01
%
NTSC-7, RL = 150
FN7451.3
August 16, 2012
ISL59444
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, RL = 500Ω to GND, VHIZ = 0.8V, unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
dP
Differential Phase Error
NTSC-7, RL = 150
0.02
°
+SR
Slew Rate
25% to 75%, VOUT = 5V,
RL = 500Ω, CL = 23.6pF, RS = 25Ω
1515
V/µs
-SR
Slew Rate
25% to 75%, VOUT = 5V,
RL = 500Ω, CL = 23.6pF, RS = 25Ω
1155
V/µs
PSRR
Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
V± = ±4.5V to ±5.5V
-57
dB
ISO
Channel Isolation
f = 10MHz, Ch-Ch X-Talk and Off
Isolation, CL = 1.6pF
75
dB
Channel-to-Channel Switching Glitch
VIN = 0V, CL = 23.6pF, RS = 25Ω
38
mVP-P
HIZ Switching Glitch
VIN = 0V, CL = 23.6pF, RS = 25Ω
175
mVP-P
tSW-L-H
Channel Switching Time Low to High
1.2V logic threshold to 10%
movement of analog output
32
ns
tSW-H-L
Channel Switching Time High to Low
1.2V logic threshold to 10%
movement of analog output
29
ns
Rise and Fall Time, 10% to 90%
VOUT = 200mVP-P, CL = 1.6pF
0.68
ns
VOUT = 2VP-P, CL = 23.6pF,
RS = 25Ω
1.4
ns
-50
SWITCHING CHARACTERISTICS
VGLITCH
TRANSIENT RESPONSE
tr, tf
tS
0.1% Settling Time
VOUT = 2VP-P, CL = 23.6pF,
RS = 25Ω
6.8
ns
tPLH
Propagation Delay - Low to High,
10% to 10%
VOUT = 200mVP-P, CL = 1.6pF
0.5
ns
VOUT = 2VP-P, CL = 23.6pF,
RS = 25Ω
0.85
ns
VOUT = 200mVP-P, CL = 1.6pF
0.54
ns
VOUT = 2VP-P, CL = 23.6pF,
RS = 25Ω
0.88
ns
VOUT = 200mVP-P, CL = 1.6pF
8.3
%
VOUT = 2VP-P, CL = 23.6pF,
RS = 25Ω
15.7
%
tPHL
OS
Propagation Delay- High to Low,
10% to 10%
Overshoot
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
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FN7451.3
August 16, 2012
ISL59444
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified.
5
5
NORMALIZED GAIN (dB)
3
CL = 9.7pF
2
CL = 7.2pF
1
0
-1
CL = 5.5pF
-2
CL = 1.6pF
-3
-4
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-5
0.001
VOUT = 200mVP-P
CL = 1.6pF
4
NORMALIZED GAIN (dB)
4
VOUT = 200mVP-P
3
2
RL = 500Ω
1
RL = 1kΩ
0
-1
-2
RL = 150Ω
-3
RL = 75Ω
-4
0.01
-5
0.001
1 1.5
0.1
0.01
FIGURE 3. SMALL SIGNAL GAIN vs FREQUENCY vs CL
5
2
1
CL = 11.6pF
0
-1
CL = 16.6pF
-2
CL = 23.6pF
-3
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-5
0.001
VOUT = 2VP-P
CL = 23.6pF
RS = 25Ω
4
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
VOUT = 2VP-P
RS = 25Ω
3
-4
2
1
0
-1
-2
RL = 150Ω
-3
0.1
-5
0.001
1 1.5
0.01
0.1
1 1.5
FIGURE 6. LARGE SIGNAL GAIN vs FREQUENCY vs RL
0.5
0.5
CL = 9.7pF
CL = 7.2pF
0.2
0.4
NORMALIZED GAIN (dB)
VOUT = 200mVP-P
0.3
NORMALIZED GAIN (dB)
RL = 1kΩ
FREQUENCY (GHz)
FIGURE 5. LARGE SIGNAL GAIN vs FREQUENCY vs CL
CL = 5.5pF
0.1
0
-0.1
-0.2
-0.3
-0.4
RL = 75Ω
RL = 500Ω
-4
CL = 28.6pF
0.01
3
FREQUENCY (GHz)
0.4
1 1.5
FIGURE 4. SMALL SIGNAL GAIN vs FREQUENCY vs RL
5
4
0.1
FREQUENCY (GHz)
FREQUENCY (GHz)
CL = 1.6pF
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.5
0.001
0.01
0.1
1 1.5
FREQUENCY (GHz)
6
0.2
0.1
0
-0.1
RL = 1kΩ
-0.2
RL = 150Ω
-0.3
-0.4
FIGURE 7. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
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0.3
VOUT = 200mVP-P
CL = 1.6pF
-0.5
0.001
RL = 500Ω
RL = 75Ω
0.01
0.1
1 1.5
FREQUENCY (GHz)
FIGURE 8. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
FN7451.3
August 16, 2012
ISL59444
0.2
5
0.1
4
0
-0.1
CL = 11.6pF
-0.2
-0.3
CL = 16.6pF
-0.4
-0.5
-0.6
-0.7
CL = 23.6pF
VOUT = 2VP-P
RS = 25Ω
CL = 28.6pF
CL INCLUDES 1.6pF
BOARD CAPACITANCE
-0.8
0.001
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
0.01
3
VOUT = 2VP-P
CL = 23.6pF
RS = 25Ω
2
RL = 150Ω
1
0
RL = 75Ω
-1
-2
-3
0.1
-5
0.001
1 1.5
0.01
-10
VIN = 1VP-P
CL = 23.6pF
RS = 25Ω
-20
VIN = 200mVP-P
CL = 23.6pF
RS = 25Ω
-30
-40
-10
-50
-20
(dB)
PSRR (dB)
1 1.5
FIGURE 10. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
20
-30
-60
CROSSTALK
-70
-40
-50
-80
PSRR (V+)
-90
-60
PSRR (V-)
-70
-80
0.3
0.1
FREQUENCY (GHz)
FREQUENCY (GHz)
0
RL = 1kΩ
-4
FIGURE 9. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
10
RL = 500Ω
1
10
OFF ISOLATION
-100
100
1000
-110
0.001
FREQUENCY (MHz)
0.01
0.1
1
3
6 10
100
500
FREQUENCY (MHz)
FIGURE 11. PSRR CHANNELS
FIGURE 12. CROSSTALK AND OFF ISOLATION
100
60
INPUT VOLTAGE NOISE (nV/√Hz)
OUTPUT RESISTANCE (Ω)
VOUT = 100mVP-P
10
1
RF = 500Ω
50
40
30
20
10
0.1
0.1
1
10
100
FREQUENCY (MHz)
FIGURE 13. ROUT vs FREQUENCY
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1000
0
0.1
1
10
100
FREQUENCY (kHz)
FIGURE 14. INPUT NOISE vs FREQUENCY
FN7451.3
August 16, 2012
ISL59444
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
S0, S1
1V/DIV
1V/DIV
S0, S1
0
0
500mV/DIV
20mV/DIV
0
VOUT
VOUT
0
20ns/DIV
20ns/DIV
FIGURE 15. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V,
RS = 25, CL = 23.6pF
FIGURE 16. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V, RS = 25, CL = 23.6pF
HIZ
1V/DIV
1V/DIV
HIZ
0
500mV/DIV
100mV/DIV
0
0
VOUT
VOUT
0
20ns/DIV
20ns/DIV
FIGURE 17. HIZ SWITCHING GLITCH VIN = 0V, RS = 25,
CL = 23.6pF
FIGURE 18. HIZ TRANSIENT RESPONSE VIN = 1V, RS = 25,
CL = 23.6pF
160
2.4
CL = 1.6pF
RL = 500Ω
80
2.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
120
40
0
-40
-80
1.6
1.2
0.8
0.4
0
-0.4
-120
-160
-0.8
TIME (4ns/DIV)
FIGURE 19. SMALL SIGNAL TRANSIENT RESPONSE
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CL = 23.6pF
RS = 25Ω
RL = 500Ω
TIME (4ns/DIV)
FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE
FN7451.3
August 16, 2012
ISL59444
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = +25°C, unless otherwise specified. (Continued)
1.0
1.250W
1.2
1.0
0.8
0.6
0.4
0.2
0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.9
SO
16

JA
(0
.1
=
50
80
”)
°C
/W
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.4
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
909mW
0.8

0.7
JA
0.6
SO
16
=
11
0.5
(0
.1
0°
50
”)
C
/W
0.4
0.3
0.2
0.1
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
AC Test Circuits
ISL59444
ISL59444
VIN
VIN
CL
2pF
50Ω
OR
75Ω
50Ω
OR
75Ω
RL
500Ω
FIGURE 23A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
50Ω
OR
75Ω
RS
CL
2pF
CL
2pF
475Ω
50Ω
OR
75Ω
50Ω
OR
75Ω
FIGURE 23B. TEST CIRCUIT FOR MEASURING WITH A 50Ω OR 75Ω
INPUT TERMINATED EQUIPMENT
ISL59444
VIN
TEST
EQUIPMENT
RS
50Ω OR 75Ω
TEST
EQUIPMENT
50Ω
OR
75Ω
FIGURE 23C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω WILL BE
DEGRADED.
Figure 23A illustrates the optimum output load for testing AC performance. Figure 23B illustrates the optimum output load when
connecting to input terminated equipment. Figure 23C illustrates back loaded test circuit for video cable.
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FN7451.3
August 16, 2012
ISL59444
Application Circuits
*CL = CT + COUT
VIN
VOUT
+
COUT
CT
1.6pF
50Ω
0pF
RL = 500Ω
*CL: TOTAL LOAD CAPACITANCE
CT: TRACE CAPACITANCE
COUT: OUTPUT CAPACITANCE
FIGURE 24A. SMALL SIGNAL 200mVP-P APPLICATION CIRCUIT
RS
25Ω
VIN
+
1.6pF
50Ω
CT
VOUT
COUT
22pF
RL = 500Ω
CL = CT + COUT
FIGURE 24B. LARGE SIGNAL 1VP-P APPLICATION CIRCUIT
Application Information
Control Signals
General
S0, S1, HIZ - These pins are, TTL/CMOS compatible control
inputs. The S0, S1 pins select which one of the inputs connect to
the output. The HIZ pin is used to three-state the output
amplifiers. For control signal rise and fall times less than 10ns
the use of termination resistors close to the part will minimize
transients coupled to the output.
The ISL59444 is a 4:1 mux that is ideal as a matrix element in
high performance switchers and routers. The ISL59444 is
optimized to drive a 2pF in parallel with a 500Ω load. The
capacitance can be split between the PCB capacitance an and
external load capacitance. Their low input capacitance and high
input resistance provide excellent 50Ω or 75Ω terminations.
Capacitance at the Output
The output amplifier is optimized for capacitance to ground (CL)
directly on the output pin. Increased capacitance causes higher
peaking with an increase in bandwidth. The optimum range for
most applications is ~1.0pF to ~6pF. The optimum value can be
achieved through a combination of PC board trace capacitance
(CT) and an external capacitor (COUT). A good method to maintain
control over the output pin capacitance is to minimize the trace
length (CT) to the next component, and include a discrete surface
mount capacitor (COUT) directly at the output pin.
For large signal applications where overshoot is important the
circuit in Figure 24B should be used. The series resistor (RS) and
capacitor (CL) form a low pass network that limits system
bandwidth and reduces overshoot. The component values shown
result in a typical pulse response shown in Figure 20.
Ground Connections
For the best isolation and crosstalk rejection, the GND pin and
NIC pins must connect to the GND plane. The NIC pins are placed
on both sides of the input pins. These pins are not internally
connected to the die. It is recommended this pin be tied to
ground to minimize crosstalk.
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HIZ State
An internal pull-down resistor connected to the HIZ pin ensures
the device will be active with no connection to the HIZ pin. The
HIZ state is established within approximately 30ns by placing a
logic high (>2V) on the HIZ pin. If the HIZ state is selected, the
output is a high impedance 1.4MΩ. Use this state to control the
logic when more than one mux shares a common output.
In the HIZ state the output is three-stated, and maintains its high
Z even in the presence of high slew rates. The supply current
during this state is basically the same as the active state.
Latch State
The latched control signals allow for synchronized channel switching.
When LE1 is low the master control latch loads the next switching
address (S0, S1), while the closed (assuming LE2 is the inverse of
LE1) slave control latch maintains the current state. LE2 switching
low closes the master latch (with previous assumption), loads the
now open slave latch, and switches the crosspoint to the newly
selected channel. Channel selection is asynchronous (changes with
any control signal change) if both LE1 and LE2 are low.
FN7451.3
August 16, 2012
ISL59444
Power-Up Considerations
PC Board Layout
The ESD protection circuits use internal diodes from all pins the
V+ and V- supplies. In addition, a dv/dt triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the “Pin Descriptions”
on page 2. The dv/dt triggered clamp imposes a maximum
supply turn-on slew rate of 1V/µs. Damaging currents can flow
for power supply rates-of-rise in excess of 1V/µs, such as during
hot plugging. Under these conditions, additional methods should
be employed to ensure the rate of rise is not exceeded.
The frequency response of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip resistors
and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid sharp
corners, use rounded corners when possible. Vias in the signal
lines add inductance at high frequency and should be avoided.
PCB traces greater than 1" begin to exhibit transmission line
characteristics with signal rise/fall times of 1ns or less. High
frequency performance may be degraded for traces greater
than one inch, unless strip lines are used.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic input
pins. Schottky diodes (Motorola MBR0550T or equivalent)
connected from V+ to ground and V- to ground (Figure 25) will
shunt damaging currents away from the internal V+ and V- ESD
diodes in the event that the V+ supply is applied to the device
before the V- supply.
• Match channel-channel analog I/O trace lengths and layout
symmetry. This will minimize propagation delay mismatches.
If positive voltages are applied to the logic or analog video input
pins before V+ is applied, current will flow through the internal
ESD diodes to the V+ pin. The presence of large decoupling
capacitors and the loading effect of other circuits connected to
V+, can result in damaging currents through the ESD diodes and
other active circuits within the device. Therefore, adequate
current limiting on the digital and analog inputs is needed to
prevent damage during the time the voltages on these inputs are
more positive than V+.
• Maximize use of AC de-coupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e., no split
planes or PCB gaps under these lines). Avoid vias in the signal
I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables, matching
cable types and keeping cable lengths to a minimum.
Limiting the Output Current
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices as
possible. Avoid vias between the cap and the device because
vias add unwanted inductance. Larger caps can be farther
away. When vias are required in a layout, they should be routed
as far away from the device as possible.
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than 50mA.
Adequate thermal heat sinking of the parts is also required.
• The NIC pins are placed on both sides of the input pins. These
pins are not internally connected to the die. It is recommended
these pins be tied to ground to minimize crosstalk.
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
V+
LOGIC
CONTROL
S0
POWER
GND
GND
SIGNAL
IN0
EXTERNAL
CIRCUITS
V+
V-
V+
V+
V+
OUT
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 25. SCHOTTKY PROTECTION CIRCUIT
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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FN7451.3
August 16, 2012
ISL59444
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
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12
FN7451.3
August 16, 2012