INTERSIL ISL59445

ISL59424, ISL59445
®
Data Sheet
September 8, 2005
FN7456.2
1GHz Triple Multiplexing Amplifiers
Features
The ISL59424 and ISL59445 are 1GHz bandwidth
multiplexing amplifiers designed primarily for video input
switching. These MUX-amps exhibit a fixed gain of 1 and
also feature a high speed three-state to enable the output of
multiple devices to be wired together. All logic inputs have
pull-downs to ground and may be left floating. The EN pin,
when pulled high, sets the ISL59424 and ISL59445 in to low
current mode - consuming just 15mW. An added feature in
the ISL59424 is a latch enable function (LE) that allows
independent logic control using a common logic bus. When
LE is high the last logic state is preserved.
• Triple 2:1 and 4:1 Multiplexers for RGB
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59424
S0
ENABLE
HIZ
LE
OUTPUT
0
0
0
0
INO (A, B, C)
1
0
0
0
IN1 (A, B, C)
X
1
X
X
Power Down
X
0
1
X
High Z
X
0
0
1
Last S0 State
Preserved
• Internally Set Gain-of-1
• High Speed Three-state Outputs (HIZ)
• Power-down Mode (EN)
• Latch Enable (ISL59424)
• ±5V Operation
• ±1200 V/µsec Slew Rate
• 1GHz Bandwidth
• Latched Select Pin (ISL59424)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• HDTV/DTV Analog Inputs
• Video Projectors
• Computer Monitors
• Set-top Boxes
• Security Video
TABLE 2. CHANNEL SELECT LOGIC TABLE ISL59445
S1
S0
ENABLE
HIZ
OUTPUT
0
0
0
0
IN0 (A, B, C)
0
1
0
0
IN1 (A, B, C)
1
0
0
0
IN2 (A, B, C)
1
1
0
0
X
X
1
X
X
0
• Broadcast Video Equipment
Ordering Information
PART
MARKING
PACKAGE
TAPE &
REEL
PKG.
DWG. #
ISL59424IR
ISL59424IR
24 Ld QFN
-
MDP0046
IN3 (A, B, C)
ISL59424IR-T7
ISL59424IR
24 Ld QFN
7”
MDP0046
X
Power Down
ISL59424IR-T13
ISL59424IR
24 Ld QFN
13”
MDP0046
1
High Z
PART NUMBER
ISL59424IRZ
(Note)
ISL59424IRZ 24 Ld QFN
(Pb-free)
-
MDP0046
ISL59424IRZ-T7
(Note)
ISL59424IRZ 24 Ld QFN
(Pb-free)
7”
MDP0046
ISL59424IRZ-T13 ISL59424IRZ 24 Ld QFN
(Note)
(Pb-free)
13”
MDP0046
ISL59445IR
ISL59445IR
32 Ld QFN*
-
MDP0046
ISL59445IR-T7
ISL59445IR
32 Ld QFN*
7”
MDP0046
ISL59445IR-T13
ISL59445IR
32 Ld QFN*
13”
MDP0046
*32 Ld QFN Exposed Pad Size 2.48 x 3.40mm
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL59424, ISL59445
Pinouts
A=1
26 HIZ
27 IN0C
28 NIC
THERMAL
PAD
IN2A 7
LE 12
13 S0
NIC 8
18 S0
IN3C 16
NIC 15
IN3B 14
NIC 13
17 S1
IN3A 12
IN2B 9
THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE
TIED TO V-
20 OUTB
19 OUTC
A=1
IN2C 10
NIC 11
NIC 10
IN1C 9
NIC 8
IN1B 7
21 VA=1
GNDB 6
14 OUTC
THERMAL
PAD
23 V+
22 OUTA
IN1C 5
15 V-
GNDC 6
A=1
NIC 4
16 OUTB
A=1
IN1A 5
24 NIC
IN1B 3
17 V+
GNDB 4
29 IN0B
NIC 2
18 OUTA
A=1
IN0C 3
25 ENABLE
GNDC 11
NIC 2
31 IN0A
32 GNDA
21 NIC
22 NIC
23 IN0A
24 GNDA
20 HIZ
IN1A 1
19 ENABLE
IN0B 1
30 NIC
ISL59445
(32-PIN QFN)
TOP VIEW
ISL59424
(24-PIN QFN)
TOP VIEW
LATCHED ON HIGH LE
THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE
TIED TO V-
NIC = NO INTERNAL CONNECTION
NIC = NO INTERNAL CONNECTION
Functional Diagram ISL59424
Functional Diagram ISL59445
EN0
S0
S0
EN0
DECODE
EN1
DL Q
C
DL Q
C
EN1
IN0(A,B,C)
OUT
S1
IN1(A,B,C)
DECODE
IN1(A,B,C)
IN0(A,B,C)
EN2
OUT
IN2(A,B,C)
IN3(A,B,C)
EN3
AMPLIFIER BIAS
LE
AMPLIFIER BIAS
HIZ
HIZ
ENABLE
ENABLE
A logic high on LE will latch the last S0 state.
This logic state is preserved when cycling HIZ
or ENABLE functions.
2
FN7456.2
September 8, 2005
ISL59424, ISL59445
Absolute Maximum Ratings (TA = 25°C)
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, VIN = 1VP-P & RL = 500Ω to GND unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
No load, VIN = 0V, Enable low, IS+
35
39
43
mA
No load, VIN = 0V, Enable low, IS-
-40
-36
-32
mA
GENERAL
IS Enabled
Enabled Supply Current (ISL59424)
No load, VIN = 0V, Enable low, IS+
47
53
60
mA
No load, VIN = 0V, Enable low, IS-
-57
-50
-44
mA
Enable High, IS+
2
3
4
mA
Enable High, IS-
-50
0
Input Bias Current
VIN = 0
-3.4
-2.2
-1.4
µA
Bias current into output, HIZ mode
ISL59424 - VOUT = +5V
8
15
22
µA
ISL59445 - VOUT = 0V
-35
0
35
µA
Enabled Supply Current (ISL59445)
+IS Disabled
Ib
ITRI
Disabled Supply Current
µA
VOUT
Positive and Negative Output Swing
VIN = ±3.5V
±3.2
±3.4
IOUT
Output Current
RL = 10Ω to GND
±80
±130
VOS
Offset Voltage
-13
3
Rout
HIZ Output Resistance
HIZ = logic high
1.0
MΩ
Rout
Enabled Output Resistance
HIZ = logic low
0.2
Ω
RIN
Input Resistance
VIN = ±3.5V
10
MΩ
Voltage Gain
VIN = ±1.5V
ACL or AV
0.98
0.99
V
mA
13
1.0
mV
V/V
LOGIC
VIH
Input High Voltage (Logic Inputs)
VIL
Input Low Voltage (Logic Inputs)
IIH
Input High Current (Logic Inputs)
VH = 5V
IIL
Input Low Current (Logic Inputs)
VL = 0V
Power Supply Rejection Ratio
(ISL59424)
DC, PSRR V+ & V- combined
60
73
dB
Power Supply Rejection Ratio
(ISL59445)
DC, PSRR V+ & V- combined
50
57
dB
Channel Isolation (ISL59424)
f = 10MHz, CL = 0.5pF, VIN = -6dBm
80
dB
75
dB
2
235
V
0.8
V
270
320
µA
1
3
µA
AC GENERAL
PSRR
ISO
Channel Isolation (ISL59445)
3
FN7456.2
September 8, 2005
ISL59424, ISL59445
Electrical Specifications
PARAMETER
Xtalk
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, VIN = 1VP-P & RL = 500Ω to GND unless otherwise specified.
DESCRIPTION
CONDITIONS
Channel Cross Talk (ISL59424)
MIN
TYP
f = 10MHz, CL = 0.5pF, VIN = -6dBm
MAX
UNIT
75
Channel Cross Talk (ISL59445)
dB
70
dG
Differential Gain Error
NTC-7, RL = 150, CL = 0.5pF
0.02
%
dP
Differential Phase Error
NTC-7, RL = 150, CL = 0.5pF
0.02
°
BW
-3dB Bandwidth
CL = 0.5pF
1000
MHz
FBW
0.1dB Bandwidth
CL = 0.5pF
130
MHz
0.1dB Bandwidth
CL = 1.5pF
200
MHz
±1200
V/µs
SWITCHING CHARACTERISTICS
Slew Rate
25% to 75%, RL = 150Ω, Input Enabled,
CL = 1.5pF, VIN = ±1V
Channel -to-Channel Switching Glitch
VIN = 0V, CL = 0.5pF
40
mVP-P
Enable Switching Glitch
VIN = 0V, CL = 0.5pF
300
mVP-P
HIZ Switching Glitch
VIN = 0V, CL = 0.5pF
200
mVP-P
Channel -to-Channel Switching Glitch
VIN = 0V, CL = 0.5pF
20
mVP-P
Enable Switching Glitch
VIN = 0V, CL = 0.5pF
200
mVP-P
HIZ Switching Glitch
VIN = 0V, CL = 0.5pF
200
mVP-P
tSW-L-H
Channel Switching Time Low to High
1.2V logic threshold to 10% movement of
analog output
15
ns
tSW-H-L
Channel Switching Time High to Low
1.2V logic threshold to 10% movement of
analog output
15
ns
tr
Rise Time
10% to 90%
600
ps
tf
Fall Time
10% to 10%
800
ps
tpd
Propagation Delay
10% to 10%
600
ps
tS
0.1% Settling Time
Step = 1V
6
ns
tLH
Latch Enable HoldTime
LE = 0V
10
ns
SR
VGLITCH
ISL58424
VGLITCH
ISL59445
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
5
10
SOURCE
POWER=-12dBm
6
CL=3.8pF
4
CL=2.7pF
3
CL=1.5pF
2
0
-2
CL=0.5pF
-4
-6
CL INCLUDES 0.5pF
BOARD CAPACITANCE
-8
SOURCE
POWER=-12dBm
4
CL=5.2pF
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
8
CL=8.7pF
RL=1kΩ
2
RL=500Ω
1
0
-1
-2
RL=150Ω
-3
RL=100Ω
-4
-5
-10
1
10
100
FREQUENCY (MHz)
FIGURE 1. GAIN vs FREQUENCY vs CL
4
1K
1.2K
1
10
1K
100
1.2K
FREQUENCY (MHz)
FIGURE 2. GAIN vs FREQUENCY vs RL
FN7456.2
September 8, 2005
ISL59424, ISL59445
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
100
0.2
SOURCE
0.1
POWER =-12dBm
SOURCE
POWER =-12dBm
CL=2.0pF
OUTPUT RESISTANCE (Ω)
0
NORMALIZED GAIN (dB)
(Continued)
-0.1
-0.2
CL=0.5pF
-0.3
CL=1.5pF
-0.4
-0.5
-0.6
ISL59424
10
ISL59445
1
-0.7
-0.8
10
1
100
FREQUENCY (MHz)
0.1
0.1
1K 1.2K
100
1K
FIGURE 4. ROUT vs FREQUENCY
0.8
0.8
RL=500Ω
CL=1.5pF
0.6
RL=500Ω
CL=1.5pF
0.6
OUTPUT VOLTAGE (V)
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 5. ISL59424 TRANSIENT RESPONSE
FIGURE 6. ISL59445 TRANSIENT RESPONSE
0
0
-10
-10
INPUT X TO OUTPUT Y
CROSSTALK
-20
-30
-30
-40
-40
OFF ISOLATION
INPUT X TO OUTPUT X
-50
-60
-70
-70
-80
-80
-90
-90
1
10
100
FREQUENCY (MHz)
FIGURE 7. ISL59424 CROSSTALK AND OFF ISOLATION
5
1K
OFF ISOLATION
INPUT X TO OUTPUT X
-50
-60
-100
0.1
INPUT X TO OUTPUT Y
CROSSTALK
-20
(dB)
(dB)
10
FREQUENCY (MHz)
FIGURE 3. 0.1dB GAIN vs FREQUENCY
OUTPUT VOLTAGE (V)
1
-100
0.1
1
10
100
1K
FREQUENCY (MHz)
FIGURE 8. ISL59445 CROSSTALK AND OFF ISOLATION
FN7456.2
September 8, 2005
ISL59424, ISL59445
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
20
20
PSRR (V+)
10
0
0
-10
-10
-20
PSRR (dB)
PSRR (dB)
10
PSRR (V-)
-30
-40
PSRR (V+)
PSRR (V-)
-20
-30
-40
-50
-50
-60
-60
-70
-70
-80
0.3
1
10
100
-80
0.3
1K
1
1K
1V/DIV
1V/DIV
VIN = 1V
S0, S1
50Ω
TERM.
VIN = 0V
0
0.5V/DIV
0
20mV/DIV
100
FIGURE 10. ISL59445 PSRR CHANNELS A, B, C
FIGURE 9. ISL59424 PSRR CHANNELS A, B, C
S0, S1
50Ω
TERM.
10
FREQUENCY (MHz)
FREQUENCY (MHz)
0
VOUT A, B, C
0
VOUT A, B, C
10ns/DIV
10ns/DIV
FIGURE 11. CHANNEL TO CHANNEL SWITCHING GLITCH
VIN = 0V
ENABLE
50Ω
TERM.
FIGURE 12. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V
VIN = 1V
ENABLE
VIN = 0V
1V/DIV
1V/DIV
50Ω
TERM.
0
0
VOUT A, B, C
1V/DIV
100mV/DIV
(Continued)
0
20ns/DIV
FIGURE 13. ENABLE SWITCHING GLITCH VIN = 0V
6
0
VOUT A, B, C
20ns/DIV
FIGURE 14. ENABLE TRANSIENT RESPONSE VIN = 1V
FN7456.2
September 8, 2005
ISL59424, ISL59445
Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
HIZ
HIZ
VIN = 0V
VIN=1V
50Ω
TERM.
1V/DIV
1V/DIV
50Ω
TERM.
0
0
VOUT A, B, C
1V/DIV
200mv/DIV
(Continued)
0
VOUT A, B, C
0
10ns/DIV
10ns/DIV
FIGURE 15. HIZ SWITCHING GLITCH VIN = 0V
FIGURE 16. HIZ TRANSIENT RESPONSE VIN = 1V
60
4
50
3.5
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
POWER DISSIPATION (W)
VOLTAGE NOISE (nV/√Hz)
3.571W
40
30
20
10
0
100
10K
QFN32
θJA=35°C/W
3
2.5
QFN24
θJA=37°C/W
2
0.5
0
1K
3.378W
100K
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FREQUENCY (Hz)
FIGURE 17. INPUT NOISE vs FREQUENCY (OUTPUT A, B, C)
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE
LAYER) TEST BOARD
0.8
758mW
POWER DISSIPATION (W)
0.7
714mW
0.6
QFN32
θJA=125°C/W
0.5
0.4
QFN24
0.3
θJA=140°C/W
0.2
0.1
0
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
7
FN7456.2
September 8, 2005
ISL59424, ISL59445
Pin Descriptions
ISL59445
(32-PIN QFN)
ISL59424
(24-PIN QFN)
PIN
NAME
EQUIVALENT
CIRCUIT
Circuit 1.
DESCRIPTION
1
5
IN1A
2, 4, 8, 13, 15,
24, 28, 30
2, 8, 10, 11,
21, 22
NIC
3
7
IN1B
5
9
IN1C
Circuit 1.
Channel 1 input for output amplifier "C"
6
4
GNDB
Circuit 4.
Ground pin for output amplifier “B”
7
IN2A
Circuit 1.
Channel 2 input for output amplifier "A"
9
IN2B
Circuit 1.
Channel 2 input for output amplifier "B"
10
Channel 1 input for output amplifier "A"
Not Internally Connected; it is recommended these pins be tied to ground to
minimize crosstalk.
Circuit 1.
Channel 1 input for output amplifier "B"
IN2C
Circuit 1.
Channel 2 input for output amplifier "C"
GNDC
Circuit 4.
Ground pin for output amplifier “C”
12
IN3A
Circuit 1.
Channel 3 input for output amplifier "A"
14
IN3B
Circuit 1.
Channel 3 input for output amplifier "B"
16
IN3C
Circuit 1.
Channel 3 input for output amplifier "C"
17
S1
Circuit 2.
Channel selection pin MSB (binary logic code)
11
6
18
13
S0
Circuit 2.
Channel selection pin. LSB (binary logic code)
19
14
OUTC
Circuit 3.
Output of amplifier “C”
20
16
OUTB
Circuit 3.
Output of amplifier “B”
21
15
V-
Circuit 4.
Negative power supply
22
18
OUTA
Circuit 3.
Output of amplifier “A”
23
17
V+
Circuit 4.
Positive power supply
25
19
ENABLE
Circuit 2.
Device enable (active low). Internal pull-down resistor ensures the device will be
active with no connection to this pin. A logic High on this pin puts device into powerdown mode. In power-down mode only logic circuitry is active. All logic states are
preserved post power-down. This state is not recommended for logic control where
more than one MUX-amp share the same video output line.
12
LE
Circuit 2.
Device latch enable on the ISL59424. A logic high on LE will latch the last (S0, S1)
logic state. HIZ and ENABLE functions are not latched with the LE pin.
26
20
HIZ
Circuit 2.
Output disable (active high). Internal pull-down resistor ensures the device will be
active with no connection to this pin. A logic high, puts the outputs in a high
impedance state. Use this state to control logic when more than one MUX-amp
share the same video output line.
27
3
IN0C
Circuit 1.
Channel 0 for output amplifier "C"
29
1
IN0B
Circuit 1.
Channel 0 for output amplifier "B"
31
23
IN0A
Circuit 1.
Channel 0 for output amplifier "A"
32
24
GNDA
Circuit 4.
Ground pin for output amplifier “A”
V+
IN
LOGIC PIN
VCIRCUIT 1
21K
33K
+
1.2V
-
V+
V+
GND.
OUT
V-
V-
CIRCUIT 2
CIRCUIT 3
THERMAL HEAT SINK PAD
V+
GNDA
GNDB
GNDC
CAPACITIVELY
COUPLED
ESD CLAMP
~1MΩ
VSUBSTRATE
V.
CIRCUIT 4
8
FN7456.2
September 8, 2005
ISL59424, ISL59445
AC Test Circuits
ISL59424 & ISL59445
TEST
EQUIPMENT
ISL59424 & ISL59445
VIN
CL
1.5pF
50Ω
or
75Ω
VIN
RL
500Ω
50Ω
or
75Ω
FIGURE 20A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
475Ω
or
462.5Ω
50Ω
or
75Ω
50Ω
or
75Ω
TEST
EQUIPMENT
RS
VIN
CL
1.5pF
FIGURE 20B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR
75Ω INPUT TERMINATED EQUIPMENT
ISL59424 & ISL59445
50Ω
or
75Ω
RS
50Ω or 75Ω
CL
1.5pF
50Ω
or
75Ω
FIGURE 20C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω
WILL BE DEGRADED.
FIGURE 20. TEST CIRCUITS
Figure 20A illustrates the optimum output load for testing AC
performance. Figure 20B illustrates the optimum output load
when connecting to 50Ω input terminated equipment.
Application Information
General
The ISL59424 and ISL59445 are triple 2:1 and 4:1 muxes
that are ideal for the matrix element of high performance
switchers and routers. The ISL59424 and ISL59445 are
optimized to drive a 1.5pF in parallel with a 500Ω load. The
capacitance can be split between the PCB capacitance an
and external load capacitance. Their low input capacitance
and high input resistance provide excellent 50Ω or 75Ω
terminations.
Ground Connections
For the best isolation and crosstalk rejection, all GND pins
and NIC pins must connect to the GND plane.
Control Signals
S0, S1, ENABLE, LE, HIZ - These pins are binary coded,
TTL/CMOS compatible control inputs. The S0, S1 pins select
which one of the inputs connect to the output. All three
amplifiers are switched simultaneously from their respective
inputs. The ENABLE, LE, HIZ pins are used to disable the part
to save power, latch in the last logic state and three-state the
output amplifiers, respectively. For control signal rise and fall
times less than 10ns the use of termination resistors close to
the part should be considered to minimize transients coupled
to the output.
9
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT- triggered clamp
is connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum
supply turn-on slew rate of 1V/µs. Damaging currents can
flow for power supply rates-of-rise in excess of 1V/µs, such
as during hot plugging. Under these conditions, additional
methods should be employed to ensure the rate of rise is not
exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 21) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
FN7456.2
September 8, 2005
ISL59424, ISL59445
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
V+
LOGIC
CONTROL
S0
POWER
GND
GND
SIGNAL
EXTERNAL
CIRCUITS
V+
V-
IN0
V+
V+
V+
OUT
V-
DE-COUPLING
CAPS
IN1
VV-
V-
V- SUPPLY
FIGURE 21. SCHOTTKY PROTECTION CIRCUIT
HIZ State
An internal pull-down resistor connected to the HIZ pin
ensures the device will be active with no connection to the
HIZ pin. The HIZ state is established within approximately
15ns (Figure 16) by placing a logic high (>2V) on the HIZ
pin. If the HIZ state is selected, the output is a high
impedance 1.4MΩ with approximately 1.5pF in parallel with
a 10µA bias current from the output. Use this state to control
the logic when more than one mux shares a common output.
In the HIZ state the output is three-stated, and maintains its
high Z even in the presence of high slew rates. The supply
current during this state is basically the same as the active
state.
ENABLE and Power Down States
The enable pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
ENABLE pin. The Power Down state is established within
approximately 100ns (Figure 14), if a logic high (>2V) is
placed on the ENABLE pin. In the Power Down state, the
output has no leakage but has a large variable capacitance
(on the order of 15pF), and is capable of being back-driven.
Under this condition, large incoming slew rates can cause
fault currents of tens of mA. Do not use this state as a
logic control for applications driving more than one mux
on a common output.
LE State
The ISL59424 is equipped with a Latch Enable pin. A logic
high (>2V) on the LE pin latches the last logic state. This
logic state is preserved when cycling HIZ or ENABLE
functions.
Limiting the Output Current
RGB video and disconnects the sync signal for the
component signal.
PC Board Layout
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip line
are used.
• Match channel-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
Application Example
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices
as possible - Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
Figure 21 illustrates the use of the ISL59445, two ISL84517
SPST switches and one NC7ST00P5X NAND gate to mux 3
different component video signals and one RGB video
signal. The SPDT switches provide the sync signal for the
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
10
FN7456.2
September 8, 2005
ISL59424, ISL59445
The QFN Package Requires Additional PCB Layout
Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply
through the high resistance IC substrate. Its primary function
is to provide heat sinking for the IC. However, because of the
connection to the V- supply through the substrate, the
thermal pad must be tied to the V- supply to prevent
unwanted current flow to the thermal pad. Do not tie this pin
to GND. Connecting this pin to GND could result in large
back biased currents flowing between GND and V-. The
ISL59445 uses the package with pad dimensions of
D2 = 2.48mm and E2 = 3.4mm.
Maximum AC performance is achieved if the thermal pad is
attached to a dedicated de-coupled layer in a multi-layered
PC board. In cases where a dedicated layer is not possible,
AC performance may be reduced at upper frequencies.
The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
eliminates the need for individual thermal pad area. When a
dedicated layer is not possible a 1” x 1” pad area is sufficient
for the ISL59445 that is dissipating 0.5W in +50°C ambient.
Pad area requirements should be evaluated on a case by
case basis.
11
FN7456.2
September 8, 2005
5V
OPTIONAL SCHOTTKY PROTECTION
Y1
Y2
31
1
Y3
7
R
12
12
Pb1
29
Pb2
3
Pb3
G
9
14
Pr1
27
Pr2
5
Pr3
10
16
B
R3
75Ω
R5
75Ω
R2
75Ω
R4
75Ω
R7
75Ω
R9
75Ω
R6
75Ω
23
22
OUTB
20
OUTC
19
IN1B
GNDA
32
IN2B
GNDB
6
IN3B
GNDC
11
IN3A
INOB
INOC
IN1C
IN2C
IN3C
R12
75Ω
1nF
NIC
2
NIC
NIC
4
8
NIC
13
NIC
15
NIC
24
NIC
28
NIC
30
HIZ
26
ENABLE 25
QFN
S0 18
S1 17
5V
H SYNC
1
5V
0.1µF
0.1µF
-5V
ISL84517IH-T
V+
COM
V-
SOT-23
IN
4
ISL84517IH-T
V SYNC
1
V+
COM
V-
SOT-23
IN
4
5
1nF
1nF
5
0.1µF
0.1µF
1nF
1nF
-5V
3
NC 2
5V
0.1µF
NC7ST00P5X
3
5V 5
NC 2
1nF
INPUT 1
FN7456.2
September 8, 2005
4 OUT
3
GND
INPUT 2
SC70
LOGIC INPUTS
FIGURE 22. APPLICATION SHOWING THREE YPBPR CHANNELS AND ONE RGB+HV CHANNEL
-5V
1nF
21
VOUTA
IN2A
R11
75Ω
R10
75Ω
R8
75Ω
V+
ISL59445IL
0.1µF
R16
500Ω
R18
500Ω
R17
500Ω
ISL59424, ISL59445
R1
75Ω
INOA
IN1A
0.1µF
ISL59424, ISL59445
QFN Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
<http://www.intersil.com/design/packages/index.asp>
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN7456.2
September 8, 2005