EL4340, EL4342 ® Data Sheet September 21, 2005 FN7421.1 500MHz Triple, Multiplexing Amplifiers Features The EL4340 and EL4342 are fixed unity gain mux amps featuring high slew rates and excellent bandwidth for video switching. These devices feature a high impedance output state (HIZ) that enables the outputs of multiple devices to be wired together. A power-down mode (ENABLE) is included to turn off un-needed circuitry in power sensitive applications. The ENABLE pin, when pulled high, sets the EL4340 and EL4342 into standby power mode - consuming just 18mW. An added feature in the EL4340 is a latch enable function (LE) that allows independent logic control using a common logic bus. • Triple 2:1 and 4:1 multiplexers for RGB Ordering Information • Supply current 11mA/ch (EL4340) and 16mA/ch (EL4342) PART NUMBER PACKAGE TAPE & REEL PKG. DWG. # • Internally set gain-of-1 • High speed three-state outputs (HIZ) • Power-down mode (ENABLE) • Latch enable (EL4340) • ±5V operation • ±870 V/µs slew rate • 500MHz bandwidth • Pb-free plus anneal available (RoHS compliant) Applications EL4340IU 24 Ld QSOP - MDP0040 EL4340IUZ (See Note) 24 Ld QSOP (Pb-free) - MDP0040 EL4340IU-T7 24 Ld QSOP 7” MDP0040 • Computer monitors EL4340IUZ-T7 (See Note) 24 Ld QSOP (Pb-free) 7” MDP0040 • Set-top boxes EL4340IU-T13 24 Ld QSOP 13” MDP0040 EL4340IUZ-T13 (See Note) 24 Ld QSOP (Pb-free) 13” MDP0040 EL4342ILZA (See Note) 32 Ld Exposed Pad 3.6 x 4.6 QFN (Pb-free) - MDP0046 EL4342ILZA-T7 (See Note) 32 Ld Exposed Pad 3.6 x 4.6 QFN (Pb-free) 7” MDP0046 EL4342ILZA-T13 (See Note) 32 Ld Exposed Pad 3.6 x 4.6 QFN (Pb-free) 13” MDP0046 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 • HDTV/DTV analog inputs • Video projectors • Security video • Broadcast video equipment TABLE 1. CHANNEL SELECT LOGIC TABLE EL4340 S0 ENABLE HIZ LE OUTPUT 0 0 0 0 INO (A, B, C) 1 0 0 0 IN1 (A, B, C) X 1 X X Power-down X 0 1 X High Z X 0 0 1 Last S0 State Preserved TABLE 2. CHANNEL SELECT LOGIC TABLE EL4342 S1 S0 ENABLE HIZ OUTPUT 0 0 0 0 IN0 (A, B, C) 0 1 0 0 IN1 (A, B, C) 1 0 0 0 IN2 (A, B, C) 1 1 0 0 IN3 (A, B, C) X X 1 X Power-down X X 0 1 High Z CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL4340, EL4342 Pinouts GND B 5 IN0C 6 NIC 7 8 NIC 9 NIC 2 IN1B 3 20 OUTA IN2A 7 16 VAV=1 GND C 11 NIC 8 15 NIC AV=1 IN2B 9 14 S0 IN1C 12 21 VAV=1 THERMAL PAD GNDB 6 17 OUTC 13 NIC LATCHED ON HIGH LE 23 V+ 22 OUTA IN1C 5 18 OUTB IN1B 10 AV=1 NIC 4 19 V+ AV=1 24 NIC 20 OUTB 19 OUTC 18 S0 17 S1 IN2C 10 IN1A AV=1 26 HIZ 21 HIZ 25 ENABLE IN3C 16 4 27 IN0C NIC IN1A 1 NIC 15 22 ENABLE 28 NIC 3 IN3B 14 IN0B 29 IN0B 23 LE NIC 13 2 IN3A 12 GND A 31 IN0A 24 NIC GNDC 11 1 32 GNDA IN0A 30 NIC EL4342 (32 LD QFN) TOP VIEW EL4340 (24 LD QSOP) TOP VIEW THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE TIED TO V- NIC = NO INTERNAL CONNECTION NIC = NO INTERNAL CONNECTION Functional Diagram EL4340 Functional Diagram EL4342 EN0 S0 S0 EN0 DECODE EN1 DL Q C DL Q C EN1 IN0(A, B, C) OUT S1 IN1(A, B, C) DECODE IN1(A, B, C) IN0(A, B, C) EN2 OUT IN2(A, B, C) IN3(A, B, C) EN3 AMPLIFIER BIAS LE AMPLIFIER BIAS HIZ HIZ ENABLE A logic high on LE will latch the last S0 state. This logic state is preserved when cycling HIZ or ENABLE functions. 2 ENABLE FN7421.1 September 21, 2005 EL4340, EL4342 Absolute Maximum Ratings (TA = 25°C) Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, Input Video = 1VP-P & RL = 500Ω to GND, CL = 5pF unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 26 30 34 mA 39 46 50 mA GENERAL ±IS Enabled Enabled Supply Current (EL4340) No load, VIN = 0V, Enable Low Enabled Supply Current (EL4342) +IS Disabled Disabled Supply Current (EL4340) No load, VIN = 0V, Enable High 2.3 2.8 3.3 mA Disabled Supply Current (EL4342) No load, VIN = 0V, Enable High 3 3.5 4 mA Disabled Supply Current No load, VIN = 0V, Enable High 10 100 µA VOUT Positive and Negative Output Swing VIN = ±3.5V, RL = 500Ω ±3.1 ±3.4 V IOUT Output Current RL = 10Ω to GND ±80 ±135 mA VOS Output Offset Voltage (EL4340) -15 7 VOS Output Offset Voltage (EL4342) -10 -IS Disabled Ib +15 mV +10 mV -3 µA Input Bias Current VIN = 0V ROUT HIZ Output Resistance HIZ = Logic High 1.4 MΩ ROUT Enabled Output Resistance HIZ = Logic Low 0.2 Ω Input Resistance VIN = ±3.5V 10 MΩ Voltage Gain VIN = ±1.5V, RL= 500Ω Output Current in Three-state VOUT = 0V RIN ACL or AV ITRI -1 -2 0.98 0.99 1.02 V/V 8 15 22 µA LOGIC VIH Input High Voltage (Logic Inputs) VIL Input Low Voltage (Logic Inputs) IIH Input High Current (Logic Inputs) VH = 5V IIL Input Low Current (Logic Inputs) 0.1% Settling Time 2 V 0.8 V 270 320 µA VL = 0V 2 3 µA Step = 1V 10 ns 235 AC GENERAL tS PSRR (EL4340) Power Supply Rejection Ratio DC, PSRR V+ & V- combined 52 72 dB PSRR (EL4342) Power Supply Rejection Ratio DC, PSRR V+ & V- combined 52 56 dB 75 dB ISO Channel Isolation 3 f = 10MHz, Ch-Ch X-Talk and Off Isolation, CL = 1.5pF FN7421.1 September 21, 2005 EL4340, EL4342 Electrical Specifications PARAMETER V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, Input Video = 1VP-P & RL = 500Ω to GND, CL = 5pF unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT dG Differential Gain Error NTC-7, RL = 150, CL = 1.5pF 0.02 % dP Differential Phase Error NTC-7, RL = 150, CL = 1.5pF 0.02 ° BW -3dB Bandwidth CL = 1.5pF 500 MHz FBW 0.1dB Bandwidth CL = 1.5pF 60 MHz 0.1dB Bandwidth CL = 4.7pF 120 MHz Slew Rate 25% to 75%, RL = 150Ω, Input Enabled, CL = 1.5pF ±870 V/µs SR SWITCHING CHARACTERISTICS Channel -to-Channel Switching Glitch VIN = 0V, CL = 1.5pF 40 mVP-P Enable Switching Glitch VIN = 0V CL = 1.5pF 300 mVP-P HIZ Switching Glitch VIN = 0V CL = 1.5pF 200 mVP-P Channel -to-Channel Switching Glitch VIN = 0V CL = 1.5pF 20 mVP-P Enable Switching Glitch VIN = 0V CL = 1.5pF 200 mVP-P HIZ Switching Glitch VIN = 0V CL = 1.5pF 200 mVP-P tSW-L-H Channel Switching Time Low to High 1.2V logic threshold to 10% movement of analog output 18 ns tSW-H-L Channel Switching Time High to Low 1.2V logic threshold to 10% movement of analog output 20 ns tr, tf Rise & Fall Time 10% to 90% 1.1 ns tpd Propagation Delay 10% to 10% 0.9 ns tLH Latch Enable Hold time (EL4340 only) LE = 0 10 ns VGLITCH EL4340 VGLITCH EL4342 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. 10 5 SOURCE POWER=-20dBm 6 CL=11.5pF 4 CL=7.3pF 3 CL=6.2pF 2 0 -2 CL=4.7pF -4 CL=2.2pF -6 CL=1.5pF CL INCLUDES 1.5pF BOARD CAPACITANCE -8 SOURCE POWER=-20dBm 4 CL=16.5pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 8 2 1 0 -1 RL=100Ω -2 RL=150Ω -3 RL=500Ω -4 RL=1kΩ -5 -10 1 10 100 FREQUENCY (MHz) FIGURE 1. GAIN vs FREQUENCY vs CL 4 1K 1 10 100 1K FREQUENCY (MHz) FIGURE 2. GAIN vs FREQUENCY vs RL FN7421.1 September 21, 2005 EL4340, EL4342 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. 100 0.2 SOURCE 0.1 POWER=-20dBm -0.1 OUTPUT RESISTANCE (Ω) CL=4.7pF 0 NORMALIZED GAIN (dB) (Continued) ² -0.2 CL=1.5pF -0.3 -0.4 -0.5 -0.6 10 1 -0.7 -0.8 10 100 FREQUENCY (MHz) 1 0.1 0.1 1K 100 1K FIGURE 4. ROUT vs FREQUENCY 0.8 0.8 RL=500Ω CL=1.5pF 0.6 RL=500Ω CL=1.5pF 0.6 OUTPUT VOLTAGE (V) 0.4 0.2 0 -0.2 -0.4 0.4 0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 TIME (5ns/DIV) TIME (5ns/DIV) FIGURE 5. EL4340 TRANSIENT RESPONSE FIGURE 6. EL4342 TRANSIENT RESPONSE 0 0 -10 -10 INPUT X TO OUTPUT Y CROSSTALK -20 -30 -40 -40 (dB) OFF ISOLATION INPUT X TO OUTPUT X -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 -100 0.1 INPUT X TO OUTPUT Y CROSSTALK -20 -30 (dB) 10 FREQUENCY (MHz) FIGURE 3. 0.1dB GAIN vs FREQUENCY OUTPUT VOLTAGE (V) 1 1 10 100 FREQUENCY (MHz) FIGURE 7. EL4340 CROSSTALK AND OFF ISOLATION 5 1K -100 0.1 OFF ISOLATION INPUT X TO OUTPUT X ² 1 10 100 1K FREQUENCY (MHz) FIGURE 8. EL4342 CROSSTALK AND OFF ISOLATION FN7421.1 September 21, 2005 EL4340, EL4342 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. 20 20 PSRR (V+) 10 0 0 -10 -10 -20 PSRR (dB) PSRR (dB) 10 PSRR (V-) -30 -40 PSRR (V+) PSRR (V-) -20 -30 -40 -50 -50 -60 -60 -70 -70 -80 0.3 1 10 100 -80 0.3 1K 1 100 1K FIGURE 9. EL4340 PSRR CHANNELS A, B, C FIGURE 10. EL4342 PSRR CHANNELS A, B, C S0, S1 50Ω TERM. S0, S1 50Ω TERM. 1V/DIV 1V/DIV VIN = 0V VIN = 1V 0 0.5V/DIV 0 20mV/DIV 10 FREQUENCY (MHz) FREQUENCY (MHz) 0 VOUT A, B, C 0 VOUT A, B, C 20ns/DIV 20ns/DIV FIGURE 11. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V ENABLE 50Ω TERM. FIGURE 12. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V VIN = 1V ENABLE VIN = 0V 1V/DIV 1V/DIV 50Ω TERM. 0 0 VOUT A, B, C 1V/DIV 100mV/DIV (Continued) 0 20ns/DIV FIGURE 13. ENABLE SWITCHING GLITCH VIN = 0V 6 0 VOUT A, B, C 20ns/DIV FIGURE 14. ENABLE TRANSIENT RESPONSE VIN = 1V FN7421.1 September 21, 2005 EL4340, EL4342 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. HIZ HIZ VIN = 0V 1V/DIV 1V/DIV 0 1V/DIV 0 200mv/DIV VIN=1V 50Ω TERM. 50Ω TERM. 0 VOUT A, B, C VOUT A, B, C 0 10ns/DIV 10ns/DIV FIGURE 15. HIZ SWITCHING GLITCH VIN = 0V FIGURE 16. HIZ TRANSIENT RESPONSE VIN = 1V 60 3 50 2.5 POWER DISSIPATION (W) VOLTAGE NOISE (nV/√Hz) (Continued) 40 30 20 10 0 100 10K 2.857W QFN32 θJA=35°C/W 2 1.5 1.136W 1 QSOP24 θJA=88°C/W 0.5 0 1K JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 100K 0 25 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FREQUENCY (Hz) FIGURE 17. INPUT NOISE vs FREQUENCY (OUTPUT A, B, C) 1.2 POWER DISSIPATION (W) 50 FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 870mW 0.8 QSOP24 θJA=115°C/W 758mW 0.6 QFN32 θJA=125°C/W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 7 FN7421.1 September 21, 2005 EL4340, EL4342 IEL4342 (32 LD QFN) EL4340 (24 LD QFN) PIN NAME EQUIVALENT CIRCUIT 1 8 IN1A Circuit 1 2, 4, 8, 13, 15, 4, 7, 9, 13, 15, 24, 28, 30 24 NIC DESCRIPTION Channel 1 input for output amplifier "A" Not Internally Connected; it is recommended these pins be tied to ground to minimize crosstalk. 3 10 IN1B Circuit 1 Channel 1 input for output amplifier "B" 5 12 IN1C Circuit 1 Channel 1 input for output amplifier "C" 6 5 GNDB Circuit 4 Ground pin for output amplifier “B” 7 NA IN2A Circuit 1 Channel 2 input for output amplifier "A" 9 NA IN2B Circuit 1 Channel 2 input for output amplifier "B" 10 NA IN2C Circuit 1 Channel 2 input for output amplifier "C" 11 11 GNDC Circuit 4 Ground pin for output amplifier “C” 12 NA IN3A Circuit 1 Channel 3 input for output amplifier "A" 14 NA IN3B Circuit 1 Channel 3 input for output amplifier "B" 16 NA IN3C Circuit 1 Channel 3 input for output amplifier "C" 17 NA S1 Circuit 2 Channel selection pin MSB (binary logic code) 18 14 S0 Circuit 2 Channel selection pin. LSB (binary logic code) 19 17 OUTC Circuit 3 Output of amplifier “C” 20 18 OUTB Circuit 3 Output of amplifier “B” 21 16 V- Circuit 4 Negative power supply 22 20 OUTA Circuit 3 Output of amplifier “A” 23 19 V+ Circuit 4 Positive power supply 25 22 ENABLE Circuit 2 Device enable (active low). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic High on this pin puts device into powerdown mode. In power-down mode only logic circuitry is active. All logic states are preserved post power-down. This state is not recommended for logic control where more than one MUX-amp share the same video output line. 23 LE Circuit 2 Device latch enable on the ISL59424. A logic high on LE will latch the last (S0, S1) logic state. HIZ and ENABLE functions are not latched with the LE pin. 26 21 HIZ Circuit 2 Output disable (active high). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic high, puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. 27 6 IN0C Circuit 1 Channel 0 for output amplifier "C" 29 3 IN0B Circuit 1 Channel 0 for output amplifier "B" 31 1 IN0A Circuit 1 Channel 0 for output amplifier "A" 32 2 GNDA Circuit 4 Ground pin for output amplifier “A” V+ IN LOGIC PIN 21K 33K + 1.2V - V- CIRCUIT 1 V+ V+ GND OUT V- VCIRCUIT 2 CIRCUIT 3 THERMAL HEAT SINK PAD V+ GNDA CAPACITIVELY COUPLED ESD CLAMP GNDB GNDC ~1MΩ VSUBSTRATE VCIRCUIT 4 8 FN7421.1 September 21, 2005 EL4340, EL4342 split between the PCB capacitance and an external load capacitor. AC Test Circuits EL4340 & EL4342 Ground Connections VIN CL 5pF 50Ω or 75Ω For the best isolation and crosstalk rejection, all GND pins and NIC pins must connect to the GND plane. RL 500Ω Control Signals S0, S1, ENABLE, LE, HIZ - These are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select the inputs. All three amplifiers are switched simultaneously from their respective inputs. The ENABLE, LE, HIZ pins are used to disable the part to save power, latch in the last logic state and three-state the output amplifiers, respectively. For control signal rise and fall times less than 10ns the use of termination resistors close to the part will minimize transients coupled to the output. FIGURE 20A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD TEST EQUIPMENT EL4340 & EL4342 RS VIN 50Ω or 75Ω CL 5pF 475Ω 50Ω or 75Ω 50Ω or 75Ω FIGURE 20B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR 75Ω INPUT TERMINATED EQUIPMENT RS CL 5pF 50Ω or 75Ω The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT- triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply rates-of-rise in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. TEST EQUIPMENT EL4340 & EL4342 VIN Power-up Considerations 50Ω or 75Ω 50Ω or 75Ω FIGURE 20C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω WILL BE DEGRADED. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 21) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. FIGURE 20. TEST CIRCUITS Figure 20A illustrates the optimum output load for testing AC performance. Figure 20B illustrates the optimun output load when connecting to 50Ω input terminated equipment. Application Information If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+ General The EL4340 and EL4342 triple 2:1 and 4:1 MUX amps are ideal as the matrix element of high performance switchers and routers. Key features include buffered high impedance analog inputs and excellent AC performance at output loads down to 150Ω for video cable-driving. The unity-gain current feedback output amplifiers are stable operating into capacitive loads and bandwidth is optimized with a load of 5pF in parallel with a 500Ω. Total output capacitance can be V+ SUPPLY SCHOTTKY PROTECTION LOGIC V+ LOGIC CONTROL S0 POWER GND GND SIGNAL IN0 EXTERNAL CIRCUITS V+ V- V+ V+ V+ OUT V- DE-COUPLING CAPS IN1 VV- V- V- SUPPLY FIGURE 21. SCHOTTKY PROTECTION CIRCUIT 9 FN7421.1 September 21, 2005 EL4340, EL4342 HIZ State An internal pull-down resistor ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 15ns (Figure 16) by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4MΩ with approximately 1.5pF in parallel with a 10µA bias current from the output. Use this state when more than one mux shares a common output. In the HIZ state the output is three-stated, and maintains its high Z even in the presence of high slew rates. The supply current during this state is same as the active state. ENABLE and Power-down States The enable pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the ENABLE pin. The Power-down state is established within approximately 80ns (Figure 14), if a logic high (>2V) is placed on the ENABLE pin. In the Power-down state, the output has no leakage but has a large variable capacitance (on the order of 15pF), and is capable of being back-driven. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Do not use this state as a high impedance output when several MUX amps share the same output line. LE State The EL4340 is equipped with a Latch Enable pin. A logic high (>2V) on the LE pin latches the last logic state. This logic state is preserved when cycling HIZ or ENABLE functions. Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. Application Example Figure 22 illustrates the use of the EL4342, two ISL84517 SPST switches and one NC7ST00P5X NAND gate to mux 3 different component video signals and one RGB video signal. The SPDT switches provide the sync signal for the RGB video and disconnects the sync signal for the component signal. PC Board Layout The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid 10 sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip line are used. • Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. • Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. • Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. • When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01µF) as close to the devices as possible - Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. • The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad The thermal pad is electrically connected to V- supply through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the V- supply through the substrate, the thermal pad must be tied to the V- supply to prevent unwanted current flow to the thermal pad. Do not tie this pin to GND as this could result in large back biased currents flowing between GND and V-. The EL4342 uses the package with pad dimensions of D2 = 2.48mm and E2 = 3.4mm. Maximum AC performance is achieved if the thermal pad is attached to a dedicated de-coupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer eliminates the need for individual thermal pad area. When a dedicated layer is not possible a 1” x 1” pad area is sufficient for the EL4342 that is dissipating 0.5W in +50°C ambient. Pad area requirements should be evaluated on a case by case basis. FN7421.1 September 21, 2005 5V OPTIONAL SCHOTTKY PROTECTION Y1 Y2 31 Y3 7 R 12 1 11 Pb1 29 Pb2 3 Pb3 G 9 14 Pr1 27 Pr2 5 Pr3 10 16 B R3 75Ω R5 75Ω R2 75Ω R4 75Ω R7 75Ω R9 75Ω R6 75Ω VOUTA IN2A IN3A 23 OUTC 19 IN1B GNDA 32 IN2B GNDB 6 IN3B GNDC 11 INOC IN1C IN2C IN3C R12 75Ω NIC 2 NIC NIC 4 8 NIC 13 NIC 15 NIC 24 NIC 28 NIC 30 HIZ 26 ENABLE 25 QFN S0 18 S1 17 5V H SYNC 1 5V V SYNC ISL84517IH-T 1 V+ COM V- SOT-23 IN FN7421.1 September 21, 2005 4 0.1µF 0.1µF -5V ISL84517IH-T V+ COM V- SOT-23 IN 4 5 3 1nF 1nF 5 0.1µF 1nF 0.1µF -5V 1nF 3 NC 2 5V 0.1µF NC7ST00P5X 5V 5 NC 2 1nF INPUT 1 4 OUT 3 GND INPUT 2 SC70 LOGIC INPUTS FIGURE 22. APPLICATION SHOWING THREE YPBPR CHANNELS AND ONE RGB+HV CHANNEL 1nF 22 20 INOB 1nF -5V 21 OUTB R11 75Ω R10 75Ω R8 75Ω V+ EL4342IL 0.1µF R16 500Ω R18 500Ω R17 500Ω EL4340, EL4342 R1 75Ω INOA IN1A 0.1µF EL4340, EL4342 QSOP Package Outline Drawing ® 12 FN7421.1 September 21, 2005 EL4340, EL4342 QFN Package Outline Drawing NOTE: The package drawings shown here may not be the latest versions. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN7421.1 September 21, 2005