500MHz Triple 4:1 Gain-of-2, Multiplexing Amplifier ISL59446 Features The ISL59446 is a triple channel 4:1 multiplexer featuring integrated amplifiers with a fixed gain of 2, high slew rate and excellent bandwidth for video switching. The device features a three-state output (HIZ), which allows the outputs of multiple devices to be tied together. A power-down mode (ENABLE) is included to turn off unneeded circuitry in power sensitive applications. When the ENABLE pin is pulled high, the part enters a power-down mode and consumes just 14mW. • 510MHz bandwidth into 150Ω TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59446 • ±1600V/µs slew rate • High impedance buffered inputs • Internally set gain-of-2 • High speed three-state outputs (HIZ) • Power-down mode (ENABLE) • ±5V operation • Supply current 11mA/ch S1 S0 ENABLE HIZ OUTPUT 0 0 0 0 IN0 (A, B, C) 0 1 0 0 IN1 (A, B, C) Applications 1 0 0 0 IN2 (A, B, C) • HDTV/DTV analog inputs 1 1 0 0 IN3 (A, B, C) • Video projectors X X 1 X Power-Down • Computer monitors X X 0 1 High Z • Pb-Free (RoHS compliant) • Set-top boxes • Security video • Broadcast video equipment EN0 S0 EN1 IN0 (A, B, C) IN1 (A, B, C) S1 DECODE EN2 + OUT IN2 (A, B, C) IN3 (A, B, C) EN3 AMPLIFIER BIAS HIZ ENABLE FIGURE 1. FUNCTIONAL DIAGRAM (EACH CHANNEL) July 31, 2014 FN6261.3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006, 2009, 2012, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL59446 -40 to +85 32 Ld QFN L32.5x6A ISL59446IRZ-T7 (Note 1) 59446 IRZ -40 to +85 32 Ld QFN L32.5x6A 26 HIZ 59446 IRZ 27 IN0C ISL59446IRZ 28 NIC PKG. DWG. # 29 IN0B PACKAGE (Pb-Free) 30 NIC PART TEMP RANGE MARKING (°C) 32 GNDA 25 ENABLE IN1A 1 NIC 2 22 OUTA x2 IN1C 5 GNDB 6 21 V20 OUTB THERMAL PAD IN2A 7 19 OUTC x2 NIC 8 18 S0 IN3C 16 17 S1 NIC 15 IN2B 9 IN2C 10 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL59446. For more information on MSL please see tech brief TB363. 23 V+ NIC 4 IN3B 14 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. IN1B 3 NIC 13 1. Please refer to TB347 for details on reel specifications. 24 NIC x2 IN3A 12 NOTES: GNDC 11 PART NUMBER (Notes 2, 3) Pin Configuration 31 IN0A Ordering Information THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE TIED TO VNIC = NO INTERNAL CONNECTION Pin Descriptions ISL59446 (32 LD QFN) PIN NAME EQUIVALENT CIRCUIT 1 IN1A Circuit 1 2, 4, 8, 13, 15, 24, 28, 30 NIC 3 IN1B Circuit 1 Channel 1 input for output amplifier "B" 5 IN1C Circuit 1 Channel 1 input for output amplifier "C" 6 GNDB Circuit 4 Ground pin for output amplifier “B” 7 IN2A Circuit 1 Channel 2 input for output amplifier "A" 9 IN2B Circuit 1 Channel 2 input for output amplifier "B" 10 IN2C Circuit 1 Channel 2 input for output amplifier "C" 11 GNDC Circuit 4 Ground pin for output amplifier “C” 12 IN3A Circuit 1 Channel 3 input for output amplifier "A" 14 IN3B Circuit 1 Channel 3 input for output amplifier "B" 16 IN3C Circuit 1 Channel 3 input for output amplifier "C" 17 S1 Circuit 2 Channel selection pin. MSB (binary logic code) 18 S0 Circuit 2 Channel selection pin. LSB (binary logic code) 19 OUTC Circuit 3 Output of amplifier “C” 20 OUTB Circuit 3 Output of amplifier “B” 21 V- Circuit 4 Negative power supply 22 OUTA Circuit 3 Output of amplifier “A” 23 V+ Circuit 4 Positive power supply Submit Document Feedback DESCRIPTION Channel 1 input for output amplifier "A" Not Internally Connected; it is recommended these pins be tied to ground to minimize crosstalk. 2 FN6261.3 July 31, 2014 ISL59446 Pin Descriptions (Continued) ISL59446 (32 LD QFN) PIN NAME EQUIVALENT CIRCUIT 25 ENABLE Circuit 2 Device enable (active low). Internal pull-down resistor ensures device is active with no connection to this pin. A logic High puts device into power-down mode and only the logic circuitry is active. Logic states are preserved post power-down. 26 HIZ Circuit 2 Output disable (active high). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic high, puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. 27 IN0C Circuit 1 Channel 0 for output amplifier "C" 29 IN0B Circuit 1 Channel 0 for output amplifier "B" 31 IN0A Circuit 1 Channel 0 for output amplifier "A" 32 GNDA Circuit 4 Ground pin for output amplifier “A” DESCRIPTION V+ IN LOGIC PIN 21k 33k + 1.2V - V- CIRCUIT 1 V+ V+ GND OUT V- VCIRCUIT 2 CIRCUIT 3 THERMAL HEAT SINK PAD V+ GNDA CAPACITIVELY COUPLED ESD CLAMP GNDB GNDC ~1M VSUBSTRATE VCIRCUIT 4 Submit Document Feedback 3 FN6261.3 July 31, 2014 ISL59446 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Digital and Analog Input Current (Note 4) . . . . . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . . 2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 32 Ld QFN Package (Notes 5, 6) . . . . . . . . 43 10 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 28 Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, VOUT = ±2VP-P and RL = 500 to GND, CL = 0pF, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNIT GENERAL +IS Enabled Enabled Supply Current No load, VIN = 0V, Enable Low 40 44 50 mA -IS Enabled Enabled Supply Current No load, VIN = 0V, Enable Low -46 -41 -37 mA +IS Disabled Disabled Supply Current No load, VIN = 0V, Enable High 3 3.4 4 mA -IS Disabled Disabled Supply Current No load, VIN = 0V, Enable High -40 -6 VOUT Positive and Negative Output Swing VIN = ±2.5V; RL = 500 ±3.8 ±4.0 ±4.2 V IOUT Output Current VIN = 0.825V RL = 10 ±80 ±135 ±180 mA VOS Output Offset Voltage -40 0 +40 mV -4 -2 -1 µA 700 900 1150 Ib µA Input Bias Current VIN = 0V ROUT HIZ Output Resistance HIZ = Logic High ROUT Enabled Output Resistance HIZ = Logic Low 0.2 Input Resistance VIN = ±1.75V 10 M Voltage Gain RL = 500 RIN ACL or AV 1.94 1.99 2.04 V/V LOGIC VIH Input High Voltage (Logic Inputs) 2 V VIL Input Low Voltage (Logic Inputs) 0.8 V IIH Input High Current (Logic Inputs) VH = 5V 200 260 320 µA IIL Input Low Current (Logic Inputs) VL = 0V -4 -2 -1 µA PSRR Power Supply Rejection Ratio DC, PSRR V+ and V- combined VOUT = 0dBm 45 53 dB Xtalk Channel-to-Channel Crosstalk f = 10MHz, ChX-Ch Y-Talk VIN = 1VP-P; CL = 1.1pF 74 dB Off-State Isolation f = 10MHz, Ch-Ch Off Isolation VIN = 1VP-P; CL = 1.1pF 76 dB Differential Gain Error NTC-7, RL = 150, CL = 1.1pF 0.008 % AC GENERAL Off - ISO dG Submit Document Feedback 4 FN6261.3 July 31, 2014 ISL59446 Electrical Specifications PARAMETER V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, VOUT = ±2VP-P and RL = 500 to GND, CL = 0pF, unless otherwise specified. (Continued) DESCRIPTION TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNIT dP Differential Phase Error NTC-7, RL = 150, CL = 1.1pF 0.01 ° BW Small Signal -3dB Bandwidth VOUT = 0.2VP-P; RL = 500, CL = 1.1pF 620 MHz VOUT = 0.2VP-P; RL = 150, CL = 2.1pF 530 MHz VOUT = 2VP-P; RL = 500, CL = 1.1pF 280 MHz VOUT = 2VP-P; RL = 150, CL = 1.1pF 260 MHz VOUT = 2VP-P; RL = 500, CL = 1.1pF 160 MHz VOUT = 2VP-P; RL = 150, CL = 1.1pF 50 MHz 1600 V/µs Large Signal -3dB Bandwidth FBW SR 0.1dB Bandwidth Slew Rate 25% to 75%, RL = 150, Input Enabled, CL = 2.1pF TRANSIENT RESPONSE tr, tf Large Signal Large Signal Rise, Fall Times, tr, tf, 10% - 90% VOUT = 2VP-P; RL = 500, CL = 1.1pF 1.2 ns VOUT = 2VP-P; RL = 150, CL = 2.1pF 1.3 ns tr, tf, Small Signal Small Signal Rise, Fall Times, tr, tf, 10% - 90% VOUT = 0.2VP-P; RL = 500, CL = 1.1pF 0.7 ns VOUT = 0.2VP-P; RL = 150, CL = 2.1pF 0.9 ns VOUT = 2VP-P; RL = 500, CL = 1.1pF 7.2 ns VOUT = 2VP-P; RL = 150, CL = 2.1pF 8.2 ns VOUT = 2VP-P; RL = 500, CL = 1.1pF 4 ns VOUT = 2VP-P; RL = 150, CL = 2.1pF 4.3 ns VIN = 0V, RL = 500CL = 1.1pF 90 mVP-P VIN = 0V, RL = 150CL = 2.1pF 15 mVP-P VIN = 0V, RL = 500CL = 1.1pF 1.8 VP-P VIN = 0V, RL = 150CL = 2.1pF 1.35 VP-P VIN = 0V, RL = 500CL = 1.1pF 340 mVP-P VIN = 0V, RL = 150CL = 2.1pF 340 mVP-P ts 0.1% ts 1% Settling TIme to 0.1% Settling TIme to 1% SWITCHING CHARACTERISTICS VGLITCH Channel - to- Channel Switching Glitch Enable Switching Glitch HIZ Switching Glitch tSW-L-H Channel Switching Time Low to High 1.2V logic threshold to 10% movement of analog output 24 ns tSW-H-L Channel Switching Time High to Low 1.2V logic threshold to 10% movement of analog output 24 ns Propagation Delay 10% to 10% 0.55 ns tpd NOTE: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Submit Document Feedback 5 FN6261.3 July 31, 2014 ISL59446 Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified. 10 10 VOUT = 0.2VP-P 8 CL = 7.4pF CL = 6.2pF 4 CL = 4.5pF 2 0 -2 CL = 3.3pF -4 CL = 2.1pF CL INCLUDES 0.6pF BOARD CAPACITANCE -8 -10 1M 100M CL = 6.2pF 2 0 CL = 4.5pF -2 CL = 3.3pF -4 CL = 2.1pF -6 CL = 0.6pF 10M CL = 10.6pF CL = 8.8pF 4 CL = 1.1pF -6 CL INCLUDES 0.6pF BOARD CAPACITANCE -8 -10 1G 1M 1G FIGURE 3. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD 10 10 VOUT = 2VP-P 8 CL = 8.8pF 2 0 CL = 2.1pF -2 CL = 0.6pF -4 -6 1M CL = 5.3pF 4 2 0 CL = 2.1pF -2 CL = 0.6pF -4 -6 CL INCLUDES 0.6pF BOARD CAPACITANCE -8 CL INCLUDES 0.6pF BOARD CAPACITANCE -8 10M 100M 1G -10 1M FREQUENCY (Hz) FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 500 LOAD 2 1 0.3 0.2 0 NORMALIZED GAIN (dB) RL = 250Ω -2 RL = 150Ω -3 -4 -5 RL = 150Ω CL = 2.1pF 0 -0.1 -0.2 -0.4 -0.5 -7 -0.6 10M 100M FREQUENCY (Hz) FIGURE 6. GAIN vs FREQUENCY vs RL Submit Document Feedback 6 1G RL = 500Ω CL = 1.1pF -0.3 -6 1M 1G VOUT = 0.2VP-P 0.1 -1 -8 10M 100M FREQUENCY (Hz) FIGURE 5. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD RL = 1kΩ RL = 500Ω VOUT = 0.2VP-P CL = 1.1pF CL = 12.6pF 6 NORMALIZED GAIN (dB) CL = 5.3pF 4 VOUT = 2VP-P 8 6 NORMALIZED GAIN (dB) 100M FREQUENCY (Hz) FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 500 LOAD NORMALIZED GAIN (dB) CL = 0.6pF 10M FREQUENCY (Hz) -10 CL = 12.6pF 6 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 6 VOUT = 0.2VP-P 8 CL = 8.8pF -0.7 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 7. 0.1dB GAIN FLATNESS FN6261.3 July 31, 2014 ISL59446 Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified. (Continued) 10k 100 VSOURCE = 2VP-P OUTPUT IMPEDANCE () OUTPUT IMPEDANCE () VSOURCE = 2VP-P 10 1 0.1 100k 1M 10M 100M 1k 100 10 100k 1G 1M 100M 1G FIGURE 9. ZOUT vs FREQUENCY - HIZ FIGURE 8. ZOUT vs FREQUENCY - ENABLED 1M 10 VSOURCE = 2VP-P VSOURCE = 0.5VP-P 0 100k PSRR (V-) -10 10k PSRR (dB) INPUT IMPEDANCE () 10M FREQUENCY (Hz) FREQUENCY (Hz) 1k -20 -30 100 -40 PSRR (V-) 10 -50 1 300k 1M 10M 100M FREQUENCY (Hz) -60 300k 1G 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 11. PSRR vs FREQUENCY FIGURE 10. ZIN vs FREQUENCY 0 -10 60 VIN = 1VP-P VOLTAGE NOISE (nV/Hz) -20 CROSSTALK RL = 500 -30 INPUT X TO OUTPUT Y RL = 150 (dB) -40 OFF ISOLATION RL = 500 -50 INPUT X TO OUTPUT X RL = 150 -60 -70 -80 50 40 30 20 10 -90 -100 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 12. CROSSTALK AND OFF ISOLATION Submit Document Feedback 7 1G 0 100 1k 10k 100k FREQUENCY (Hz) FIGURE 13. INPUT NOISE vs FREQUENCY FN6261.3 July 31, 2014 ISL59446 VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified. (Continued) 0.002 0 -0.002 -0.004 -0.006 -0.008 -0.010 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -4 -3 -2 -1 1 0 VOUT DC (V) 2 3 4 NORMALIZED PHASE (°) NORMALIZED GAIN (dB) NORMALIZED PHASE (°) NORMALIZED GAIN (dB) Typical Performance Curves 0.010 0.008 0.006 0.004 0.002 0 -0.002 -0.004 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -4 -3 -2 -1 0 1 FIGURE 14. DIFFERENTIAL GAIN AND PHASE; VOUT = 0.2VP-P, FO = 3.58MHz, RL = 500 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.1 RL = 150 CL = 2.1pF 0.2 0 0.1 0 TIME (5ns/DIV) TIME (5ns/DIV) FIGURE 16. SMALL SIGNAL TRANSIENT RESPONSE; RL = 500 FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE; RL = 150 VOUT = 2VP-P VOUT = 2VP-P RL = 500 CL = 1.1pF RL = 150 CL = 2.1pF 2.0 OUTPUT VOLTAGE (V) 2.0 OUTPUT VOLTAGE (V) 4 VOUT = 0.2VP-P VOUT = 0.2VP-P 1.0 0 1.0 0 TIME (5ns/DIV) FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE; RL = 500 Submit Document Feedback 3 FIGURE 15. DIFFERENTIAL GAIN AND PHASE; VOUT = 0.2VP-P, FO = 3.58MHz, RL = 150 RL = 500 CL = 1.1pF 0.2 2 VOUT DC (V) 8 TIME (5ns/DIV) FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE; RL = 150 FN6261.3 July 31, 2014 ISL59446 Typical Performance Curves VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified. (Continued) 50 50 INPUT RISE, FALL TIMES <175ps VOUT = 1.4VP-P 40 OVERSHOOT (%) 40 OVERSHOOT (%) VOUT = 2VP-P 30 20 VOUT = 1VP-P INPUT RISE, FALL TIMES <175ps VOUT = 2VP-P VOUT = 1.4VP-P 30 20 VOUT = 1VP-P 10 10 VOUT = 0.2VP-P VOUT = 0.2VP-P 0 2 4 6 8 0 10 2 CL (pF) VIN = 0V 10 VIN = 1V S0, S1 50 TERM. 1V/DIV 1V/DIV 0 VOUT A, B, C 1V/DIV 20mV/DIV 8 FIGURE 21. PULSE OVERSHOOT vs VOUT, CL; RL = 150 0 0 0 VOUT A, B, C 20ns/DIV 20ns/DIV FIGURE 22. CHANNEL-TO-CHANNEL SWITCHING GLITCH VIN = 0V ENABLE 50 TERM. FIGURE 23. CHANNEL-TO-CHANNEL TRANSIENT RESPONSE VIN = 1V VIN = 1V ENABLE VIN = 0V 1V/DIV 1V/DIV 50 TERM. 0 0 VOUT A, B, C 2V/DIV 1V/DIV 6 CL (pF) FIGURE 20. PULSE OVERSHOOT vs VOUT, CL; RL = 500 S0, S1 50 TERM. 4 0 40ns/DIV FIGURE 24. ENABLE SWITCHING GLITCH VIN = 0V Submit Document Feedback 9 0 VOUT A, B, C 40ns/DIV FIGURE 25. ENABLE TRANSIENT RESPONSE VIN = 1V FN6261.3 July 31, 2014 ISL59446 Typical Performance Curves HIZ VS = ±5V, RL = 500 to GND, TA = +25°C, unless otherwise specified. (Continued) HIZ VIN = 0V 1V/DIV 1V/DIV 0 2V/DIV 0 200mv/DIV VIN = 1V 50Ω TERM. 50Ω TERM. 0 VOUT A, B, C VOUT A, B, C 0 20ns/DIV 20ns/DIV FIGURE 26. HIZ SWITCHING GLITCH VIN = 0V FIGURE 27. HIZ TRANSIENT RESPONSE VIN = 1V MAX POWER DISSIPATION (W) 3.5 3.0 32 LD 5mmx6mm QFN JA = 43°C/W 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 AMBIENT TEMPERATURE (°C) FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Submit Document Feedback 10 FN6261.3 July 31, 2014 ISL59446 Application Information AC Test Circuits ISL59446 VIN General LCRIT x2 VOUT *CL 1.1pF 50 or 75 RL 500or 150 *CL Includes PCB trace capacitance FIGURE 29A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD ISL59446 VIN x2 CL RS CS RL 500or 75 FIGURE 29B. INTER-STAGE APPLICATION CIRCUIT ISL59446 LCRIT x2 TEST EQUIPMENT RS 475 *CL 1.1pF 50 56.2 50 *CL Includes PCB trace capacitance FIGURE 29C. 500 TEST CIRCUIT WITH 50LOAD ISL59446 VIN LCRIT x2 TEST EQUIPMENT RS 118 *CL 2.1pF 50or 75 86.6 50 *CL Includes PCB trace capacitance FIGURE 29D. 150 TEST CIRCUIT WITH 50LOAD ISL59446 VIN 50 or 75 For the best isolation and crosstalk rejection, all GND pins and NIC pins must connect to the GND plane. AC Design Considerations LCRIT 50 or 75 VIN Key features of the ISL59446 include a fixed gain of 2, buffered high impedance analog inputs and excellent AC performance at output loads down to 150 for video cable-driving. The current feedback output amplifiers are stable operating into capacitive loads. LCRIT x2 TEST EQUIPMENT RS 50 or 75 *CL 2.1pF 50 or 75 *CL Includes PCB trace capacitance FIGURE 29E. BACKLOADED TEST CIRCUIT FOR 75 VIDEO CABLE APPLICATION AC Test Circuits Figures 29C and 29D illustrate the optimum output load for testing AC performance at 500 and 150 loads. Figure 29E illustrates the optimum output load for 50 and 75 cable-driving. Submit Document Feedback 11 High speed current-feed amplifiers are sensitive to capacitance at the inverting input and output terminals. The ISL59446 has an internally set gain of 2, so the inverting input is not accessible. Capacitance at the output terminal increases gain peaking (Figure 2) and pulse overshoot (Figures 20 and 21). The AC response of the ISL59446 is optimized for a total output capacitance of up to 2.1pF over the load range of 150 to 500 When PCB trace capacitance and component capacitance exceed 2pF, pulse overshoot becomes strongly dependent on the input pulse amplitude and slew rate. This effect is shown in Figures 20 and 21, which show approximate pulse overshoot as a function of input slew rate and output capacitance. Fast pulse rise and fall times (<150ns) at input amplitudes above 0.2V, cause the input pulse slew rate to exceed the 1600V/µs output slew rate of the ISL59446. At 125ps rise time, pulse input amplitudes >0.2V cause slew rate limit operation. Increasing levels of output capacitance reduce stability resulting in increased overshoot, and settling time. PC board trace length should be kept to a minimum in order to minimize output capacitance and prevent the need for controlled impedance lines. At 500MHz trace lengths approaching 1” begin exhibiting transmission line behavior and may cause excessive ringing if controlled impedance traces are not used. Figure 29A shows the optimum interstage circuit when the total output trace length is less than the critical length of the highest signal frequency. For applications where pulse response is critical and where interstage distances exceed LCRIT, the circuit shown in Figure 29B is recommended. Resistor RS constrains the capacitance seen by the amplifier output to the trace capacitance from the output pin to the resistor. Therefore, RS should be placed as close to the ISL59446 output pin as possible. For interstage distances much greater than LCRIT, the back-loaded circuit shown in Figure 29E should be used with controlled impedance PCB lines, with RS and RL equal to the controlled impedance. For applications where interstage distances are long, but pulse response is not critical, capacitor CS can be added to low values of RS to form a low-pass filter to dampen pulse overshoot. This approach avoids the need for the large gain correction required by the -6dB attenuation of the back-loaded controlled impedance interconnect. Load resistor RL is still required but can be 500 or greater, resulting in a much smaller attenuation factor. FN6261.3 July 31, 2014 ISL59446 Control Signals (>2V) on the HIZ pin. If the HIZ state is selected, the output impedance is ~1000 (Figure 9). The supply current during this state is same as the active state. S0, S1, ENABLE, HIZ - These are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select the inputs. All three amplifiers are switched simultaneously from their respective inputs. The ENABLE pin is used to disable the part to save power, and the HIZ pin to set the output stage in a high impedance state. For control signal rise and fall times less than 10ns the use of termination resistors close to the part may be necessary to prevent reflections and to minimize transients coupled to the output. ENABLE and Power-Down States The enable pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the ENABLE pin. The power-down state is established within approximately 200ns (Figure 25), if a logic high (>2V) is placed on the ENABLE pin. In the power-down state, the output has no leakage but has a large variable capacitance (on the order of 15pF), and is capable of being back-driven. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Therefore, the parallel connection of multiple outputs is not recommended unless the application can tolerate the limited power-down output impedance. Power-Up Considerations The ESD protection circuits use internal diodes from all pins to the V+ and V- supplies. In addition, a dV/dT- triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table on page 2. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply rates-of-rise in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 30) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. PC Board Layout The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+. • The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip line are used. HIZ State • Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. An internal pull-down resistor ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 20ns (Figure 27) by placing a logic high V+ SUPPLY SCHOTTKY PROTECTION LOGIC V+ LOGIC CONTROL S0 POWER GND GND SIGNAL IN0 V- V+ V+ OUT V+ V- DECOUPLING CAPS EXTERNAL CIRCUITS V+ IN1 V- VV- V- SUPPLY FIGURE 30. SCHOTTKY PROTECTION CIRCUIT Submit Document Feedback 12 FN6261.3 July 31, 2014 ISL59446 • Maximize use of AC decoupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e., no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. • Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. • When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • Minimum of 2 power supply decoupling capacitors are recommended (1000pF, 0.01µF) as close to the devices as possible - avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be further away. When vias are required in a layout, they should be routed as far away from the device as possible. • The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad The thermal pad is electrically connected to V- supply through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the V- supply through the substrate, the thermal pad must be tied to the V- supply to prevent unwanted current flow to the thermal pad. Do not tie this pin to GND as this could result in large back biased currents flowing between GND and V-. The ISL59446 package has pad dimensions of D2 = 2.48mm and E2 = 3.4mm. Maximum AC performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. • The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer eliminates the need for individual thermal pad area. When a dedicated layer is not possible a 1” x 1” pad area is sufficient for the ISL59446 that is dissipating 0.5W in +50°C ambient temperature. Pad area requirements should be evaluated on a case-by-case basis. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION July 31, 2014 FN6261.3 CHANGE Added Revision History. Electrical Spec Table on page 4 - made 3 limit changes as follows: +Is Enabled MAX from 48 to 50mA +Is Disabled MAX from 3.8 to 4mA -Is Enabled MIN from -45mA to -46mA About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 13 FN6261.3 July 31, 2014 ISL59446 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L32.5x6A (One of 10 Packages in MDP0046) 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 0.00 0.02 0.05 - D PIN #1 I.D. MARK E 5.00 BSC - D2 2.48 REF - E 6.00 BSC - E2 (N/2) 2X 0.075 C 2X 0.075 C 0.45 b 0.17 - 0.50 0.55 - 0.22 0.27 - c 0.20 REF b L - e 0.50 BSC - N 32 REF 4 ND 7 REF 6 NE 9 REF 5 0.10 M C A B Rev 1 2/09 NOTES: (N-2) (N-1) N N LEADS TOP VIEW 3.40 REF L 1. Dimensioning and tolerancing per ASME Y14.5M-1994. PIN #1 I.D. 2. Tiebar view shown is a non-functional feature. 3 1 2 3 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the “E” side of the package (or Y-direction). (E2) 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. NE 5 (N/2) 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 7 (D2) BOTTOM VIEW 0.10 C e C (c) SEATING PLANE 0.08 C N LEADS & EXPOSED PAD C 2 A (L) SEE DETAIL "X" A1 SIDE VIEW Submit Document Feedback N LEADS DETAIL X 14 FN6261.3 July 31, 2014