INTERSIL ISL59446

ISL59446
®
Data Sheet
May 19, 2006
500MHz Triple 4:1 Gain-of-2, Multiplexing
Amplifier
The ISL59446 is a triple channel 4:1 multiplexer featuring
integrated amplifiers with a fixed gain of 2, high slew-rate
and excellent bandwidth for video switching. The device
features a three-state output (HIZ), which allows the outputs
of multiple devices to be tied together. A power-down mode
(ENABLE) is included to turn off un-needed circuitry in power
sensitive applications. When the ENABLE pin is pulled high,
the part enters a power-down mode and consumes just
14mW.
FN6261.0
Features
• 510MHz bandwidth into 150Ω
• ±1600V/µs slew rate
• High impedance buffered inputs
• Internally set gain-of-2
• High speed three-state outputs (HIZ)
• Power-down mode (ENABLE)
• ±5V operation
• Supply current 11mA/ch
Ordering Information
• Pb-free plus anneal available (RoHS compliant)
PART NUMBER
PART
TAPE &
(Note)
MARKING REEL
ISL59446IRZ
PACKAGE
(Pb-Free)
PKG.
DWG. #
Applications
IRZ
-
32 Ld QFN
L32.5x6A
• HDTV/DTV analog inputs
ISL59446IRZ-T7 IRZ
7”
32 Ld QFN
L32.5x6A
• Video projectors
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Computer monitors
• Set-top boxes
• Security video
• Broadcast video equipment
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59446
S1
S0
ENABLE
HIZ
OUTPUT
0
0
0
0
IN0 (A, B, C)
0
1
0
0
IN1 (A, B, C)
1
0
0
0
IN2 (A, B, C)
1
1
0
0
IN3 (A, B, C)
X
X
1
X
Power-Down
X
X
0
1
High Z
26 HIZ
27 IN0C
28 NIC
29 IN0B
30 NIC
31 IN0A
32 GNDA
Pinout
IN1A 1
25 ENABLE
NIC 2
24 NIC
x2
23 V+
IN1B 3
22 OUTA
NIC 4
x2
IN1C 5
GNDB 6
Functional Diagram (each channel)
21 V-
EN0
20 OUTB
THERMAL
PAD
S0
19 OUTC
IN2A 7
x2
NIC 8
EN1
18 S0
DECODE
IN3C 16
NIC 15
IN3B 14
NIC 13
IN3A 12
GNDC 11
17 S1
IN2C 10
IN2B 9
S1
IN0(A, B, C)
IN1(A, B, C)
EN2
EN3
IN2(A, B, C)
+
OUT
IN3(A, B, C)
AMPLIFIER BIAS
THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE
TIED TO V-
HIZ
NIC = NO INTERNAL CONNECTION
ENABLE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59446
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . -40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, VOUT = ±2VP-P and RL = 500Ω to GND, CL = 0pF, unless otherwise
specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
+IS Enabled
Enabled Supply Current
No load, VIN = 0V, Enable Low
40
44
48
mA
-IS Enabled
Enabled Supply Current
No load, VIN = 0V, Enable Low
-45
-41
-37
mA
+IS Disabled
Disabled Supply Current
No load, VIN = 0V, Enable High
3
3.4
3.8
mA
-IS Disabled
Disabled Supply Current
No load, VIN = 0V, Enable High
-40
-6
VOUT
Positive and Negative Output Swing
VIN = ±2.5V; RL = 500Ω
±3.8
±4.0
±4.2
V
IOUT
Output Current
VIN = 0.825V RL = 10Ω
±80
±135
±180
mA
VOS
Output Offset Voltage
-40
-25
-10
mV
-4
-2
-1
µA
700
900
1150
Ω
Ib
µA
Input Bias Current
VIN = 0V
ROUT
HIZ Output Resistance
HIZ = Logic High
ROUT
Enabled Output Resistance
HIZ = Logic Low
0.2
Ω
Input Resistance
VIN = ±1.75V
10
MΩ
Voltage Gain
RL = 500Ω
RIN
ACL or AV
1.94
1.99
2.04
V/V
LOGIC
VIH
Input High Voltage (Logic Inputs)
2
V
VIL
Input Low Voltage (Logic Inputs)
0.8
V
IIH
Input High Current (Logic Inputs)
VH = 5V
200
260
320
µA
IIL
Input Low Current (Logic Inputs)
VL = 0V
-4
-2
-1
µA
PSRR
Power Supply Rejection Ratio
DC, PSRR V+ and V- combined
VOUT = 0dBm
45
53
dB
Xtalk
Channel to Channel Crosstalk
f = 10MHz, ChX-Ch Y-Talk
VIN = 1VP-P; CL = 1.1pF
74
dB
Off-State Isolation
f = 10MHz, Ch-Ch Off Isolation
VIN = 1VP-P; CL = 1.1pF
76
dB
dG
Differential Gain Error
NTC-7, RL = 150, CL = 1.1pF
0.008
%
dP
Differential Phase Error
NTC-7, RL = 150, CL = 1.1pF
0.01
°
AC GENERAL
Off - ISO
2
FN6261.0
May 19, 2006
ISL59446
Electrical Specifications
PARAMETER
BW
V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, VOUT = ±2VP-P and RL = 500Ω to GND, CL = 0pF, unless otherwise
specified. (Continued)
DESCRIPTION
Small Signal -3dB Bandwidth
Large Signal -3dB Bandwidth
FBW
SR
0.1dB Bandwidth
Slew Rate
CONDITIONS
MIN
TYP
MAX
UNIT
VOUT = 0.2VP-P; RL = 500Ω, CL = 1.1pF
620
MHz
VOUT = 0.2VP-P; RL = 150Ω, CL = 2.1pF
530
MHz
VOUT = 2VP-P; RL = 500Ω, CL = 1.1pF
280
MHz
VOUT = 2VP-P; RL = 150Ω, CL = 1.1pF
260
MHz
VOUT = 2VP-P; RL = 500Ω, CL = 1.1pF
160
MHz
VOUT = 2VP-P; RL = 150Ω, CL = 1.1pF
50
MHz
25% to 75%, RL = 150Ω, Input Enabled,
CL = 2.1pF
1600
V/µs
TRANSIENT RESPONSE
tr, tf Large
Signal
Large Signal Rise, Fall Times, tr, tf,
10% - 90%
VOUT = 2VP-P; RL = 500Ω, CL = 1.1pF
1.2
ns
VOUT = 2VP-P; RL = 150Ω, CL = 2.1pF
1.3
ns
tr, tf, Small
Signal
Small Signal Rise, Fall Times, tr, tf,
10% - 90%
VOUT = 0.2VP-P; RL = 500Ω, CL = 1.1pF
0.7
ns
VOUT = 0.2VP-P; RL = 150Ω, CL = 2.1pF
0.9
ns
Settling TIme to 0.1%
VOUT = 2VP-P; RL = 500Ω, CL = 1.1pF
7.2
ns
VOUT = 2VP-P; RL = 150Ω, CL = 2.1pF
8.2
ns
VOUT = 2VP-P; RL = 500Ω, CL = 1.1pF
4
ns
VOUT = 2VP-P; RL = 150Ω, CL = 2.1pF
4.3
ns
VIN = 0V, RL = 500Ω; CL = 1.1pF
90
mVP-P
VIN = 0V, RL = 150Ω; CL = 2.1pF
15
mVP-P
VIN = 0V, RL = 500Ω; CL = 1.1pF
1.8
VP-P
VIN = 0V, RL = 150Ω; CL = 2.1pF
1.35
VP-P
VIN = 0V, RL = 500Ω; CL = 1.1pF
340
mVP-P
VIN = 0V, RL = 150Ω; CL = 2.1pF
340
mVP-P
ts 0.1%
ts 1%
Settling TIme to 1%
SWITCHING CHARACTERISTICS
VGLITCH
Channel -to-Channel Switching Glitch
Enable Switching Glitch
HIZ Switching Glitch
tSW-L-H
Channel Switching Time Low to High
1.2V logic threshold to 10% movement of
analog output
24
ns
tSW-H-L
Channel Switching Time High to Low
1.2V logic threshold to 10% movement of
analog output
24
ns
Propagation Delay
10% to 10%
0.55
ns
tpd
3
FN6261.0
May 19, 2006
ISL59446
Typical Performance Curves
VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified.
10
10
VOUT = 0.2VP-P
8
CL = 7.4pF
CL = 6.2pF
4
CL = 4.5pF
2
0
-2
CL = 3.3pF
-4
CL = 2.1pF
CL = 1.1pF
-6
CL INCLUDES 0.6pF
BOARD CAPACITANCE
-8
-10
1M
CL = 10.6pF
CL = 8.8pF
4
CL = 6.2pF
2
0
CL = 4.5pF
-2
CL = 3.3pF
-4
CL = 2.1pF
-6
CL = 0.6pF
10M
CL INCLUDES 0.6pF
BOARD CAPACITANCE
-8
100M
-10
1G
1M
1G
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs CL
INTO 150Ω LOAD
10
10
VOUT = 2VP-P
8
CL = 8.8pF
2
0
CL = 2.1pF
-2
CL = 0.6pF
-4
-6
1M
CL = 5.3pF
4
2
0
CL = 2.1pF
-2
CL = 0.6pF
-4
-6
CL INCLUDES 0.6pF
BOARD CAPACITANCE
-8
CL INCLUDES 0.6pF
BOARD CAPACITANCE
-8
10M
100M
1G
-10
1M
FREQUENCY (Hz)
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL
INTO 500Ω LOAD
2
1
VOUT = 0.2VP-P
0.2
RL = 500Ω
RL = 150Ω
CL = 2.1pF
NORMALIZED GAIN (dB)
0.1
-1
RL = 250Ω
-2
RL = 150Ω
-3
-4
-5
0
-0.1
-0.3
-0.4
-0.5
-7
-0.6
10M
100M
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY vs RL
4
1G
RL = 500Ω
CL = 1.1pF
-0.2
-6
1M
1G
0.3
0
-8
10M
100M
FREQUENCY (Hz)
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs CL
INTO 150Ω LOAD
RL = 1kΩ
VOUT = 0.2VP-P
CL = 1.1pF
CL = 12.6pF
6
NORMALIZED GAIN (dB)
CL = 5.3pF
4
VOUT = 2VP-P
8
6
NORMALIZED GAIN (dB)
100M
FREQUENCY (Hz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL
INTO 500Ω LOAD
NORMALIZED GAIN (dB)
CL = 0.6pF
10M
FREQUENCY (Hz)
-10
CL = 12.6pF
6
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
6
VOUT = 0.2VP-P
8
CL = 8.8pF
-0.7
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 6. 0.1dB GAIN FLATNESS
FN6261.0
May 19, 2006
ISL59446
Typical Performance Curves
VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. (Continued)
10k
100
VSOURCE = 2VP-P
OUTPUT IMPEDANCE (Ω)
OUTPUT IMPEDANCE (Ω)
VSOURCE = 2VP-P
10
1
0.1
0.1M
1M
10M
100M
1k
100
10
0.1M
1G
1M
100M
1G
FIGURE 8. ZOUT vs FREQUENCY - HIZ
FIGURE 7. ZOUT vs FREQUENCY - ENABLED
1M
10
VSOURCE = 2VP-P
VSOURCE = 0.5VP-P
0
100k
PSRR (V-)
-10
10k
PSRR (dB)
INPUT IMPEDANCE (Ω)
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
1k
-20
-30
100
-40
PSRR (V-)
10
-50
1
0.3M
1M
10M
100M
FREQUENCY (Hz)
-60
0.3M
1G
1M
10M
100M
FREQUENCY (Hz)
1G
FIGURE 10. PSRR vs FREQUENCY
FIGURE 9. ZIN vs FREQUENCY
0
-10
60
VIN = 1VP-P
VOLTAGE NOISE (nV/√Hz)
-20
CROSSTALK RL = 500
-30 INPUT X TO OUTPUT Y RL = 150
(dB)
-40
OFF ISOLATION RL = 500
-50 INPUT X TO OUTPUT X RL = 150
-60
-70
-80
50
40
30
20
10
-90
-100
0.1M
1M
10M
100M
FREQUENCY (Hz)
FIGURE 11. CROSSTALK AND OFF ISOLATION
5
1G
0
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 12. INPUT NOISE vs FREQUENCY
FN6261.0
May 19, 2006
ISL59446
VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. (Continued)
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.01
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.10
-4
-3
-2
-1
1
0
VOUT DC (V)
2
3
4
NORMALIZED PHASE (°) NORMALIZED GAIN (dB)
NORMALIZED PHASE (°) NORMALIZED GAIN (dB)
Typical Performance Curves
0.01
0.008
0.006
0.004
0.002
0
-0.002
-0.004
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.10
-4
-3
-2
-1
0
1
FIGURE 13. DIFFERENTIAL GAIN AND PHASE;
VOUT = 0.2VP-P, FO = 3.58MHz, RL = 500Ω
0.1
RL = 150Ω
CL = 2.1pF
0.2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
4
VOUT = 0.2VP-P
VOUT = 0.2VP-P
0
0.1
0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE;
RL = 500Ω
FIGURE 16. SMALL SIGNAL TRANSIENT RESPONSE;
RL = 150Ω
VOUT = 2VP-P
VOUT = 2VP-P
RL = 500Ω
CL = 1.1pF
RL = 150Ω
CL = 2.1pF
2.0
OUTPUT VOLTAGE (V)
2.0
OUTPUT VOLTAGE (V)
3
FIGURE 14. DIFFERENTIAL GAIN AND PHASE;
VOUT = 0.2VP-P, FO = 3.58MHz, RL = 150Ω
RL = 500Ω
CL = 1.1pF
0.2
2
VOUT DC (V)
1.0
0
1.0
0
TIME (5ns/DIV)
FIGURE 17. LARGE SIGNAL TRANSIENT RESPONSE;
RL = 500Ω
6
TIME (5ns/DIV)
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE;
RL = 150Ω
FN6261.0
May 19, 2006
ISL59446
Typical Performance Curves
VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. (Continued)
50
40
50
INPUT RISE, FALL TIMES
VOUT = 2VP-P
<175ps
VOUT = 1.4VP-P
40
INPUT RISE, FALL TIMES
<175ps
VOUT = 2VP-P
OVERSHOOT (%)
OVERSHOOT (%)
VOUT = 1.4VP-P
30
20
VOUT = 1VP-P
30
20
VOUT = 1VP-P
10
10
VOUT = 0.2VP-P
VOUT = 0.2VP-P
0
2
4
CL (pF)
6
8
0
10
FIGURE 19. PULSE OVERSHOOT vs VOUT, CL; RL = 500Ω
1V/DIV
1V/DIV
6
8
10
VIN = 1V
0
VOUT A, B, C
1V/DIV
20mV/DIV
CL (pF)
S0, S1
50Ω
TERM.
0
0
0
VOUT A, B, C
20ns/DIV
20ns/DIV
FIGURE 21. CHANNEL TO CHANNEL SWITCHING GLITCH
VIN = 0V
ENABLE
50Ω
TERM.
FIGURE 22. CHANNEL TO CHANNEL TRANSIENT RESPONSE
VIN = 1V
VIN = 1V
ENABLE
VIN = 0V
1V/DIV
1V/DIV
50Ω
TERM.
0
0
VOUT A, B, C
2V/DIV
1V/DIV
4
FIGURE 20. PULSE OVERSHOOT vs VOUT, CL; RL = 150Ω
VIN = 0V
S0, S1
50Ω
TERM.
2
0
40ns/DIV
FIGURE 23. ENABLE SWITCHING GLITCH VIN = 0V
7
0
VOUT A, B, C
40ns/DIV
FIGURE 24. ENABLE TRANSIENT RESPONSE VIN = 1V
FN6261.0
May 19, 2006
ISL59446
Typical Performance Curves
VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. (Continued)
VIN = 0V
HIZ
50Ω
TERM.
1V/DIV
1V/DIV
0
2V/DIV
0
200mv/DIV
VIN = 1V
HIZ
50Ω
TERM.
0
VOUT A, B, C
VOUT A, B, C
0
20ns/DIV
20ns/DIV
FIGURE 25. HIZ SWITCHING GLITCH VIN = 0V
FIGURE 26. HIZ TRANSIENT RESPONSE VIN = 1V
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
3
2.5
POWER DISSIPATION (W)
POWER DISSIPATION (W)
2.857W
QFN32
θJA = 35°C/W
2
1.5
1
0.5
1
0.8
758mW
0.6
QFN32
θJA = 125°C/W
0.4
0.2
0
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
8
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6261.0
May 19, 2006
ISL59446
Pin Descriptions
ISL59446
(32 LD QFN)
PIN NAME
EQUIVALENT
CIRCUIT
1
IN1A
Circuit 1
2, 4, 8, 13, 15, 24,
28, 30
NIC
DESCRIPTION
Channel 1 input for output amplifier "A"
Not Internally Connected; it is recommended these pins be tied to ground to minimize
crosstalk.
3
IN1B
Circuit 1
Channel 1 input for output amplifier "B"
5
IN1C
Circuit 1
Channel 1 input for output amplifier "C"
6
GNDB
Circuit 4
Ground pin for output amplifier “B”
7
IN2A
Circuit 1
Channel 2 input for output amplifier "A"
9
IN2B
Circuit 1
Channel 2 input for output amplifier "B"
10
IN2C
Circuit 1
Channel 2 input for output amplifier "C"
11
GNDC
Circuit 4
Ground pin for output amplifier “C”
12
IN3A
Circuit 1
Channel 3 input for output amplifier "A"
14
IN3B
Circuit 1
Channel 3 input for output amplifier "B"
16
IN3C
Circuit 1
Channel 3 input for output amplifier "C"
17
S1
Circuit 2
Channel selection pin MSB (binary logic code)
18
S0
Circuit 2
Channel selection pin. LSB (binary logic code)
19
OUTC
Circuit 3
Output of amplifier “C”
20
OUTB
Circuit 3
Output of amplifier “B”
21
V-
Circuit 4
Negative power supply
22
OUTA
Circuit 3
Output of amplifier “A”
23
V+
Circuit 4
Positive power supply
25
ENABLE
Circuit 2
Device enable (active low). Internal pull-down resistor ensures device is active with no
connection to this pin. A logic High puts device into power-down mode and only the logic
circuitry is active. Logic states are preserved post power-down.
26
HIZ
Circuit 2
Output disable (active high). Internal pull-down resistor ensures the device will be active with
no connection to this pin. A logic high, puts the outputs in a high impedance state. Use this
state to control logic when more than one MUX-amp share the same video output line.
27
IN0C
Circuit 1
Channel 0 for output amplifier "C"
29
IN0B
Circuit 1
Channel 0 for output amplifier "B"
31
IN0A
Circuit 1
Channel 0 for output amplifier "A"
32
GNDA
Circuit 4
Ground pin for output amplifier “A”
V+
IN
LOGIC PIN
21k
+
1.2V
-
V+
V+
GND
OUT
33k
V-
CIRCUIT 1
GNDB
GNDC
CIRCUIT 2
CIRCUIT 3
THERMAL HEAT SINK PAD
V+
GNDA
V-
V-
CAPACITIVELY
COUPLED
ESD CLAMP
~1MΩ
VSUBSTRATE
VCIRCUIT 4
9
FN6261.0
May 19, 2006
ISL59446
Application Information
AC Test Circuits
ISL59446
VIN
General
LCRIT
VOUT
x2
*CL
1.1pF
50Ω
or
75Ω
RL
500Ω, or
150Ω
*CL Includes PCB trace capacitance
FIGURE 29A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59446
VIN
50Ω
or
75Ω
CL
RS
CS
RL
500Ω, or
75Ω
FIGURE 29B. INTER-STAGE APPLICATION CIRCUIT
ISL59446
LCRIT
x2
TEST
EQUIPMENT
RS
475Ω
*CL
1.1pF
50Ω
56.2Ω
50Ω
*CL Includes PCB trace capacitance
FIGURE 29C. 500Ω TEST CIRCUIT WITH 50Ω LOAD
ISL59446
VIN
LCRIT
x2
TEST
EQUIPMENT
RS
118Ω
*CL
2.1pF
50Ω,or
75Ω
86.6Ω
50Ω
*CL Includes PCB trace capacitance
FIGURE 29D. 150Ω TEST CIRCUIT WITH 50Ω LOAD
ISL59446
VIN
For the best isolation and crosstalk rejection, all GND pins
and NIC pins must connect to the GND plane.
AC Design Considerations
LCRIT
x2
VIN
Key features of the ISL59446 include a fixed gain of 2,
buffered high impedance analog inputs and excellent AC
performance at output loads down to 150Ω for video cabledriving. The current feedback output amplifiers are stable
operating into capacitive loads.
LCRIT
x2
TEST
EQUIPMENT
RS
50Ω or 75Ω
*CL
2.1pF
50Ω
or
75Ω
50Ω or 75Ω
*CL Includes PCB trace capacitance
FIGURE 29E. BACKLOADED TEST CIRCUIT FOR 75Ω VIDEO
CABLE APPLICATION
AC Test Circuits
Figures 29C and 29D illustrate the optimum output load for
testing AC performance at 500Ω and 150Ω loads.
Figure 29E illustrates the optimum output load for 50Ω and
75Ω cable-driving.
10
High speed current-feed amplifiers are sensitive to
capacitance at the inverting input and output terminals. The
ISL59446 has an internally set gain of 2, so the inverting
input is not accessible. Capacitance at the output terminal
increases gain peaking (Figure 1) and pulse overshoot
(Figures19, 20). The AC response of the ISL59446 is
optimized for a total output capacitance of up to 2.1pF over
the load range of 150Ω to 500Ω. When PCB trace
capacitance and component capacitance exceed 2pF, pulse
overshoot becomes strongly dependent on the input pulse
amplitude and slew rate. This effect is shown in Figures 19
and 20, which show approximate pulse overshoot as a
function of input slew rate and output capacitance. Fast
pulse rise and fall times (<150ns) at input amplitudes above
0.2V, cause the input pulse slew rate to exceed the
1600V/µs output slew rate of the ISL59446. At 125ps rise
time, pulse input amplitudes >0.2V cause slew rate limit
operation. Increasing levels of output capacitance reduce
stability resulting in increased overshoot, and settling time.
PC board trace length should be kept to a minimum in order
to minimize output capacitance and prevent the need for
controlled impedance lines. At 500MHz trace lengths
approaching 1” begin exhibiting transmission line behavior
and may cause excessive ringing if controlled impedance
traces are not used. Figure 29A shows the optimum
inter-stage circuit when the total output trace length is less
than the critical length of the highest signal frequency.
For applications where pulse response is critical and where
inter-stage distances exceed LCRIT, the circuit shown in
Figure 29B is recommended. Resistor RS constrains the
capacitance seen by the amplifier output to the trace
capacitance from the output pin to the resistor. Therefore,
RS should be placed as close to the ISL59446 output pin as
possible. For inter-stage distances much greater than LCRIT,
the back-loaded circuit shown in Figure 29E should be used
with controlled impedance PCB lines, with RS and RL equal
to the controlled impedance.
For applications where inter-stage distances are long, but
pulse response is not critical, capacitor CS can be added to
low values of RS to form a low-pass filter to dampen pulse
overshoot. This approach avoids the need for the large gain
correction required by the -6dB attenuation of the
FN6261.0
May 19, 2006
ISL59446
HIZ State
back-loaded controlled impedance interconnect. Load
resistor RL is still required but can be 500Ω or greater,
resulting in a much smaller attenuation factor.
An internal pull-down resistor ensures the device will be
active with no connection to the HIZ pin. The HIZ state is
established within approximately 20ns (Figure 26) by placing
a logic high (>2V) on the HIZ pin. If the HIZ state is selected,
the output impedance is ~1000Ω (Figure 8). The supply
current during this state is same as the active state.
Control Signals
S0, S1, ENABLE, HIZ - These are binary coded, TTL/CMOS
compatible control inputs. The S0, S1 pins select the inputs.
All three amplifiers are switched simultaneously from their
respective inputs. The ENABLE pin is used to disable the part
to save power, and the HIZ pin to set the output stage in a
high impedance state. For control signal rise and fall times
less than 10ns the use of termination resistors close to the
part may be necessary to prevent reflections and to minimize
transients coupled to the output.
ENABLE and Power-Down States
The enable pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
ENABLE pin. The power-down state is established within
approximately 200ns (Figure 24), if a logic high (>2V) is
placed on the ENABLE pin. In the power-down state, the
output has no leakage but has a large variable capacitance
(on the order of 15pF), and is capable of being back-driven.
Under this condition, large incoming slew rates can cause
fault currents of tens of mA. Therefore, the parallel connection
of multiple outputs is not recommended unless the application
can tolerate the limited power-down output impedance.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins
to the V+ and V- supplies. In addition, a dV/dT- triggered
clamp is connected between the V+ and V- pins, as shown in
the Equivalent Circuits 1 through 4 section of the Pin
Description table. The dV/dT triggered clamp imposes a
maximum supply turn-on slew rate of 1V/µs. Damaging
currents can flow for power supply rates-of-rise in excess of
1V/µs, such as during hot plugging. Under these conditions,
additional methods should be employed to ensure the rate of
rise is not exceeded.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 30) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners, use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless strip line
are used.
V+ SUPPLY
SCHOTTKY
PROTECTION
LOGIC
V+
LOGIC
CONTROL
S0
POWER
GND
GND
EXTERNAL
CIRCUITS
V+
V-
V+
V+
SIGNAL
IN0
OUT
V+
V-
DECOUPLING
CAPS
V-
IN1
V-
V-
V- SUPPLY
FIGURE 30. SCHOTTKY PROTECTION CIRCUIT
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FN6261.0
May 19, 2006
ISL59446
• Match channel-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC decoupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply decoupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices
as possible - avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
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The QFN Package Requires Additional PCB Layout
Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply
through the high resistance IC substrate. Its primary function
is to provide heat sinking for the IC. However, because of the
connection to the V- supply through the substrate, the
thermal pad must be tied to the V- supply to prevent
unwanted current flow to the thermal pad. Do not tie this pin
to GND as this could result in large back biased currents
flowing between GND and V-. The ISL59446 the package
with pad dimensions of D2 = 2.48mm and E2 = 3.4mm.
Maximum AC performance is achieved if the thermal pad is
attached to a dedicated decoupled layer in a multi-layered
PC board. In cases where a dedicated layer is not possible,
AC performance may be reduced at upper frequencies.
• The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
eliminates the need for individual thermal pad area. When
a dedicated layer is not possible a 1” x 1” pad area is
sufficient for the ISL59446 that is dissipating 0.5W in
+50°C ambient. Pad area requirements should be
evaluated on a case by case basis.
FN6261.0
May 19, 2006
ISL59446
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x6A (One of 10 Packages in MDP0046)
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
0.00
0.02
0.05
-
D
PIN #1
I.D. MARK
E
5.00 BSC
-
D2
2.48 REF
-
E
6.00 BSC
-
E2
(N/2)
2X
0.075 C
2X
0.075 C
0.45
b
0.20
-
0.50
0.55
-
0.22
0.24
-
c
0.20 REF
b
L
-
e
0.50 BSC
-
N
32 REF
4
ND
7 REF
6
NE
9 REF
5
0.10 M C A B
Rev 0 9/05
NOTES:
(N-2)
(N-1)
N
N LEADS
TOP VIEW
3.40 REF
L
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
PIN #1 I.D.
2. Tiebar view shown is a non-functional feature.
3
1
2
3
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
(E2)
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
NE 5
(N/2)
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
7
(D2)
BOTTOM VIEW
0.10 C
e
C
(c)
SEATING
PLANE
0.08 C
N LEADS
& EXPOSED PAD
C
2
A
(L)
SEE DETAIL "X"
A1
SIDE VIEW
N LEADS
DETAIL X
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FN6261.0
May 19, 2006