No. AN9411 Application Note June 1994 Using the HI1171 Evaluation Kit Author: Stephen G. LaJeunesse Introduction The HI1171 is an 8-bit 40MHz Digital to Analog Converter. This device is TTL/CMOS logic compatible. This current out DAC is ideally suited for Video Signal Reconstruction and low cost DDS (Direct Digital Synthesis) applications due to the inherent low noise design and low glitch area. Description Architecture The HI1171 DAC is a binaurally weighted current cell architecture. The Functional Block Diagram shows the functional architecture of the device. The internal latches have a blanking function that clears the data in the 8-bit latch and holds the output current at zero. An external reference must be used. The HI1171 is internally referenced to the +5V supply to reduce internal noise. As such, an external potentiometer can be used to derive a reference voltage. The IREF pin is used to set the scalable output current. In setting the output current the IREF pin should have a resistor connected to it that is 16 times greater than the output resistor. RREF = 16 x ROUT As the values of both ROUT and RREF increase, power consumption is decreased, but glitch energy and output settling time is increased. Functional Block Diagram (LSB) D0 D1 D2 D3 DECODER 8-BIT LATCH D4 6 MSBs CURRENT CELLS D5 VG (MSB) D7 CURRENT CELLS (FOR FULL SCALE) BLNK BIAS VOLTAGE GENERATOR VB AVDD Copyright AVSS IOUT1 DECODER D6 CLK IOUT2 2 LSBs CURRENT CELLS CLOCK GENERATOR DVDD DVSS © Intersil Corporation 1994 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 154 + VREF IREF Application Note 9411 Measuring Glitch Differential Linearity and Missing Codes Glitch is caused by the time skew between bits of the incoming digital data. Typically the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time. Unequal delay paths through the device can also cause one current source to change before another. To minimize this, the Intersil HI1171 employs an internal register, just prior to the current sources, that is updated on the clock edge. In traditional DACs, the worst case glitch usually happens at the major transition i.e. 0111 1111 to 1000 0000. For a D/A Converter the differential linearity is the step size difference through-out the entire code range. For the HI1171 the step to step maximum difference is ±0.25 LSBs. For any given D/A converter, to guarantee no missing codes the converter must be monotonic. Since the glitch is a transient event, this leads designers to believe that a simple low pass filter can be used to eliminate or reduce the size of the glitch. In effect, low pass filtering a glitch tends to “smear” the event and does little to remove the energy of the transient. See Figure 1. The definition of Monotonicity is that as the input code is increased the output should increase. When an input code is increased and the output of the DAC does not increase or reverses direction then this converter is assumed to be missing codes. As shown in Figure 3 as the input code increases the output voltage should increase. When an error of 1.0 LSB is incurred that bit can be assumed to be a missing code since the output did not increase but rather remained the same. INL ERROR (LSBs) GLITCH AREA = 1/2 (H X W) V 0.5 0.4 0.3 0.2 0.1 OFFSET -0.1 -0.2 -0.3 -0.4 -0.5 HEIGHT (H) WIDTH (W) t(ps) 1 2 3 4 5 6 7 8 +F.S. FIGURE 1. GLITCH AREA FIGURE 2. INL TYPICAL PERFORMANCE CURVE Integral Linearity The HI1171 has a FSR range of 15mA. When driving an equivalent 75Ω load the full scale voltage swing is 0 to +1.125V. Most video and communication applications use a 1VP-P voltage swing which yields 13mA full scale current sink capability. With a 1VP-P voltage swing on the HI1171 output, an LSB is LSB = Full Scale Range/2N -1 INPUT CODE 11 -1.0 LSB ERROR 10 (MISSING CODE) where N is the number of bits and the Full Scale Range is 1V. The LSB size for this application is 3.9mV. To determine the Integral Linearity of the HI1171 the bit weights of each major transition is taken. Since the End Point method is used to calculate the overall INL the first measurements taken are Offset and then the Full Scale Voltage. Then the ideal LSB size for this given End Point line is used to calculate the INL error. The worst case linearity of the HI1171 is specified to be less than +1.3 and -0.5 LSBs. For the overall transfer function the typical INL performance is shown in Figure 2. 155 01 -0.5 LSB ERROR OUTPUT VOLTAGE 00 FIGURE 3. DNL EXAMPLE Application Note 94111 The Evaluation Board The HI1171 Evaluation board is a 1/2 size daughter board designed to interface to the HSP-EVAL board. These boards when used together create a flexible and powerful DDS system. The HSP45116 board is used to generate the high speed digital SINE wave patterns for the D/A module. The HI1171 board reconstructs the incoming digital data to an analog representation that can be analyzed on a spectrum analyzer or oscilloscope. 0 FUNDAMENTAL (PURE TONE) AMPLITUDE (dB) -50 Plugging In NOISE FLOOR After opening the HSP45116 board and the HI1171 board power should be applied to the banana jacks. A +5V supply will be needed. To reduce noise the power supply leads should be twisted pairs. The interface cable should be connected to an IBM PC or compatible parallel port. Power should be applied to the board and then the software can be started. the software can be run directly from floppy disk. To run the software place the floppy disk into drive A: and type: A: NCOMCTRL -85 f 1MHz fN FIGURE 4. FREQUENCY PLOT OF 1MHz TONE The fundamental of a pure 1MHz tone should appear as an impulse in the frequency domain at 1MHz. In a sampled system noise terms are produced near the sampling frequencies called aliases. These aliases are related to the fundamental in that they are located fN around the sampling frequency as shown in Figure 5. the HSP45116 Control Panel will be loaded. To exercise the board the following parameters should be set: FUNDAMENTAL 0 BINFMT# = 0 AMPLITUDE (dB) and then set the Center Frequency to: CENTER FREQUENCY = 01000000H where the center frequency is in hex. At this point the output of the HI1171 DAC module should be converting a SINE wave at 48kHz. Connect the output of the HI1171 module to an oscilloscope. Adjust the potentiometer until the output waveform has an amplitude of 1VP-P . Adjusting the potentiometer Clockwise (CW) will reduce the amplitude and Counter-Clockwise (CCW) will increase the amplitude. The HI1171 module has a jumper plug for selecting the blanking feature of the HI1171. When J2 is installed, the DAC will not blank but will convert the incoming data. When J2 is not installed, the DAC will be blanked. The HI1171 is very sensitive to clock noise. Some TTL/ CMOS oscillators have tremendous amounts of ringing and overshoot. To reduce this use a clean clock source whenever possible. Spurious Free Dynamic Range The Spurious Free Dynamic Range of the HI1171 DAC is the most important specification for communication applications. This specification shows how Integral Linearity, Glitch, and Switching noise affect the spectral purity of the output signal. Several important things must be noted first. SAMPLING FUNCTION (SINE X/X) -50 ALIAS (fs - 1MHz) -85 f 1MHz fN 4MHz fS FIGURE 5. SAMPLING ALIAS PRODUCTS So for a 1MHz fundamental and a 5MHz sampling rate an alias term is created at 4MHz. A SYNC2 function shaping is also induced by sampling a signal. Aliases continue up through the frequency spectrum repeating around the sampling frequency and its harmonics (i.e. 2fS, 3fS, 4fS...). A reconstructed Sine wave out of the HI1171 is not ideal and as such has harmonics of the fundamental. The difference between the magnitude of the fundamental and the highest noise spur whether it is harmonically related to the fundamental or not, is the definition of Spurious Free Dynamic Range. Figures 6, 7, and 8 are sample Spectrum Analyzer plots taken, of the HI1171 at various frequencies. Included are the oscilloscope plots. When a quantized signal is reconstructed, certain artifacts are created. Let’s take the example of trying to recreate a 1MHz Sine wave with a 1VP-P output. In the frequency domain the fundamental should appear at 1MHz as shown in Figure 4. 156 Application Note 9411 f N = 5MHz UNFILTERED ATTEN 40dB RL 0dB 10dB/ CODE WORD = 2000 0000HEX f S = 40MHz ∆MKR -42.50dB 5.0MHz ∆MKR 5.0MHz -42.50dBm START 0Hz RBW 3.0kHz STOP 20.0MHz SWP 5.60s VBW 10kHz FIGURE 6A. SFDR TO NYQUIST UNFILTERED FIGURE 6B. 5MHz UNFILTERED OSCILLOSCOPE PLOT FIGURE 6. fN = 5MHz FILTERED ATTEN 40dBm RL 0dB 10dB/ CODE WORD = 2000 0000HEX fS = 40MHz ∆MKR -62.84dB 600kHz ∆MKR 600kHz -62.84dB START 0Hz RBW 1.0kHz STOP 20.0MHz SWP 50.0s VBW 3.0kHz FIGURE 7A. SFDR TO NYQUIST BANDPASS FILTERED FIGURE 7B. 5MHz FILTERED OSCILLOSCOPE PLOT FIGURE 7. fN = 1MHz UNFILTERED ATTEN 40dB RL 0dBm 10dB/ CODE WORD = 0666 6666HEX fS = 40MHz ∆MKR -73.67dB -180.0kHz ∆MKR -180.0kHz -73.67dB CENTER 1.0000MHz RBW 100Hz VBW 1.0kHz SPAN500.0kHz SWP 40.0s FIGURE 8A. LIMITED SPAN FIGURE 8B. 1MHz UNFILTERED OSCILLOSCOPE PLOT FIGURE 8. 157 Application Note 9411 Schematic Materials List PIN NUMBER DESCRIPTION PART NUMBER VENDOR QUANTITY REFERENCE (DES) 1 96 Pin Female DIN A1262-ND Digi-Key 1 P1 2 2 Post Jumper Thru-Hole 518-1070 Allied 1 J2 3 Banana Jacks J147-ND Digi-Key 2 BJ1, 2 5 Female BNC Connector 713-7160 Allied 1 BNC1 6 50Ω Res. Thru-Hole 297-4157 Allied 1 R8 7 1.2kΩ Res. Thru-Hole 297-5366 Allied 1 R4 8 39Ω Res. Thru-Hole 297-5140 Allied 1 R2 9 100Ω Res. Thru-Hole 297-4202 Allied 1 R3 10 0Ω Res. Thru-Hole - - 2 R6, 7 11 22kΩ Res. Thru-Hole 297-4586 Allied 1 R1 12 1kΩ Pot - - 1 R5 12 10µH Ind. Thru-Hole 274300111 Dexter 2 L1, 2 13 0.1µF Cap CER Thru-Hole 852-1170 Allied 2 C2, 4 14 0.1µF Cap CER Thru-Hole 852-1157 Allied 5 C1, 3, 5, 6, 7 15 10µF TANT Cap Thru-Hole 926-1985 Allied 2 C8, 9 16 HI1171 D/A DIP Package HI1171JIP Intersil 1 U1 17 HI1171 Eval Board HI1171.EVAL - 1 - 158 Schematic Diagram J1 VCC P1B P1C 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DB0 DB3 DB5 DB7 CON32 CON32 DB1 DB2 DB4 DB6 CLK 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 1 3 2 4 U3B VCC U3A 74ACT00 J3 1 2 3 6 5 74ACT00 9 U3C INVERTED CLOCK 8 10 CON3 74ACT00 12 U3D 11 13 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AVDD R7 0 74ACT00 R6 0 U1 24 VCC VCC R1 22K CON50A 23 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 8 7 6 5 4 3 2 1 9 J2 1 2 DVDD AVDD AVDD AVDD DVDD D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB OUT) BLANK VG VREF IOUT IOUT/ AVDD 22 19 18 C5 0.01µF 17 16 ADJUST TO 1.0V R2 20 C7 CON32 BNC1 BNC 39 21 C6 0.01 12 CLK CON2 R5 1K Application Note 9411 159 P1A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 11 VB IREF 15 R4 R3 100 1.2K 0.01µF 10 DVSS 13 DV SS AVSS 14 HI1171 AVDD BJ1 DIGITAL SUPPLY BJACK HIGH QUALITY REFERENCE CIRCUIT VCC L1 4.7µF DGND 10µH BJACK + C8 4.7µF TO UI PIN 16 L2 R7 3.6K R6 5K 10µH + C9 BJ2 AVDD R5 20K AVDD VCC U2 LT1009CZ C2 0.1µF C1 0.01µF C4 0.1µF C3 0.01µF Application Note 9411 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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