X9118
Dual Supply/Low Power/1024-Tap/2-Wire Bus
Data Sheet
April 9, 2014
Single Digitally-Controlled (XDCP™)
Potentiometer
FN8161.5
Features
• 1024 resistor taps – 10-bit resolution
The X9118 is a single digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 2-wire serial interface for write, read and transfer
operations of the potentiometer
• Wiper resistance, 40Ω typical @ 5V
• Four non-volatile data registers for each potentiometer
• Non-volatile storage of multiple wiper positions
• Power on recall: Loads saved wiper position on power-up
• Standby current < 15µA Max
• System VCC: 2.7V to 5.5V operation
• Analog V+/V-: -5V to +5V
• 100kΩ end-to-end resistance
• Endurance: 100,000 data changes per bit per register
• 100 years data retention
• 14 Ld TSSOP
• Low power CMOS
• Pb-free (RoHS compliant)
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
VCC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(kΩ)
TEMP
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
X9118TV14IZ
X9118 TVZI
5 ±10%
100
-40 to +85
14 Ld TSSOP
M14.173
X9118TV14IZ-2.7
X9118 TVZG
2.7 to 5.5
100
-40 to +85
14 Ld TSSOP
M14.173
X9118TV14Z
X9118 TVZ
5 ±10%
100
0 to +70
14 Ld TSSOP
M14.173
X9118TV14Z-2.7
X9118 TVZF
2.7 to 5.5
100
0 to +70
14 Ld TSSOP
M14.173
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
2. For Moisture Sensitivity Level (MSL), please see product information page for X9118. For more information on MSL, please see tech brief TB363.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2008, 2009, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9118
Functional Diagram
VCC
2-WIRE
BUS
INTERFACE
ADDRESS
DATA
STATUS
BUS
INTERFACE
AND
CONTROL
RH
WRITE
READ
TRANSFER
POWER ON RECALL
CONTROL
VSS
100kΩ
1024-TAPS
POT
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
(DR0-DR3)
NC
NC
V+
WIPER
RL
RW
V-
Detailed Functional Diagram
VCC
V+
POWER ON
RECALL
DR0
SCL
INTERFACE
AND
CONTROL
CIRCUITRY
SDA
A1
A0
DR1
DATA
DR2
DR3
RH
WIPER
COUNTER
REGISTER
(WCR)
100KΩ
1024-TAPS
RL
CONTROL
RW
WP
VSS
V-
Circuit Level Applications
System Level Applications
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable DC reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Control the gain in audio and home entertainment systems
• Trim the resistance in Wheatstone bridge circuits
• Provide the variable DC bias for tuners in RF wireless
systems
• Control the gain, characteristic frequency and Q-factor in
filter circuits
• Set the operating points in temperature control systems
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent systems
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
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FN8161.5
April 9, 2014
X9118
DEVICE ADDRESS (A1–A0)
Pinout
X9118
(14 LD TSSOP)
TOP VIEW
V+
NC
1
14
VCC
2
13
RL
A0
3
12
RH
SCL
4
11
RW
NC
A1
WP
5
10
SDA
6
VSS
7
9
8
V-
The address inputs are used to set the least significant 2 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input, in
order to initiate communication with the X9118. A maximum
of 4 XDCP devices may occupy the 2-wire serial bus.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to the
Data Registers.
Potentiometer Pins
RH, RL
Pin Assignments
FUNCTION
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
PIN #
PIN NAME
1
V+
Analog Supply Voltage
RW
2, 10
NC
No Connect
3
A0
Device Address for 2-wire bus
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
4
SCL
Serial Clock for 2-wire bus
Bias Supply Pins
5
WP
Hardware Write Protect
6
SDA
Serial Data Input/Output for 2-wire bus
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
7
VSS
System Ground
8
V-
Analog Supply Voltage
9
A1
Device Address for 2-wire bus
11
RW
Wiper terminal of the Potentiometer
12
RH
High terminal of the Potentiometer
13
RL
Low terminal of the Potentiometer
14
VCC
System Supply Voltage
The VCC pin is the system or digital supply voltage. The VSS
pin is the system ground.
ANALOG SUPPLY VOLTAGES (V+ AND V-)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper switches
while the V- supply is used to bias switches and the internal
P+ substrate of the integrated circuit. Both of these supplies
set the voltage limits of the potentiometer.
Other Pins
Pin Descriptions
NO CONNECT
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bi-directional serial data input/output pin for a
2-wire slave device and is used to transfer data into and out
of the device. It receives device address, opcode, wiper
register address and data sent from a 2-wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.
It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor. The user
must account for the capacitance on the bus line and the
desired rise and fall times when selecting a pull-up resistor.
2kΩ to 2.5kΩ are typical values when using the maximum
clock frequency.
No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.
Principles of Operation
The X9118 is an integrated microcircuit incorporating a
resistor array and its registers and counters and the serial
interface logic providing direct communication between the
host and the digitally controlled potentiometer. This section
provides a detailed description of the following:
• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description
SERIAL CLOCK (SCL)
This input is used by 2-wire master to supply 2-wire serial
clock to the X9118.
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X9118
SERIAL DATA PATH
RH
SERIAL
BUS
INPUT
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
10
REGISTER 2
(DR2)
10
REGISTER 3
(DR3)
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then RW = RL
If WCR = 3FF[HEX] then RW = RH
RL
RW
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Resistor Array Description
CLOCK AND DATA CONVENTIONS
The X9118 is comprised of a resistor array. The array
contains 1023, in effect, discrete resistive segments that are
connected in series (see Figure 1). The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL inputs).
Data states on the SDA line can change only during SCL
LOW periods. The SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions,
see Figure 3.
At both ends of each array and between each resistor
segment is a CMOS switch (transmission gate) connected to
the wiper (RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the wiper counter register (WCR). The 10 bits
of the WCR (WCR[9:0]) are decoded to select, and enable,
one of 1024 switches.
All commands to the X9118 are preceded by the start
condition, which is a HIGH-to-LOW transition of SDA while
SCL is HIGH. The X9118 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met, see Figure 3.
The WCR may be written directly. The Data Registers and
the WCR can be read and written by the host system.
START CONDITION
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is
HIGH, see Figure 3.
Serial Interface Description
ACKNOWLEDGE
SERIAL INTERFACE – 2-WIRE
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8 bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9118 supports a bi-directional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9118 will be
considered a slave device in all applications.
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The X9118 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte, the X9118 will
respond with a final acknowledge, see Figure 2.
FN8161.5
April 9, 2014
X9118
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACKNOWLEDGE POLLING
INSTRUCTION AND REGISTER DESCRIPTION
The disabling of the inputs during the internal nonvolatile write
operation, can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9118
initiates the internal write cycle. The ACK polling, Flow 1, can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the X9118 is
still busy with the write operation no ACK will be returned. If the
X9118 has completed the write operation an ACK will be
returned and the master can then proceed with the next
operation.
Device Addressing: Identification Byte (ID and A)
Flow 1. ACK Polling Sequence
NONVOLATILE WRITE
COMMAND COMPLETED
ENTERACK POLLING
ISSUE
START
Following a start condition, the master must output the
address of the slave it is accessing. The most significant
4 bits of the slave address are the device type identifier. The
ID[3:0] bits is the device ID for the X9118; this is fixed as
0101[B] (refer to Table 1 on page 6).
The A[1:0] bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the
A1-A0 input pins. The slave address is externally specified
by the user. The X9118 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9118 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address sent by
the master executes the instruction. The A1 to A0 inputs can
be actively driven by CMOS input signals or tied to VCC or
VSS. The R/W bit is the LSB and used to set the device for
read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
ISSUE SLAVE
ADDRESS
ACK
RETURNED?
ISSUE STOP
NO
Table 3 provides a complete summary of the instruction set
opcodes.
YES
FURTHER
OPERATION?
The next byte sent to the X9118 contains the instruction and
register pointer information. The three most significant bits
are used to provide the instruction opcode (I[2:0]). The RB
and RA bits point to one of the four registers. The format is
shown in Table 2.
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
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FN8161.5
April 9, 2014
X9118
TABLE 1. IDENTIFICATION BYTE FORMAT
DEVICE TYPE
IDENTIFIES
INTERNAL SLAVE
ADDRESS
SET TO 0
FOR PROPER
OPERATION
READ OR
WRITE BIT
ID3
ID2
ID1
ID0
0
A1
A0
R/W
0
1
0
1
0
A1
A0
R/W
(MSB)
(LSB)
TABLE 2. INSTRUCTION BYTE FORMAT
INSTRUCTION
OPCODE
I2
REGISTER
SELECTION
SET TO 0
FOR PROPER
OPERATION
I1
I0
0
RB
SET TO 0 FOR
PROPER OPERATION
RA
0
(MSB)
0
(LSB)
REGISTER SELECTED
RB
RA
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
TABLE 3. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
R/W
I2
I1
I0
0
RB
RA
0
0
Read Wiper Counter Register
1
1
0
0
0
0
0
0
0
Read the contents of the Wiper Counter Register
Write Wiper Counter Register
0
1
0
1
0
0
0
0
0
Write new value to the Wiper Counter Register
Read Data Register
1
1
0
1
0
1/0
1/0
0
0
Read the contents of the Data Register pointed to
RB-RA.
Write Data Register
0
1
1
0
0
1/0
1/0
0
0
Write new value to the Data Register pointed to
RB-RA.
XFR Data Register to Wiper
Counter Register
1
1
1
0
0
1/0
1/0
0
0
Transfer the contents of the Data Register pointed to
by RB-RA to the Wiper Counter Register
XFR Wiper Counter Register
to Data Register
0
1
1
1
0
1/0
1/0
0
0
Transfer the contents of the Wiper Counter Register
to the Data Register pointed to by RB-RA.
OPERATION
NOTE:
3. 1/∅ = data is one or zero.
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X9118
Four of the six instructions are four bytes in length. These
instructions are:
Instruction and Register Description
Device Addressing
• Read Wiper Counter Register – Read the current wiper
position of the potentiometer.
WIPER COUNTER REGISTER (WCR)
The X9118 contains a Wiper Counter Register (see Table 4)
for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways:
1. It may be written directly by the host via the write Wiper
Counter Register instruction (serial load).
2. It may be written indirectly by transferring the contents of
one of four associated Data Registers via the XFR Data
register.
3. It is loaded with the contents of its Data Register zero
(R0) upon power-up.
The Wiper Counter Register is a volatile register; that is,
contents are lost when the X9118 is powered down. Although
the register is automatically loaded with the value in DR0
upon power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to
ensure proper loadings of the DR0 value into the WCR.
DATA REGISTERS (DR)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can be transferred between any of the four data
registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bit 9 to Bit 0 are used to store one of the 1024 wiper position
(0 ~1023).
• Write Wiper Counter Register – Change current wiper
position of the potentiometer.
• Read Data Register – Read the contents of the selected
Data Register.
• Write Data Register – Write a new value to the selected
Data Register.
The basic sequence of the four byte instructions is illustrated
in Figure 3. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer
from a data register to a WCR is essentially a write to a static
RAM, with the static RAM controlling the wiper position. The
response of the wiper to this action will be delayed by tWRL. A
transfer from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a minimum
of tWR to complete. The transfer can occur between the
potentiometer and one of its associated registers.
Two instructions (see Figure 4) require a two-byte sequence
to complete. These instructions transfer data between the
host and the X9118; either between the host and one of the
Data Registers or directly between the host and the Wiper
Counter Register. These instructions are:
• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the Wiper Counter Register.
• XFR Wiper Counter Register to Data Register –This
transfers the contents of the specified Wiper Counter
Register to the specified Data Register.
Refer to “Instruction Format” on page 8 for more details.
Other
POWER-UP AND POWER-DOWN REQUIREMENTS
At all times, the V+ voltage must be greater than or equal to
the voltage at RH or RL, and the voltage at RH or RL must be
greater than or equal to the voltage at V-. During power-up
and power-down, VCC, V+, and V- must reach their final
values within 1ms of each other.
TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9 TO WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9 TO BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
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FN8161.5
April 9, 2014
X9118
SCL
SDA
0
1
0
1
S ID3 ID2 ID1 ID0
T
A
DEVICE ID
R
T
0
A1
A0 R/W
INTERNAL
ADDRESS
0
0
A I2
I1 I0 0
C
K INSTRUCTION
OPCODE
RB RA 0
0
A
C
K
REGISTER
ADDRESS
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
0
1
0
1
0
0
0 X
X
0
0
X
S ID3 ID2 ID1 ID0 0 A1 A0 R/W A I2 I1 I0 0 RB RA 0
T
C
A DEVICE ID
INTERNAL K INSTRUCTION REGISTER
R
OPCODE
ADDRESS
ADDRESS
T
X X
X
X X
A
C
K
W
C
R
9
W A W W
C C C C
R K R R
8
7 6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W A
C C
R K
0
S
T
O
P
WIPER OR DATA
POSITION
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
Instruction Format
Read Wiper Counter Register (WCR)
DEVICE
ADDRESSES
R/W = 1
DEVICE TYPE
S IDENTIFIER
T
A
R 0 1 0 1
T
0 A1 A0
INSTRUCTION
OPCODE
S
A
C
K
1
0
0
REGISTER
ADDRESSES
0
0
0
0
0
WIPER POSITION
(SENT BY SLAVE ON SDA)
S
A
W W
C
C C
K X X X X X X R R
9
WIPER POSITION
(SENT BY SLAVE ON SDA)
M
A W W W
C C C C
K R R R
7 6 5
8
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
M S
W A T
C C O
R K P
0
Write Wiper Counter Register (WCR)
INSTRUCTION
OPCODE
R/W = 0
DEVICE
S DEVICE TYPE
IDENTIFIER
ADDRESSES
T
A
R
0 1 0 1 0 A1 A0
T
S
A
C
K 1
0
1
REGISTER
ADDRESSES
0
0
0
0
WIPER
POSITION
(SENT BY MASTER ON SDA)
WIPER POSITION
(SENT BY MASTER ON SDA)
0
S
A
C
K X
X
X X
X
S
A
W W
W W
C
C C
C C
K
X
R R
R R
7 6
9 8
S
A
W W W W W W
C
C C C C C C
K
R R R R R R
5 4 3 2 1 0
S
T
O
P
Read Data Register (DR)
DEVICE
ADDRESSES
0 A1 A0
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R/W = 1
DEVICE TYPE
S IDENTIFIER
T
A
R 0 1 0 1
T
8
S
A
C
K
INSTRUCTION
OPCODE
1
0
1
0
REGISTER
ADDRESSES
RB
RA
0
WIPER POSITION
(SENT BY SLAVE ON SDA)
S
A
W
C
C
0 K X X X X X X
R
9
WIPER POSITION OR DATA
(SENT BY SLAVE ON SDA)
M
W A W W W
C C C C C
K
R R R
R
7 6 5
8
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
M S
W A T
C C O
R K P
0
FN8161.5
April 9, 2014
X9118
DEVICE
ADDRESSES
0 A1 A0
INSTRUCTION
OPCODE
R/W = 0
DEVICE TYPE
S IDENTIFIER
T
A
R 0 1 0 1
T
S
A
C
K 1
1 0
0
REGISTER
ADDRESSES
WIPER POSITION OR DATA
(SENT BY MASTER ON SDA)
S
A
W
C
C
RB RA 0 0 K X X X X X X
R
9
WIPER POSITION OR DATA
(SENT BY MASTER ON SDA)
S
W A W W W
C C C C C
R K R R R
7 6 5
8
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
S S
W A T
C C O
R K P
0
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
R/W = 0
DEVICE
S DEVICE TYPE
IDENTIFIER
ADDRESSES
T
A
R 0 1 0 1 0 A1 A0
T
S
A
C
K
INSTRUCTION
OPCODE
1
1
1
0
REGISTER
ADDRESSES
RB RA 0
S
A
C
0 K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
R/W = 1
DEVICE
S DEVICE TYPE
IDENTIFIER
ADDRESSES
T
A
R 0 1 0 1 0 A1 A0
T
S
A
C
K
INSTRUCTION
OPCODE
1
1
0
0
REGISTER
ADDRESSES
RB RA 0
S
A
C
0 K
S
T
O
P
NOTES:
1. “A1 ~ A0”: stands for the device addresses sent by the master.
2. WCRx refers to wiper position data in the Wiper Counter Register.
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X9118
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Voltage on SCL, SDA, or Any Address Input
with Respect to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
Voltage on V+ (referenced to VSS) (Note 8) . . . . . . . . . . . . . . . .10V
Voltage on V- (referenced to VSS) (Note 8) . . . . . . . . . . . . . . . . -10V
(V+) – (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Any Voltage on RH/RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+
Any Voltage on RL/RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Supply Voltage (VCC) Limits (Note 8)
X9118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
X9118-2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Thermal Resistance (Typical, Note 3, 4) . θJA (°C/W) θJC (°C/W)
14 Ld TSSOP . . . . . . . . . . . . . . . . . . . .
92
25
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Power Rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW
Wiper current (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For θJC, the “case temp” location is taken at the package top center.
Analog Specifications
SYMBOL
RTOTAL
TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range , -40°C to +85°C.
PARAMETER
TEST CONDITIONS
MIN
(Note 10)
End to End Resistance
TYP
MAX
(Note 10)
UNITS
100
End to End Resistance Tolerance
kΩ
±20
%
RW
Wiper Resistance
IW = (VRH - VRL)/RTOTAL, VCC = 3V, VRL = -3V
150
500
Ω
RW
Wiper Resistance
IW = (VRH - VRL)/RTOTAL, VCC = 5V, VRL = 0V
40
100
Ω
Vv+
Voltage on V+ Pin
X9118 (Note 8)
+4.5
+5.5
V
X9118-2.7 (Note 8)
+2.7
+5.5
V
X9118
-5.5
-4.5
V
X9118-2.7
-5.5
-2.7
V
Voltage on any RH or RL Pin
VSS = 0V
V-
Noise
Ref: 1kHz
VvVTERM
Voltage on V- Pin
Resolution
V
dBV
0.1
%
Absolute Linearity (Note 5)
Rw(n)(actual) – Rw(n)(expected), where n = 1 to
1023
±1.5
MI
(Note 7)
Relative Linearity (Note 6)
Rw(m + 1) – [Rw(m) + MI], where m = 1 to 1023
±1.5
MI
(Note 7)
Temperature Coefficient of RTOTAL
CH/CL/CW
V+
-120
Ratiometric Temperature
Coefficient
Wiper at middle point
Potentiometer Capacitances
See Macro model
±300
ppm/°C
±20
ppm/°C
10/10
/25
pF
NOTES:
5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
6. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
7. MI = RTOT/1023 or (RH – RL)/1023, single pot.
8. VCC, V+, V- must reach their final values within 1ms of each other.
9. n = 0, 1, 2, …,1023; m = 0, 1, 2, …, 1022.
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FN8161.5
April 9, 2014
X9118
DC Operating Specifications
-40°C to +85°C.
SYMBOL
TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range ,
PARAMETER
MIN
MAX
(Note 10) TYP (Note 10) UNITS
TEST CONDITIONS
3
mA
VCC Supply Current (Nonvolatile Write) fSCL = 400kHz; VCC = +5.5V; SDA = Open;
(for 2-wire, Active, Non-volatile Write State only)
7
mA
ISB
VCC Current (Standby)
VCC = +5.5V; VIN = VSS or VCC; SDA = VCC;
(for 2-wire, Standby State only)
15
μA
ILI
Input Leakage Current
VIN = VSS to VCC
10
μA
ILO
Output Leakage Current
VOUT = VSS to VCC
10
μA
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW Voltage
-1
VCC x 0.3
V
VOL
Output LOW Voltage
0.4
V
ICC1
VCC Supply Current (Active)
ICC2
fSCL = 400kHz; VCC = +5.5V; SDA = Open;
(for 2-wire, Active, Read and Volatile Write States only)
IOL = 3mA
NOTE:
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Endurance and Data Retention
PARAMETER
MIN
UNITS
Minimum Endurance
100,000
Data changes per bit per register
Data Retention
100
years
Capacitance
SYMBOL
CIN/OUT
(Note 11)
CIN (Note 11)
TEST
TYP
UNITS
TEST CONDITIONS
Input/Output Capacitance (SI)
8
pF
VOUT = 0V
Input Capacitance (SCL, WP, A1 and A0)
6
pF
VIN = 0V
Power-Up Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
0.2
50
V/ms
tr VCC (Note 11)
VCC Power-up Rate
tPUR (Note 12)
Power-up to Initiation of Read Operation
1
ms
tPUW (Note 12)
Power-up to Initiation of Write Operation
50
ms
NOTES:
11. This parameter is not 100% tested.
12. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
parameters are periodically sampled and not 100% tested.
AC Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing Level
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VCC x 0.5
11
FN8161.5
April 9, 2014
X9118
Equivalent A.C. Load Circuit
5V
3V
1533Ω
SPICE MACROMODEL
867Ω
RTOTAL
RL
RH
SDA OUTPUT
SDA OUTPUT
100pF
CW
CL
10pF
CL
10pF
25pF
100pF
RW
AC Timing High-Voltage Write Cycle Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
400
kHz
fSCL
Clock Frequency
tCYC
Clock Cycle Time
2500
ns
tHIGH
Clock High-Time
600
ns
tLOW
Clock Low-Time
1300
ns
tSU:STA
Start Setup Time
600
ns
tHD:STA
Start Hold Time
600
ns
tSU:STO
Stop Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
100
ns
tHD:DAT
SDA Data Input Hold Time
30
ns
tR
SCL and SDA Rise Time
300
ns
tF
SCL and SDA Fall Time
300
ns
tAA
SCL Low to SDA Data Output Valid Time
tDH
250
ns
SDA Data Output Hold Time
0
ns
tI
Noise Suppression Time Constant at SCL and SDA inputs
50
ns
tBUF
Bus Free Time (Prior to Any Transmission)
1300
ns
tSU:WPA
A0, A1 Setup Time
0
ns
tHD:WPA
A0, A1 Hold Time
0
ns
High-Voltage Write Cycle Timing
SYMBOL
tWR
PARAMETER
High-Voltage Write Cycle Time (store instructions)
TYP
MAX
UNITS
5
10
ms
XDCP Timing
SYMBOL
PARAMETER
TYP
UNITS
tWRPO
Wiper Response Time After the Third (last) Power Supply is Stable
8
µs
tWRL
Wiper Response Time After Instruction Issued (all load instructions)
8
µs
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FN8161.5
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X9118
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Timing Diagrams
Start and Stop Timing
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tAA
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tDH
FN8161.5
April 9, 2014
X9118
XDCP Timing (For All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
RW
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(ANY INSTRUCTION)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
Applications Information
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
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14
Two terminal Variable Resistor;
Variable current
FN8161.5
April 9, 2014
X9118
Application Circuits
NONINVERTING AMPLIFIER
VS
VOLTAGE REGULATOR
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
COMPARATOR WITH HYSTERISIS
OFFSET VOLTAGE ADJUSTMENT
R1
R2
VS
VS
–
+
VO
100kΩ
–
VO
+
+12V
10kΩ
}
10kΩ
}
TL072
10kΩ
R1
R2
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN8161.5
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X9118
Application Circuits (Continued)
ATTENUATOR
FILTER
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kW
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G V S
-1/2 ≤ G ≤ +1/2
R2
}
VS
R1
}
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R2
C1
VS
–
+
–
VO
+
R1
ZIN
R3
VO = G VS
G = - R2/R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
R2
–
C
R1
–
+
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
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FN8161.5
April 9, 2014
X9118
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
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17
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
FN8161.5
April 9, 2014