an9726

Using the HI5766EVAL1 Evaluation Board
TM
Application Note
December 1997
AN9726.1
Description
are connected together and the holding capacitors are
switched to the op-amp output nodes. The charge then
redistributes between CS and CH completing one sampleand-hold cycle. The front end sample-and-hold output is a
fully-differential, sampled-data representation of the analog
input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fullydifferential output for the converter core. During the sampling
phase, the VIN pins see only the on-resistance of a switch
and CS. The relatively small values of these components
result in a typical full power input bandwidth of 250MHz for
the converter.
The HI5766EVAL1 evaluation board for the HI5766 can be
used to evaluate the performance of the HI5766 10-bit
60MSPS analog-to-digital converter (ADC). As shown in the
Evaluation Board Functional Block Diagram, this evaluation
board includes sample clock driver circuitry, reference
voltage generators and single-ended to differential analog
input drive circuitry. Buffered digital data outputs are
conveniently provided for easy interfacing to a ribbon
connector or logic probes. The evaluation board is provided
with some prototyping area for the addition of user
designed custom interfaces or circuits.
HI5766 A/D Theory of Operation
As illustrated in the HI5766 functional block diagram and the
timing diagram in Figure 2, eight identical pipeline
subconverter stages, each containing a two-bit flash
converter and a two-bit multiplying digital-to-analog
converter, follow the S/H circuit with the ninth stage being a
two bit flash converter. Each converter stage in the pipeline
will be sampling in one phase and amplifying in the other
clock phase. Each individual subconverter clock signal is
offset by 180 degrees from the previous stage clock signal
resulting in alternate stages in the pipeline performing the
same operation.
The HI5766 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 1 depicts
the circuit for the front end differential-in-differential-out
sample-and-hold (S/H). The switches are controlled by an
internal sampling clock which is a non-overlapping two
phase signal, Φ1 and Φ2, derived from the master sampling
clock. During the sampling phase, Φ1, the input signal is
applied to the sampling capacitors, CS. At the same time the
holding capacitors, CH, are discharged to analog ground. At
the falling edge of Φ1 the input signal is sampled on the
bottom plates of the sampling capacitors. In the next clock
phase, Φ2, the two bottom plates of the sampling capacitors
Evaluation Board Functional Block Diagram
SAMPLE
CLOCK
INPUT
+5VD
50Ω
BIAS
TEE
CLK
CLOCK
OUT
CLK
1.2V
BANDGAP
VOLTAGE
REFERENCE
+2.5V
VAR
GAIN
CLK
VREF+
+2.0V
VAR
GAIN
CLK
VREF-
10
10
ANALOG
INPUT
G = +1
VIN+
D0-D9
D
Q
50Ω
VIN-
G = -1
DIGITAL
DATA
OUT
(D0 - D9)
HI5766
DGND
AGND
+5VD
+5VA
3-1
-5VA
1-888-INTERSIL or 321-724-7143
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Intersil and Design is a trademark of Intersil Corporation.
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Copyright
© Intersil Corporation 2000
Application Note 9726
HI5766 Functional Block Diagram
VDC
CLOCK
BIAS
CLK
VINVIN+
S/H
STAGE 1
DFS
2-BIT
FLASH
2-BIT
DAC
OE
+
∑
DVCC2
X2
D9 (MSB)
D8
D7
D6
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
STAGE 8
D5
D4
D3
2-BIT
FLASH
2-BIT
DAC
D2
D1
+
∑
D0 (LSB)
-
X2
DGND2
STAGE 9
2-BIT
FLASH
AVCC
3-2
AGND
DVCC1
DGND1
VREF +
VREF - (OPTIONAL)
Application Note 9726
Φ1
VIN+
Φ1
Φ1
Φ1
CH
CS
Φ2
VIN-
outputs of the eight identical two-bit subconverter stages
with the corresponding output of the ninth stage flash
converter before applying the eighteen bit result to the digital
error correction logic. The digital error correction logic uses
the supplementary bits to correct any error that may exist
before generating the final ten bit digital data output of the
converter.
-+
VOUT+
+-
VOUT-
CS
Φ1
Φ1
CH
FIGURE 1. ANALOG INPUT SAMPLE-AND-HOLD
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary
bit to be used by the digital error correction logic. The output
of each subconverter stage is input to a digital delay line
which is controlled by the internal sampling clock. The
function of the digital delay line is to time align the digital
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 7th cycle of the clock after the analog
sample is taken. This time delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output during
the following clock cycle. The digital output data is
synchronized to the external sampling clock by a double
buffered latching technique. The output of the digital error
correction circuit is available in two’s complement or offset
binary format depending on the state of the Data Format
Select (DFS) control input (see HI5766 Data Sheet Table 1,
A/D Code Table).
ANALOG
INPUT
CLOCK
INPUT
SN-1
HN-1
SN
HN
SN+1
HN+1
SN+2
SN+5
HN+5
SN+6
HN+6
SN+7
HN+7
SN+8
HN+8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N-1
B2, N-2
B1, N
B2, N-1
B1, N+1
B1, N+4
B1, N+5
B2, N+4
B2, N
9TH
STAGE
B9, N-5
B9, N-4
B9, N-3
DATA
OUTPUT
DN-6
DN-5
DN-4
B9, N
B2, N+5
B1, N+7
B2, N+6
B9, N+1
B9 N+2
B9, N+3
DN
DN+1
DN+2
DN-1
tLAT
NOTES:
1. SN: N-th sampling period.
2. HN: N-th holding period.
3. BM, N: M-th stage digital output corresponding to N-th sampled input.
4. DN: Final data output corresponding to N-th sampled input.
FIGURE 2. HI5766 INTERNAL CIRCUIT TIMING
3-3
B1, N+6
Application Note 9726
Layout and Power Supplies
The HI5766EVAL1 evaluation board is a four layer board
with a layout optimized for the best performance of the ADC.
Included in the application note are electrical schematics of
the evaluation board circuitry, a components layout, a
components part list and views of the various board layers
that make up the printed wiring board. The user should feel
free to copy the layout in their application. Refer to the
components layout and the evaluation board electrical
schematics for the following discussions.
The HI5766 A/D converter has separate analog and digital
supply and ground pins to keep digital noise out of the
analog signal path. The evaluation board provides separate
low impedance analog and digital ground planes. Since the
analog and digital ground planes of the evaluation board are
connected together at a single point where the power
supplies enter the board, DO NOT tie the grounds together
back at the power supplies.
The analog and digital supplies are also kept separate on the
evaluation board and should be driven by clean linear
regulated supplies. The power supplies can be hooked up
with external wires to the holes marked +5VAIN, +5VA1IN, 5VAIN, +5VDIN, +5VD1IN and +5VD2IN. +5VDIN, +5VD1IN
and +5VD2IN are digital supplies and should be returned to
DGND. +5VAIN, +5VA1IN and -5VAIN are the analog supplies
and should be returned to AGND. Table 1 lists the operational
supply voltages for the evaluation board. Single supply
operation of the converter is possible but the overall
performance of the converter may degrade.
TABLE 1. EVALUATION BOARD POWER SUPPLIES
POWER
SUPPLY
NOMINAL
VALUE
CURRENT
(TYP)
+5VAIN
5.0V ±5%
121mA
FUNCTION(S) SUPPLIED
Analog Input and Reference
Voltage Generator Op Amps,
Bandgap Reference
+5VA1IN
5.0V ±5%
30mA
A/D AVCC
-5VAIN
-5.0V ±5%
120mA
Analog Input and Reference
Voltage Generator Op Amps,
Bandgap Reference
+5VDIN
5.0V ±5%
5mA
Sample Clock Generator,
D0-D9 D-FF
+5VD1IN
5.0V ±5%
22mA
A/D DVCC1
+5VD2IN 5.0V ±5% /
3.0V ±10%
5mA
A/D DVCC2
Reference Voltage Generator Circuit
The HI5766 is designed to accept two external reference
voltage sources at the VREF input pins. Typical operation of
the converter requires VREF+ to be set at +2.5V and VREF - to
be set at 2.0V. However, it should be noted that the input
structure of the VREF+ and VREF - input pins consists of a
resistive voltage divider with one resistor of the divider
(nominally 500Ω) connected between VREF+ and VREF - and
the other resistor of the divider (nominally 2000Ω) connected
3-4
between VREF - and analog ground. This allows the user the
option of supplying only the +2.5V VREF+ voltage reference
with the +2.0V VREF - being generated internally by the
voltage division action of the input structure.
The HI5766 is tested with VREF - equal to +2.0V and VREF+
equal to +2.5V yielding a fully differential analog input voltage
range of ±0.5V.
In order to minimize overall converter noise it is recommended
that adequate high frequency decoupling be provided at both
of the reference voltage input pins, VREF+ and VREF -.
The VREF+ and VREF- reference voltage generation circuitry
on the evaluation board consists of a Intersil ICL8069 +1.2V
bandgap voltage reference (D1) along with operational
amplifiers (U3 and U4) both operating in a non-inverting
variable gain configuration that is utilized to generate the
reference voltages for the HI5766. The reference voltages,
VREF+ and VREF-, are set at the factory to the proper
voltage levels required by the HI5766. Variable resistor VR1
is used to adjust VREF+ to +2.5V and variable resistor VR2
is used to adjust VREF- to +2.0V.
Operation of the converter with a single +2.5V VREF+
reference voltage can be demonstrated by simply removing
R20 from the VREF- generation circuit. This opens the path
between the VREF- operational amplifier (U4) output and the
VREF- input of the HI5766 while still providing decoupling at
the converter VREF- voltage reference input pin.
Sample Clock Driver
In order to ensure rated performance of the HI5766, the duty
cycle of the sample clock should be held at 50%. It must also
have low phase noise and operate at standard TTL logic levels.
It can be difficult to find a low phase noise generator that will
provide a 40MHz squarewave at TTL logic levels.
Consequently, the HI5766EVAL1 evaluation board is designed
with a logic inverter (U7) acting as a voltage comparator to
generate the sampling clock for the HI5766 when a sinewave
(<±1.5V) is applied to the CLK input of the evaluation board.
The sample clock sinewave is AC coupled into the input of the
inverter and a discrete bias tee is used to bias the sinewave
around the trigger level of the inverter’s input. A potentiometer
(VR3) varies the DC bias voltage added to the sinewave input
allowing the user to adjust the duty cycle of the sampling clock
to obtain the best performance from the ADC and to evaluate
the effects of sample clock duty cycle on the performance of the
converter. The trigger level for the sample clock input to the
HI5766 converter is approximately 1.5V. Therefore, the duty
cycle of the sampling clock should be measured around the
1.5V trigger level at the HI5766 sample clock input pin.
The sinewave to logic level comparator drives a series of
additional inverters that provides isolation between the four
sample clocks used on the evaluation board. One clock is
used to drive the converter sample clock input pin, a second
clock is used to drive the digital output data (D0-D9) D-type
flip-flop and the last two provide CLK and CLK at the data
output connector, P2. The clock/data relationship at the P2
output connector is as follows. CLK has rising edges aligned
with data transitions and CLK has rising edges mid-bit.
Application Note 9726
The data corresponding to a particular analog input sample will
be available at the digital outputs of the HI5766 after the data
latency (7 cycles) plus the HI5766 digital data output delay.
The sample clock and digital output data signals are buffered
and made available through two connectors contained on the
evaluation board. The line buffering allows for driving long leads
or analyzer inputs. These drivers are not necessary for the
digital output data if the load presented to the converter does
not exceed the data sheet CMOS drive limits and a load
capacitance of 10pF. P1 allows the evaluation board to be
interfaced to the DSP evaluation boards available from Intersil
and should be installed on the far side (Layer 4) of the
evaluation board for proper signal routing to the DSP evaluation
boards. The digital output data and sample clock can also be
accessed by clipping the test leads of a logic analyzer or data
acquisition system onto the I/O pins of connector P2.
The A/D converters OE control input pin allows the digital
output data bus of the converter to be switched to a threestate high impedance mode. This feature enables the testing
and debugging of systems which are utilizing one or more
converters. This three-state control signal is not intended for
use as an enable/disable function on a common data bus
and could result in possible bus contention issues. The A/D
converters OE control input pin is controlled by the
installation or removal of a shunt, JP1, contained on the
evaluation board. Installation of JP1 forces the OE control
input pin low for normal operation while removal of JP1
allows the digital output data bus of the converter to be
switched to a three-state high impedance mode.
A DC voltage source, VDC, equal to 3.2V (typical), is made
available to the user to help simplify circuit design when using
an AC coupled differential input. This low output impedance
voltage source is not designed to be a reference but makes an
excellent DC bias source and stays well within the analog
input common mode voltage range over temperature.
VIN+
VIN
HI5766
VDC
-VIN
VIN -
FIGURE 3. AC COUPLED DIFFERENTIAL INPUT
The HI5766EVAL1 evaluation board accepts a single-ended
analog input and converts it to a differential signal for driving
the VIN+ and VIN- analog inputs of the converter. The singleended to differential conversion is accomplished through the
use of two operational amplifiers (U1 and U2). U1 is
configured as a unity gain amplifier and U2 is configured as
an inverting amplifier with a gain of minus one.
+5V
VIN+
0.5VP-P
VIN+
VIN+
0.25V < VDC < 4.75V
VIN-
0.5VP-P
The fully differential analog input of the HI5766 A/D can be
configured in various ways depending on the signal source
and the required level of performance.
+5V
VIN0.5VP-P
Analog Input
VINVDC = 4.75V
VDC = 0.25V
0V
0V
FIGURE 4. DIFFERENTIAL ANALOG INPUT COMMON MODE
VOLTAGE RANGE
Differential Analog Input Configuration
HI5766 Performance Characterization
For the AC coupled differential input (Figure 3) assume the
difference between VREF+, typically 2.5V, and VREF-,
typically 2.0V, is 0.5V. Fullscale is achieved when the VIN
and -VIN input signals are 0.5VP-P, with -VIN being
180 degrees out of phase with VIN. The converter will be at
positive fullscale when the VIN+ input is at VDC + 0.25V and
the VIN- input is at VDC - 0.25V (VIN+ - VIN- = +0.5V).
Conversely, the converter will be at negative fullscale when
the VIN+ input is equal to VDC - 0.25V and VIN- is at
VDC + 0.25V (VIN+ - VIN- = -0.5V).
Dynamic testing is used to evaluate the HI5766
performance. Among these tests are Signal-to-Noise and
Distortion Ratio (SINAD), Signal-to-Noise Ratio (SNR), Total
Harmonic Distortion (THD), Spurious Free Dynamic Range
(SFDR) and InterModulation Distortion (IMD).
Since the HI5766 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V,
see Figure 4. The performance of the ADC does not change
significantly with the value of the analog input common
mode voltage.
3-5
Figure 5 shows the test system used to perform dynamic
testing on high-speed ADCs at Intersil. The clock (CLK) and
analog input (AIN) signals are sourced from low phase noise
HP8662A synthesized signal generators that are phase
locked to each other to ensure coherence. The output of the
signal generator driving the ADC analog input is bandpass
filtered to improve the harmonic distortion of the analog input
signal. The comparator on the evaluation board will convert
the sine wave CLK input signal to a square wave to drive the
sample clock input of the HI5766. The ADC data is captured
by a logic analyzer and then transferred over the GPIB bus
to the PC. The PC has the required software to perform the
Fast Fourier Transform (FFT) and do the data analysis.
Application Note 9726
Coherent testing is recommended in order to avoid the
inaccuracies of windowing. The sampling frequency and
analog input frequency have the following relationship: fI/fS =
M/N, where fI is the frequency of the input analog sinusoid,
fS is the sampling frequency, N is the number of samples,
and M is the number of cycles over which the samples are
taken. By making M an integer and odd number (1, 3, 5, ...)
the samples are assured of being nonrepetitive.
Refer to the HI5766 data sheet for a complete list of test
definitions and the results that can be expected using the
evaluation board with the test setup shown. Evaluating the
part with a reconstruction DAC is only suggested when
doing bandwidth or video testing.
HP8662A
HP8662A
REF
BANDPASS
FILTER
CLK
RFIN
COMPARATOR
VIN
HI5766
CLK
DIGITAL DATA OUTPUT
HI5766EVAL1
EVALUATION BOARD
10
Video Testing
Figure 6 shows how a test system can be configured to do
video testing of the HI5766 with the DAC reconstruction
board and the HI5766EVAL1 evaluation board. The
appropriate test waveform is generated by a video source
such as the TSG100 or TEK1001 from Tektronix and applied
to the converter. The digitized video is converted back to
analog by the reconstruction DAC for evaluation by a video
analyzer, TEK VM700.
Since the HI5766 is a 10-bit A/D, install jumpers JP1 and
JP2 on the DAC reconstruction board to tie the DAC two
LSB’s high. Install JP3 so that the video out of the
reconstruction board will have negative going sync. JP5-9 on
the DAC reconstruction board are utilized to establish the
correct clock/data timing relationship into the DAC.
Setup the HI5766EVAL1 evaluation board for video testing
by following the procedures outlined previously in the
HI5766EVAL1 evaluation board application note on the
video input configuration and single-ended DC coupled
analog inputs. Input the video signal to the HI5766EVAL1
evaluation board through the SMA connector marked
VIDEO. Note that all cables carrying video should be 75Ω.
Finally, mate the DAC reconstruction board P1 connector to
the HI5766EVAL1 evaluation board P2 connector. Correct
alignment between the two boards will have P1 pin 34 of the
DAC reconstruction board plugged into P2 pin 25 of the
HI5766EVAL1 evaluation board.
See Application Note AN9419 “Using the DAC Reconstruct
Board” for additional applications information.
3-6
DAS9200
12-BIT DAC
GPIB
PC
OSCILLOSCOPE
FIGURE 5. HIGH-SPEED A/D TEST SYSTEM
VIDEO
SIGNAL
SOURCE
CLOCK
GEN
CLK
VIDEO
COMPARATOR
VIN
HI5766
CLK
DIGITAL DATA OUTPUT
HI5766EVAL1
EVALUATION BOARD
10 (P2)
12-BIT DAC
RECONSTRUCT BOARD
(DACRECON-EV)
VIDEO
TEK
VM700
FIGURE 6. VIDEO TEST SETUP
Application Note 9726
HI5766 Pin Descriptions
PIN NO.
NAME
Digital Supply (+5.0V)
15
DFS
Data Format Select Input
DGND1
Digital Ground
16
D9
Data Bit 9 Output (MSB)
3
DVCC1
Digital Supply (+5.0V)
17
D8
Data Bit 8 Output
4
DGND1
Digital Ground
18
D7
Data Bit 7 Output
5
AVCC
Analog Supply (+5.0V)
19
D6
Data Bit 6 Output
6
AGND
Analog Ground
20
D5
Data Bit 5 Output
7
VREF+
+2.5V Positive Reference Voltage
Input
21
DGND2
22
CLK
8
VREF -
+2.0V Negative Reference Voltage
Input (Optional)
23
DVCC2
9
VIN+
Positive Analog Input
24
D4
Data Bit 4 Output
10
VIN-
Negative Analog Input
25
D3
Data Bit 3 Output
11
VDC
DC Bias Voltage Output
26
D2
Data Bit 2 Output
12
AGND
Analog Ground
27
D1
Data Bit 1 Output
13
AVCC
Analog Supply (+5.0V)
28
D0
Data Bit 0 Output (LSB)
14
OE
PIN NO.
NAME
1
DVCC1
2
DESCRIPTION
DESCRIPTION
Digital Ground
Sample Clock Input
Digital Output Supply
(+3.0V or +5.0V)
Digital Output Enable Control Input
FIGURE 7. HI5766EVAL1 EVALUATION BOARD PARTS LAYOUT (NEAR SIDE)
3-7
Application Note 9726
FIGURE 8. HI5766EVAL1 EVALUATION BOARD COMPONENT NEAR SIDE (LAYER 1)
FIGURE 9. HI5766EVAL1 EVALUATION BOARD GROUND PLANE LAYER (LAYER 2)
3-8
Application Note 9726
FIGURE 10. HI5766EVAL1 EVALUATION BOARD POWER PLANE LAYER (LAYER 3)
FIGURE 11. HI5766EVAL1 EVALUATION BOARD COMPONENT FAR SIDE (LAYER 4)
3-9
Application Note 9726
FIGURE 12. HI5766EVAL1 EVALUATION BOARD PARTS LAYOUT (FAR SIDE)
3-10
+5VL
C34 +
4.7µF
C35
E13
0.1µF
E14
3-11
5VD2
C33 +
4.7µF
R17
4.99K
JP3
C32
0.1µF
D0 - D9, CLK4 (CLK
TO P1
U5
1
5VD1
+
2
C25
4.7µF
3
C27
0.1µF
5
6
7
VREF+
8
VREF-
9
VIN+
10
VIN-
11
VDC
12
13
+5VA1
+
14
+
D0
DGND1
D1
DVCC1
D2
DGND1
D3
AVCC
D4
AGND
DVCC2
VREF+
VREF-
HI5766
VIN+
CLK
DGND2
D5
VIN-
D6
VDC
D7
AGND
D8
AVCC
D9
OE
DFS
U6
27
1
26
2
25
3
24
4
23
5
22
6
CLK1
21
7
20
8
19
9
18
10
17
11
16
12
VCC 24
23
D0
Q0
22
D1
Q1
21
D2
Q2
20
D3
Q3
D4
Q4 19
FCT821A
Q5 18
D5
Q6 17
D6
Q7 16
D7
Q8 15
D8
Q9 14
D9
CP 13
GND
P2
OE
D0 1
2
D1 3
4
D2 5
6
D3 7
8
D4 9
10
D5 11
12
D6 13
14
D7 15
16
D8 17
18
D9 19
20
21
22
23
24
15
CLK2
CLK4
R16
R15
C28
4.7µF
C29
0.1µF
C30
4.7µF
C31
0.1µF
JP1
4.99K
4.99K
+5VD
JP1-3
U5-6
C25-35
R15-17
FB7
E13-14
P1
CLK3
JP2
Application Note 9726
4
C26
0.1µF
DVCC1
28
HI5766EVAL1 Evaluation Board Schematic Diagrams
FB7
+5VD
Application Note 9726
HI5766EVAL1 Evaluation Board Schematic Diagrams
(Continued)
+5VA
+
1
J1
C1
0.1µF
C3
4.7µF
7
3
VIN
NC
+
8
V+
VV-
-
C6
0.1µF
V+
R1
56.2
2
C2
0.01µF
5
6
VIN+
R22
10
U1
OPA642U
4
-5VA
C4
0.01µF
R6
100
C5
+ 4.7µF
R8
0
VDC
R2
22.1
C61
1000pF
R9
A/R
R5 499
+5VA
R7
100
+
C7
C8
0.01µF 0.1µF
1
7
2
NC
-
8
V+
V+
V-
R3
499
+
R4
0 OR 249
C10
C9
0.01µF 4.7µF
V-
U2
5
3
6
OPA642U
4
-5VA
C11
0.01µF
C12
+ 4.7µF
J1
U1-2
C1-13, 61
R1-9, 22, 23
3-12
R23
10
VINC13
0.1µF
Application Note 9726
HI5766EVAL1 Evaluation Board Schematic Diagrams
(Continued)
+5VA
+5VA
+ C14
4.7µF
C59
0.01µF
+
R10
1
4.99K
7
1.2V
3
8
+ C16
4.7µF
4
NC
+
8
V-
-
5
R19
0
6
2.5V
VREF+
+
U3
OPA642U
4
C15
0.01µF
C17
0.01µF
V+
V+
V-
D1
ICL8069CCBA
2
C60
0.01µF
C18
4.7µF
C55
0.01µF
C56
4.7µF
-5VA
C19
0.01µF
C20
+ 4.7µF
R11
499
R12
249
VR1
1.0K
1(CCW)
2
VREF+
3(CW)
VREF+
+5VA
+
1
C22
4.7µF
7
3
NC
+
8
V+
V-
2
-
C21
0.01µF
V+
V5
6
U4
OPA642U
4
-5VA
C23
0.01µF
R13
499
R14
249
VR2
1.0K
1(CCW)
2
VREF-
3(CW)
VREF-
3-13
C24
+ 4.7µF
R20
0
2.0V
VREF-
+
C57
0.01µF
C58
4.7µF
Application Note 9726
HI5766EVAL1 Evaluation Board Schematic Diagrams
(Continued)
+5VD
+
C36
0.1µF
J2
C41
C42
4.7µF 0.1µF
U7
C37
0.1µF
AC04
13
U7
1
12
14
2
CLK1
CLK IN
R18
56.2
7
L1
1.5µH
+5VD
+
VR3
1.0K
AC04
U7
9
1(CCW)
2
(CLK)
8
CLK2
AC04
(CLK)
3(CW)
C38
C39
4.7µF 0.1µF
U7
11
C40
0.1µF
R21
100
10
U7
3
AGND
TEST
POINT
TP1
TP2
DGND
TEST
POINT
TP3
CLK3
AC04
(CLK)
4
AC04
TP4
U7
5
6
CLK4
(CLK)
AC04
E1
E2
E7
E8
FB1
+5VAIN
FB4
+5VA
+
AGND
E3
C43
C44
4.7µF 0.1µF
+5VDIN
+
DGND
(ANALOG INPUT AND REFERENCE
VOLTAGE GENERATOR OP-AMPS,
BANDGAP REFERENCE)
E4
E9
C49 C50
4.7µF 0.1µF
E10
FB2
+5VA1IN
+
AGND
E5
FB5
+5VA1 (A/D AVCC)
+5VD1IN
+
DGND
C45 C46
4.7µF 0.1µF
AGND AND DGND TIE TOGETHER
AT A SINGLE POINT WHERE
THE POWER SUPPLIES
ENTER THE PWB
E6
E11
C51
C52
4.7µF 0.1µF
AGND
FB6
-5VA
+
C47
C48
4.7µF 0.1µF
+5VD2IN
(ANALOG INPUT AND REFERENCE DGND
VOLTAGE GENERATOR OP-AMPS,
BANDGAP REFERENCE)
J2
U7
C36-54
R18, 21
VR3
FB1-6
E1-12
L1
3-14
+5VD1
(A/D DVCC1)
E12
FB3
-5VAIN
+5VD
(SAMPLE CLOCK
GENERATOR,
D F-F VIA LPF)
+
C53
4.7µF
C54
0.1µF
+5VD2
(+5V/+3V)
(A/D DVCC2)
Application Note 9726
HI5766EVAL1 Evaluation Board Schematic Diagrams
(Continued)
P1C
D1
D2
D4
D6
D8
CLK4 (CLK)
D0 - D9, CLK4 (CLK)
3-15
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
P1A
D0
D3
D5
D7
D9
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
Application Note 9726
HI5766EVAL1 Evaluation Board Parts List
REFERENCE DESIGNATOR
QTY
R1,18
2
56.2Ω, 1/8W 805 CHIP, 1%
R9
1
A/RΩ, 1/8W 805 CHIP, 1%
R2
1
22.1Ω, 1/8W 805 CHIP, 1%
R3, 5, 11, 13
4
499Ω, 1/8W 805 CHIP, 1%
R4, 12, 14
3
249Ω, 1/8W 805 CHIP, 1%
R8, 19, 20
3
0.0Ω, 1/4W 805 CHIP, 1%
R6, 7, 21
3
100Ω, 1/8W 805 CHIP, 1%
R10, 15, 16, 17
4
4.99KΩ, 1/8W 805 CHIP, 1%
R22, 23
2
10Ω, 1/16W 402 CHIP, 1%
VR1, 2, 3
3
1kΩ TRIM POT
C3, 5, 10, 12, 14, 16, 18, 20, 22, 24, 25, 28, 30, 33, 34, 38, 41, 43,
45, 47, 49, 51, 53, 56, 58
25
4.7µF CHIP TANT CAP, 10WVDC, 20%, EIA CASE A
C1, 6, 7, 13, 26, 27, 29, 31, 32, 35, 36, 37, 39, 40, 42, 44, 46, 48,
50, 52, 54
21
0.1µF CER CAP, 50WVDC, 10%, 805 CASE, Y5V DIELECTRIC
C61
1
1000pF CER CAP, 50WVDC, 10%, 805 CASE, X7R DIELECTRIC
C2, 4, 8, 9, 11, 15, 17, 19, 21, 23, 55, 57, 59, 60
14
0.01µF CER CAP, 50WVDC, 10%, 805 CASE, X7R DIELECTRIC
FB1-7
7
10µH FERRITE BEAD
L1
1
1.5µH CHIP INDUCTOR, 1210 CASE
J1, 2
2
SMA STRAIGHT JACK PCB MOUNT
---
4
RUBBER FEET
---
DESCRIPTION
DUT CLAMP
JP1, 2, 3
3
1x2 HEADER
JPH1, 2, 3
3
1x2 HEADER JUMPER
P2
1
2x12 HEADER
P1
1
64-PIN EUROCARD RT ANGLE
AGND, DGND
4
TEST POINT
D1
1
INTERSIL ICL8069CCBA LOW VOLTAGE BANDGAP REFERENCE
U5
1
INTERSIL HI5766KCB 10-BIT 60MHz A/D CONVERTER
U1, 2, 3, 4
4
OP-AMP
U6
1
10-BIT D-TYPE FLIP-FLOP
U7
1
HEX INVERTER
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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