an9707

Using the HI5805EVAL1 Evaluation Board
TM
Application Note
March 1997
Description
AN9707
connection to most laboratory signal generators. In addition,
the duty cycle of the clock driving the A/D converter is made
adjustable by way of a potentiometer so that the effects of
sample clock duty cycle on the HI5805 may be observed.
The HI5805EVAL1 evaluation board is made available to
allow the circuit designer the ability to evaluate the
performance of the Intersil HI5805 monolithic 12-bit 5MSPS
analog-to-digital converter (ADC). As shown in the
Evaluation Board Functional Block Diagram, this evaluation
board includes sample clock generation circuitry, a singleended to differential analog input amplifier configuration and
digital data output latches/buffers. The buffered digital data
outputs are conveniently provided for easy interfacing to a
ribbon connector or logic probes. In addition, the evaluation
board is provided with some prototyping area for the addition
of user designed custom interfaces or circuits.
The analog input signal is also connected through an SMA
type RF connector, J1, and applied to a single-ended to
differential analog input amplifier. This input is AC-coupled
and terminated in 50W allowing for connection to most
laboratory signal generators. A differential RC lowpass filter
is incorporated on the output of the differential amplifier to
limit the broadband noise going into the HI5805 converter.
The digital data output latches/buffers consist of a pair of
74ALS574A D-type flip-flops. With this digital output
configuration the digital output data transitions seen at the
I/O connector are essentially time aligned with the rising
edge of the sampling clock.
The sample clock generator circuit accepts the external
sampling signal through an SMA type RF connector, J2. This
input is AC-coupled and terminated in 50W allowing for
Evaluation Board Functional Block Diagram
TTL COMPARATOR
CLK
CLOCK
OUT
(CLK)
50Ω
+5VD
-5VD
CLK
VREFOUT
G = +1
VREFIN
VIN+
ANALOG
INPUT
CLK
D0-D11
12
12
D
Q
G = -1
50Ω
VIN-
DIGITAL
DATA
OUT
(D0 - D11)
HI5805
DGND
AGND
+5VD
3-1
-5VD
+5VA
-5VA
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Application Note 9707
HI5805 A/D Theory of Operation
the result that alternate stages in the pipeline will perform the
same operation. The output of each of the three identical fourbit subconverter stages is a four-bit digital word containing a
supplementary bit to be used by the digital error correction
logic. The output of each subconverter stage is input to a digital
delay line which is controlled by the internal clock. The function
of the digital delay line is to time align the digital outputs of the
three identical four-bit subconverter stages with the
corresponding output of the fourth stage flash converter before
inputting the sixteen bit result into the digital error correction
logic. The digital error correction logic uses the supplementary
bits to correct any error that may exist before generating the
final twelve-bit digital data output (D0-D11) of the converter.
The HI5805 is a 12-bit fully differential sampling pipelined
A/D converter with digital error correction. Figure 1 depicts
the circuit for the converters front-end differential-indifferential-out sample-and-hold (S/H). The sampling
switches are controlled by internal sampling clock signals
which consist of two phase non-overlapping clock signals, φ1
and φ2, derived from the master clock (CLK) driving the
converter. During the sampling phase, φ1, the input signal is
applied to the sampling capacitors, CS. At the same time the
holding capacitors, CH, are discharged to analog ground. At
the falling edge of φ1 the input analog signal is sampled on
the bottom plates of the sampling capacitors. In the next
clock phase, φ2, the two bottom plates of the sampling
capacitors are connected together and the holding capacitors
are switched to the op amp output nodes. The charge then
redistributes between CS and CH, completing one sampleand-hold cycle. The output of the sample-and-hold is a fullydifferential, sampled-data representation of the analog input.
The circuit not only performs the sample-and-hold function,
but can also convert a single-ended input to a fully-differential
output for the converter core. During the sampling phase, the
VIN pins see only the on-resistance of the switches and CS.
The relatively small values of these components result in a
typical full power input bandwidth of 100MHz for the converter.
φ1
VIN +
φ1
CS
φ2
VIN -
φ1
CH
VOUT +
-+
+ -
VOUT -
CS
φ1
CH
φ1
φ1
FIGURE 1. ANALOG INPUT SAMPLE-AND-HOLD
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is presented on
the digital data output bus on the 3rd cycle of the clock after
the analog sample is taken. This delay is specified as the
data latency. After the data latency time, the data
representing each succeeding analog sample is output on
the following clock pulse. The output data is synchronized to
the external sampling clock with a data latch and is
presented in offset binary format.
As illustrated in the HI5805 Functional Block Diagram and the
timing diagram contained Figure 2, three identical pipeline
subconverter stages, each containing a four-bit flash converter,
a four-bit digital-to-analog converter and an amplifier with a
voltage gain of 8, follow the S/H circuit with the fourth stage
being only a 4-bit flash converter. Each converter stage in the
pipeline will be sampling in one phase and amplifying in the
other clock phase. Each individual sub-converter clock signal is
offset by 180 degrees from the previous stage clock signal, with
ANALOG
INPUT
CLOCK
INPUT
INPUT
S/H
1ST
STAGE
SN-1
HN-1
HN
SN
SN+1
B1, N-1
2ND
STAGE
3RD
STAGE
B2, N-2
4TH
STAGE
B4, N-3
B2, N-1
HN+2
B3, N-1
HN+3
B3, N
SN+5
B1, N+2
B3, N+1
HN+5
B3, N+1
B4, N+1
DN
tLAT
FIGURE 2. HI5805 INTERNAL CIRCUIT TIMING
HN+6
B1, N+7
B2, N+3
B3, N+2
B4, N+1
DN+1
SN+6
B1, N+3
B2, N+2
NOTES:
1. SN: N-th sampling period.
2. HN: N-th holding period.
3. BM, N: M-th stage digital output corresponding to N-th sampled input.
4. DN: Final data output corresponding to N-th sampled input.
3-2
HN+4
B2, N+1
B4, N
DN-1
SN+4
B1, N+1
B2, N+1
B4, N-1
DN-2
SN+3
B1, N+1
B2, N
B4, N-2
DN-3
SN+2
B1, N
B3, N-2
DATA
OUTPUT
HN+1
B3, N+3
B4, N+2
DN+1
DN+2
Application Note 9707
HI5805 Functional Block Diagram
BIAS
VDC
CLOCK
VINVIN+
REF
S/H
CLK
VROUT
VRIN
STAGE 1
DVCC3
4-BIT
4-BIT
FLASH
DAC
+
∑
-
D11 (MSB)
D10
X8
D9
STAGE 3
4-BIT
4-BIT
FLASH
DAC
+
∑
DIGITAL DELAY
AND
DIGITAL ERROR CORRECTION
D8
D7
D6
D5
D4
D3
D2
D1
X8
D0 (LSB)
STAGE 4
4-BIT
DGND3
FLASH
AVCC
AGND
3-3
DVCC1
DGND1
DVCC2
DGND2
Application Note 9707
Reference Generator, VROUT and VRIN
The HI5805 has an internal reference voltage generator,
therefore no external reference voltage is required. VROUT
must be connected to VRIN when using the internal
reference. Internal to the converter, two reference voltages
of 1.3V and 3.3V are generated making for a fully differential
analog input signal range of ±2V.
The HI5805 can be used with an external reference. The
converter requires only one external reference voltage
connected to the VRIN pin with VROUT left open. The
evaluation board is configured with VROUT connected to VRIN
through a 0Ω resistor, R15. If it is desired to evaluate the
performance of the converter utilizing an externally provided
reference voltage, R15 can be removed and the alternate
reference voltage can be brought in through twisted pair wire or
coaxial cable. The latter would be the recommended method
since it would provide the greatest immunity to externally
coupled noise voltages. In order to minimize overall converter
noise it is recommended that adequate high frequency
decoupling be provided at the reference input pin, VRIN .
The difference between the converter's two internally
generated voltage references is 2V. For the AC coupled
differential input, (Figure 3), if VIN is a 2VP-P sinewave with VIN being 180 degrees out of phase with VIN, the converter
will be at positive full scale when the VIN+ input is at VDC + 1V
and the VIN- input is at VDC - 1V (VIN+ - VIN- = +2V).
Conversely, the ADC will be at negative full scale when the
VIN+ input is equal to VDC - 1V and VIN- is at VDC + 1V (VIN+
- VIN- = -2V).
+5V
VIN+
2.0VP-P
VIN+
+5V
VIN2.0VP-P
VIN+
1.0V < VDC < 4.0V
VIN2.0VP-P
0V
VINVDC = 4.0V
VDC = 1.0V
0V
FIGURE 4. DIFFERENTIAL ANALOG INPUT COMMON MODE
VOLTAGE RANGE
Analog Input
The fully differential analog input of the HI5805 A/D can be
configured in various ways depending on the signal source
and the required level of performance.
Differential Analog Input Configuration
A fully differential connection (Figure 3) will yield the best
performance from the HI5805 A/D converter. Since the
HI5805 is powered off a single +5V supply, the analog input
must be biased so it lies within the analog input common
mode voltage range of 1.0V to 4.0V. Figure 4 illustrates the
differential analog input common mode voltage range that
the converter will accommodate. The performance of the
ADC does not change significantly with the value of the
common mode voltage.
VIN+
VIN
HI5805
VDC
-VIN
VIN -
FIGURE 3. AC COUPLED DIFFERENTIAL INPUT
A 2.3V DC bias voltage source, VDC, half way between the top
and bottom internally generated reference voltages, is made
available to the user to help simplify circuit design when using a
differential input. This low output impedance voltage source is
not designed to be a reference but makes an excellent bias
source and stays within the analog input common mode
voltage range over temperature. The DC voltage source has a
temperature coefficient of about +200ppm/oC.
3-4
Evaluation Board Layout and Power Supplies
The HI5805 evaluation board is a four layer board with a layout
optimized for the best performance of the ADC. This application
note includes an electrical schematic of the evaluation board, a
component parts list, a component placement layout drawing
and reproductions of the various board layers used in the board
stack-up. The user should feel free to copy the layout in their
application. Refer to the component layout and the evaluation
board electrical schematic for the following discussions.
The HI5805 monolithic A/D converter has been designed
with separate analog and digital supply and ground pins to
keep digital noise out of the analog signal path. The
evaluation board provides separate low impedance analog
and digital ground planes on layer 2. Since the analog and
digital ground planes are connected together at a single
point where the power supplies enter the board, DO NOT tie
them together back at the power supplies.
The analog and digital supplies are also kept separate on
the evaluation board and should be driven by clean linear
regulated supplies. The external power supplies can be
hooked up with wires to the plated through holes marked
+5VAIN, +5VAIN1, -5VAIN, +5VDIN, +5VD1IN, +5VD2IN,
-5VDIN, AGND and DGND near the analog prototyping area.
+5VDIN, +5VD1IN, +5VD2IN and -5VDIN are digital
supplies and should be returned to DGND. +5VAIN,
+5VAIN1 and -5VAIN are the analog supplies and should be
returned to AGND. Table 1 lists the operational supply
voltages, typical current consumption and the evaluation
board circuit function being powered. Single supply
operation of the converter is possible but the overall
performance of the converter may degrade.
Application Note 9707
converter. The HI5805 clock input trigger level is approximately
1.5V. Therefore, the duty cycle of the sampling clock should be
measured at this 1.5V trigger level. Test point TP4 provides a
convenient point to monitor the sample clock duty cycle and
make any required adjustments.
TABLE 1. HI5805 EVALUATION BOARD POWER SUPPLIES
POWER
SUPPLY
NOMINAL
VALUE
CURRENT
(TYP)
FUNCTION(S)
SUPPLIED
+5VAIN
5.0V ±5%
22mA
Op Amps
+5VAIN1
5.0V ±5%
46mA
A/D AVCC
-5VAIN
-5.0V ±5%
22mA
Op Amps
+5VDIN
5.0V ±5%3
43mA
CLK Comparator,
D0-D11 D-FF
+5VD1IN
5.0V ±5%
13mA
A/D DVCC1 and
DVCC2
+5VD2IN
5.0V ±5%
1mA
A/D DVCC3
-5VDIN
-5.0V ±5%
3mA
CLK Comparator
Figure 5 shows the sample clock and digital data timing
relationship for the evaluation board. The data
corresponding to a particular sample will be available at the
digital data outputs of the HI5805 after the data latency time,
tLAT, of 3 sample clock cycles plus the HI5805 digital data
output delay, tOD. Table 2 lists the values that can be
expected for the indicated timing delays. Refer to the HI5805
data sheet for additional timing information.
It should be noted that overdriving the analog input beyond
the ±2.0V fullscale input voltage range will not damage the
converter as long as the overdrive voltage stays within the
converters analog supply voltages. In the event of an
overdrive condition the converter will recover within one
sample clock cycle.
The sample clock and digital output data signals are made
available through two connectors contained on the evaluation
board. The line buffering provided by the data output latches
allows for driving long leads or analyzer inputs. These data
latches are not necessary for the digital output data if the load
presented to the converter does not exceed the data sheet load
limits of one standard TTL load and 10pF. The P1 I/O connector
allows the evaluation board to be interfaced to the DSP
evaluation boards available from Intersil. Alternatively, the
digital output data and sample clock can also be accessed by
clipping the test leads of a logic analyzer or data acquisition
system onto the I/O pins of connector header P2.
Sample Clock Driver, Timing and I/O
In order to ensure rated performance of the HI5805, the duty
cycle of the sample clock should be held at 50% ±5%. It must
also have low phase noise and operate at standard TTL levels.
A voltage comparator (U3) with TTL output levels is provided on
the evaluation board to generate the sampling clock for the
HI5805 when a sinewave (< ±3V) or squarewave clock is
applied to the CLK input (J1) of the evaluation board. A
potentiometer (VR1) is provided to allow the user to adjust the
duty cycle of the sampling clock to obtain the best performance
from the ADC and to allow the user to investigate the effects of
expected duty cycle variations on the performance of the
TABLE 2. TIMING SPECIFICATIONS
PARAMETER
DESCRIPTION
tOD
HI5805 Digital Output Data Delay
tPD1
U3 Prop Delay
tPD2
U5/6 Prop Delay
SINEWAVE CLK IN
(J1)
tPD1
HI5805 SAMPLE
CLOCK INPUT
(CLK)
tOD
HI5805 DIGITAL
DATA OUTPUT
(D0 - D11)
DATA N-1
DATA N
CLOCK OUT
(CLK AT TP4, P1-C20 OR P2-13)
tPD2
DIGITAL DATA OUTPUTS
(74ALS574)
DATA N-1
DATA N
FIGURE 5. EVALUATION BOARD CLOCK AND DATA TIMING RELATIONSHIPS
3-5
TYP
8ns
4.5ns
9ns
Application Note 9707
HI5805 Performance Characterization
TABLE 3. HI5805 PIN DESCRIPTION
Dynamic testing is used to evaluate the performance of the
HI5805 A/D converter. Among the tests performed are Signalto-Noise and Distortion Ratio (SINAD), Signal-to-Noise Ratio
(SNR), Total Harmonic Distortion (THD), Spurious Free
Dynamic Range (SFDR) and Intermodulation Distortion (IMD).
PIN NO.
NAME
1
CLK
2
DVCC1
Digital Supply (5.0V)
Figure 6 shows the test system used to perform dynamic
testing on high-speed ADCs at Intersil. The clock (CLK) and
analog input (VIN) signals are sourced from low phase noise
HP8662A synthesized signal generators that are phase locked
to each other to ensure coherence. The output of the signal
generator driving the ADC analog input is bandpass filtered to
improve the harmonic distortion of the analog input signal. The
comparator on the evaluation board will convert the sine wave
CLK input signal to a square wave at TTL logic levels to drive
the sample clock input of the HI5805. The ADC data is
captured by a logic analyzer and then transferred over the GPIB
bus to the PC. The PC has the required software to perform the
Fast Fourier Transform (FFT) and do the data analysis.
3
DGND1
Digital Ground
4
DVCC1
Digital Supply (5.0V)
5
DGND1
Digital Ground
6
AVCC
Analog Supply (5.0V)
7
AGND
Analog Ground
8
VIN+
Positive Analog Input
9
VIN-
Negative Analog Input
10
VDC
DC Bias Voltage Output
11
VROUT
12
VRIN
Reference Voltage Input
13
AGND
Analog Ground
14
AVCC
Analog Supply (5.0V)
15
D11
Data Bit 11 Output (MSB)
16
D10
Data Bit 10 Output
17
D9
Data Bit 9 Output
18
D8
Data Bit 8 Output
19
D7
Data Bit 7 Output
20
D6
Data Bit 6 Output
21
DGND2
Digital Output Ground
22
DVCC2
Digital Output Supply (3.0V to 5.0V)
23
D5
Data Bit 5 Output
24
D4
Data Bit 4 Output
25
D3
Data Bit 3 Output
26
D2
Data Bit 2 Output
27
D1
Data Bit 1 Output
28
D0
Data Bit 0 Output (LSB)
Coherent testing is recommended in order to avoid the
inaccuracies of windowing. The sampling frequency and
analog input frequency have the following relationship: FI/FS
= M/N, where FI is the frequency of the input analog
sinusoid, FS is the sampling frequency, N is the number of
samples, and M is the number of cycles over which the
samples are taken. By making M an integer and odd number
(1, 3, 5, ...) the samples are assured of being nonrepetitive.
Refer to the HI5805 data sheet for a complete list of test
definitions and the results that can be expected using the
evaluation board with the test setup shown. Evaluating the
part with a reconstruction DAC is only suggested when
doing bandwidth or video testing.
HP8662A
HP8662A
REF
BANDPASS
FILTER
CLK
VIN
DESCRIPTION
Input Clock
Reference Voltage Output
COMPARATOR
VIN
HI5805
CLK
DIGITAL DATA OUTPUT
HI5805EVAL1
EVALUATION BOARD
10
DAS9200
12-BIT DAC
GPIB
PC
OSCILLOSCOPE
FIGURE 6. HIGH-SPEED A/D PERFORMANCE TEST SYSTEM
3-6
Application Note 9707
HI5805EVAL1 Typical Performance Curves
12
-20
-30
11
-50
dB
ENOB (BITS)
-40
10
9
-60
8
-70
7
6
-80
-90
1
10
INPUT FREQUENCY (MHz)
1
100
10
100
INPUT FREQUENCY (MHz)
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
FIGURE 8. TOTAL HARMONIC DISTORTION (THD) vs INPUT
FREQUENCY
70
-20
-30
60
-40
dB
dB
-50
50
-60
-70
-80
40
-90
-100
30
10
1
1
100
10
100
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
FIGURE 9. SINAD vs INPUT FREQUENCY
FIGURE 10. SECOND HARMONIC DISTORTION (2HD) vs
INPUT FREQUENCY
70
-20
-30
-40
60
dB
dB
-50
50
-60
-70
-80
40
-90
30
10
1
INPUT FREQUENCY (MHz)
FIGURE 11. SNR vs INPUT FREQUENCY
3-7
-100
100
1
10
100
INPUT FREQUENCY (MHz)
FIGURE 12. THIRD HARMONIC DISTORTION (3HD) vs INPUT
FREQUENCY
Application Note 9707
FIGURE 13. HI5805EVAL1 EVALUATION BOARD PARTS LAYOUT (NEAR SIDE)
FIGURE 14. HI5805EVAL1 EVALUATION BOARD COMPONENT NEAR SIDE (LAYER 1)
3-8
Application Note 9707
FIGURE 15. HI5805EVAL1 EVALUATION BOARD GROUND PLANE LAYER (LAYER 2)
FIGURE 16. HI5805EVAL1 EVALUATION BOARD POWER PLANE LAYER (LAYER 3)
3-9
Application Note 9707
FIGURE 17. HI5805EVAL1 EVALUATION BOARD COMPONENT FAR SIDE (LAYER 4)
FIGURE 18. HI5805EVAL1 EVALUATION BOARD PARTS LAYOUT (FAR SIDE)
3-10
+
C28
10µF
C29
0.1µF
C30
0.1µF
R17
4.99K
E16
E15
D0 - D11, CLK
3-11
R16
4.99K
+5VD2
+
C33
10µF
C34
0.1µF
2
1
CLK
2
3
C22
0.1µF
L1
12µH
3
C23
0.1µF
5
4
6
7
8
VIN+
9
VIN-
10
VDC
11
12
R15
0
13
14
+5VA1
C24
10µF
+
CLK
CLK
D0
D0
DV
DVCC1
CC1
D1
D1
DGND1
DGND1
D2
D2
DV
DVCC1
CC1
D3
D3
DGND1
DGND1
D4
D4
AVCC
AV
CC
D5
D5
AGND
AGND
HI5805
VVIN+
IN+
DV
DVCC2
CC2
DGND2
DGND2
VVININ-
D6
D6
VVDC
DC
D7
D7
VVREFOUT
REFOUT
D8
D8
VVREFIN
REFIN
D9
D9
AGND
AGND
D10
D10
AVCC
AV
CC
D11
D11
28
4
27
5
26
6
25
7
24
8
23
9
22
10
21
1
20
2
19
3
18
4
17
5
16
6
15
7
8
C27
0.1µF
9
10
C25
C26
0.1µF 0.1µF
VCC
OE
20
Q0 19
Q1 18
D0
D1
Q2 17
Q3 16
D0
Q4 15
Q5 14
D2
D4
D7
Q6 13
Q7 12
GND
CP
D2
D3
D4
‘574
D5
D6
VCC
OE
D0
D1
D2
D3
D4
‘574
D5
D1
D3
D5
11
20
Q0 19
Q1 18
D6
Q2 17
Q3 16
D8
Q4 15
Q5 14
D10
D7
Q6 13
Q7 12
GND
CP
D6
P2
D7
D9
D11
11
U6
JP1
U4-6
C21-30,33,34
R15-17
FB8
E15-16
L1
P2
TP4
TP4
CLK
Application Note 9707
+
C21
10µF
U5
1
U4
+5VD1
JP1
HI5805EVAL1 Evaluation Board Schematic Diagrams
FB8
+5VD
Application Note 9707
HI5805EVAL1 Evaluation Board Schematic Diagrams
(Continued)
+5VA
1
J1
C1
0.1µF
C2
0.01µF
7
3
VIN
NC
+
8
C6
0.1µF
V+
R1
56.2
6
V+
V2
VIN+
R18
10
U1
V-
-
+
C3
10µF
5
OPA642U
4
-5VA
C4
0.01µF
+
R6
100
C5
10µF
VDC
R2
22.1
R14
A/R
C31
47pF
R5
499
+5VA
1
C9
0.01µF
7
2
NC
-
8
+
V-
OPA642U
4
-5VA
C11
0.01µF
+
C12
10µF
+5VD
+
1
J2
C14
0.1µF
2
CLK IN
3
-5VD
C17
10µF +
V+
+
7
2
3(CW)
3-12
C19
0.1µF
CLK
1 (CCW)
Q
LE
GND
8
V5
U3
6
MAX9686BCSA
4
-
VR1
5K
C20
0.1µF
CLK
C18
0.01µF
R12
249
-5VD
+5VD
R11
249
C16
10µF
C15
0.01µF
Q
R9
49.9
R10
249
C7
0.1µF
VINC13
0.1µF
U2
5
3
R4
0 or 249
C8
0.01µF
R19
10
6
V+
V-
R7
100
+
C10
10µF
V+
R3
499
R8
0
R13
249
J1-2
U1-3
C1-20,31
R1-14,18,19
VR1
Application Note 9707
HI5805EVAL1 Evaluation Board Schematic Diagrams
P1C
D1
D3
D4
D6
D8
D10
CLK
D0 - D11, CLK
3-13
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
(Continued)
P1A
A1
A2
A3
D0 A4
D2
A5
A6
D5
A7
D7
A8
D9
A9
D11
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
E14
E7
FB1
+5VAIN
+
AGND
C46
0.1µF
C35
10µF
+5VA
(OP-AMPS)
E6
FB4
+5VD
+5VDIN
+
DGND
C38
10µF
C45
0.1µF
(COMPARATOR, D-FF VIA LPF)
AGND AND DGND TIE TOGETHER
AT A SINGLE POINT WHERE
THE POWER SUPPLIES
ENTER THE PWB
E2
E4
E8
+5VA1IN
+
AGND
E5
C36
10µF
E3
C47
0.1µF
+
P1
C35-48
FB1-7
E1-14
TP1-3
DGND
C48
0.1µF
TP1
TP2
C39
10µF
E10
C44
0.1µF
FB6
+5VD2IN
+
DGND
TP3
E12
C40
10µF
E13
C43
0.1µF
+5VD2
(+5V TO +3V)
(A/D DVCC3)
FB7
-5VDIN
DGND
+5VD1
(A/D DVCC1 & DVCC2 )
+
C41
10µF
C42
0.1µF
-5VD
(COMPARATOR)
(Continued)
C37
10µF
FB5
+
E11
-5VA
(OP-AMPS)
E9
+5VD1IN
FB3
-5VAIN
AGND
+5VA1
(A/D AVCC)
Application Note 9707
FB2
HI5805EVAL1 Evaluation Board Schematic Diagrams
3-14
E1
Application Note 9707
HI5805EVAL1 Evaluation Board Parts List
REFERENCE
DESIGNATOR
QTY
-
1
Printed Wiring Board
R1
1
56.2Ω, 1/8W
1206 Chip, 1%
R2
1
22.1Ω, 1/8W
1206 Chip, 1%
R3, 5
2
499Ω, 1/8W
1206 Chip, 1%
R4, 10, 11, 12, 13
5
249Ω, 1/8W
1206 Chip, 1%
R8, 15
2
DESCRIPTION
0.0Ω, 1/4W
1206 Chip, 5%
REFERENCE
DESIGNATOR
QTY
DESCRIPTION
C1, 6, 7, 13, 14, 19,
20, 22, 23, 25, 26, 27,
29, 30, 34, 42-48
22
0.1µF Cer Cap, 50WVDC, 10%,
1206 Case, X7R Dielectric
C2, 4, 8, 9, 11, 15, 18
7
0.01µF Cer Cap, 50WVDC, 10%,
1206 Case, X7R Dielectric
C31
1
47pF Cer Cap, 50WVDC, 5%,
1206 Case, NPO Dielectric
FB1-8
8
10µH Ferrite Bead
L1
1
12µH Shielded Chip Inductor,
1812 Case
J1, 2
2
SMA Straight Jack PCB Mount
-
5
Rubber Feet
JP1
1
1x2 Header
JPH1
1
1x2 Header Jumper
R6, 7
2
100Ω, 1/8W
1206 Chip, 1%
R9
1
49.9Ω, 1/8W
1206 Chip, 1%
R16, 17
2
4.99kΩ, 1/8W
1206 Chip, 1%
P2
1
2x13 Header
P1
1
64-Pin Eurocard RT Angle
TP1, 2, 3, 4
4
Test Point
U4
1
Intersil HI5805KCB, 12-Bit
5MSPS A/D Converter
U3
1
Ultrafast Voltage Comparator
U1, 2
2
Op Amp
U5, 6
2
Octal D-Type Flip-Flop
R18, 19
2
10Ω, 1/8W
1206 Chip, 1%
R14
1
A/RΩ, 1/8W
805 Chip, 1%
VR1
1
5kΩ Trim Pot
C3, 5, 10, 12, 16, 17,
21, 24, 28, 33, 35-41
17
10µF Chip Tant Cap, 10WVDC,
20%, EIA Case B
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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