HI5762EVAL2 Evaluation Board User’s Manual TM Application Note January 1999 AN9811 Description adjustable by way of a potentiometer so that the effects of sample clock duty cycle on the HI5762 may be observed. The HI5762EVAL2 evaluation board is made available to allow the circuit designer the ability to evaluate the performance of the Intersil HI5762 monolithic Dual 10-bit 60 MSPS analog-to-digital converter (ADC) with internal voltage reference. As shown in the Evaluation Board Functional Block Diagram, this evaluation board includes sample clock generation circuitry, a single-ended to differential analog input amplifier configuration for both the I and Q channel inputs, an external variable voltage reference and digital data output latches/buffers. The buffered digital data outputs are conveniently provided for easy interfacing to a ribbon connector or logic probes. The I and Q channel analog input signals are also connected through SMA type RF connectors, J1 and J2, and applied to single-ended to differential analog input amplifiers. These inputs are AC-coupled and terminated in 50Ω allowing for connection to most laboratory signal generators. Also, provisions for differential RC lowpass filters are incorporated on the output of the differential amplifiers to limit the broadband noise going into the HI5762 converter. The I and Q channel digital data output latches/buffers consist of a pair of 74FCT2821 D-type flip-flops. The digital data output interface provides both phases of the sampling clock, CLK and CLK, so that the digital data transitions are essentially time aligned with the rising edge of the CLK sampling clock or time aligned with the falling edge of the CLK sampling clock. The sample clock generator circuit accepts the external sampling signal through an SMA type RF connector, J3. This input is AC-coupled and terminated in 50Ω allowing for connection to most laboratory signal generators. In addition, the duty cycle of the clock driving the A/D converter is made Evaluation Board Functional Block Diagram SAMPLE CLOCK INPUT J3 50Ω BIAS TEE +5VD CLK CLOCK OUT CLK J2 Q-CHANNEL ANALOG INPUT (Q_IN) CLK QIIN+ G = +1 50Ω 10 10 QD0-QD9 D Q QIING = -1 VROUT ICL8069 1.2V BANDGAP VOLTAGE REFERENCE I-CHANNEL ANALOG INPUT (I_IN) VRIN +2.5V VAR GAIN HI5762 J1 IIN+ G = +1 50Ω 10 10 ID0-ID9 D Q IING = -1 DGND Q-CHANNEL DIGITAL DATA OUTPUT (QD0 - QD9) I-CHANNEL DIGITAL DATA OUTPUT (ID0 - ID9) AGND +5VD 3-1 +5VA -5VA 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 Application Note 9811 Evaluation Board Layout and Power Supplies The HI5762 evaluation board is a four layer board with a layout optimized for the best performance of the ADC. Included in the application note are electrical schematics of the evaluation board, a component parts list, a component placement layout drawing and reproductions of the various board layers used in the board stack-up. The user should feel free to copy the layout in their application. Refer to the component layout and the evaluation board electrical schematic for the following discussions. The HI5762 monolithic A/D converter has been designed with separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The evaluation board provides separate low impedance analog and digital ground planes on layer 2. Since the analog and digital ground planes are connected together at a single point where the power supplies enter the board, DO NOT tie them together back at the power supplies. The analog and digital power planes are also kept separate on the evaluation board and should be driven by clean linear regulated supplies. The external power supplies are hooked up with the twisted pair wires soldered to the plated through holes marked +5VAIN, +5VAIN1, -5VAIN, +5VDIN, +5VD1IN, +5VD2IN, AGND and DGND. The +5VDIN, +5VD1IN and +5VD2IN are digital supplies and are returned to DGND. The +5VAIN, +5VAIN1 and -5VAIN are the analog supplies and are returned to AGND. Table 1 lists the operational supply voltages, typical current consumption and the evaluation board circuit function being powered. Single supply operation of the converter is possible but the overall performance of the converter may degrade. TABLE 1. HI5762EVAL2 EVALUATION BOARD POWER SUPPLIES POWER SUPPLY NOMINAL VALUE CURRENT (TYP) FUNCTION(S) SUPPLIED +5VAIN 5.0V±5% 51mA Analog Input Op Amps, Reference Voltage Op Amps, Bandgap Reference +5VA1IN 5.0V±5% 73mA A/D AVCC1 and AVCC2 -5VAIN -5.0V±5% 50mA Analog Input Op Amps, Reference Voltage Op Amps +5VDIN 5.0V±5% 15mA Sample Clock Generator and D-FF’s +5VD1IN 5.0V±5% 61mA A/D DVCC1 and DVCC2 +5VD2IN 5.0V±5% or 3.0V±10% 4.5mA A/D DVCC3 3-2 Sample Clock Driver, Timing and I/O In order to ensure rated performance of the HI5762, the duty cycle of the sample clock should be held at 50% ±5%. It must also have low phase noise and operate at standard TTL levels. A CMOS inverter (U7) used as a voltage comparator is provided on the evaluation board to generate the sampling clock for the HI5762 when a sinewave (< 2Vp-p) or squarewave clock is applied to the CLK input (J3) of the evaluation board. A potentiometer (VR2) is provided to allow the user to adjust the duty cycle of the sampling clock to obtain the best performance from the ADC and to allow the user to investigate the effects of expected duty cycle variations on the performance of the converter. The HI5762 clock input trigger level is approximately 1.5V. Therefore, the duty cycle of the sampling clock should be measured at this 1.5V trigger level. U7-2 provides a convenient point to monitor the sample clock duty cycle and make any required adjustments. Figure 2 shows the sample clock and digital data timing relationship for the evaluation board. The data corresponding to a particular sample will be available at the digital data outputs of the HI5762 after the data latency time, tLAT, of 6 sample clock cycles plus the HI5762 digital data output delay, tOD. Table 2 lists the values that can be expected for the indicated timing delays. Refer to the HI5762 data sheet for additional timing information. The sample clock and digital output data signals are made available through two connectors contained on the evaluation board. The line buffering provided by the data output latches allows for driving long leads or analyzer inputs. These data latches are not necessary for the digital output data if the load presented to the converter does not exceed the data sheet load limits of 100mA and 15pF. The P2 I/O connector allows the evaluation board to be interfaced to the DSP evaluation boards available from Intersil. Alternatively, the digital output data and sample clock can also be accessed by clipping the test leads of a logic analyzer or data acquisition system onto the I/O pins of connector header P1. TABLE 2. TIMING SPECIFICATIONS PARAMETER DESCRIPTION TYP tOD HI5762 Digital Output Data Delay 50ns tPD1 U7 Prop Delay 9ns tPD2 U10/11 Prop Delay 4.5ns HI5762 Performance Characterization Dynamic testing is used to evaluate the performance of the HI5762 A/D converter. Among the tests performed are Signal-to-Noise and Distortion Ratio (SINAD), Signal-toNoise Ratio (SNR), Total Harmonic Distortion (THD), Spurious Free Dynamic Range (SFDR) and Intermodulation Distortion (IMD). Application Note 9811 Figure 1 shows the test system used to perform dynamic testing on high-speed ADCs at Intersil. The clock (CLK) and analog input (VIN) signals are sourced from low phase noise HP8662A synthesized signal generators that are phase locked to each other to ensure coherence. The output of the signal generator driving the ADC analog input is bandpass filtered to improve the harmonic distortion of the analog input signal. The comparator on the evaluation board will convert the sine wave CLK input signal to a square wave at TTL logic levels to drive the sample clock input of the HI5762. The ADC data is captured by a logic analyzer and then transferred over the GPIB bus to the PC. The PC has the required software to perform the Fast Fourier Transform (FFT) and do the data analysis. Coherent testing is recommended in order to avoid the inaccuracies of windowing. The sampling frequency and analog input frequency have the following relationship: FI/FS = M/N, where FI is the frequency of the input analog sinusoid, FS is the sampling frequency, N is the number of samples, and M is the number of cycles over which the samples are taken. By making M an integer and odd number (1, 3, 5, ...) the samples are assured of being nonrepetitive. HP8662A HP8662A REF BANDPASS FILTER VIN CLK COMPARATOR I_IN/Q_IN HI5762 CLK I/Q DIGITAL DATA OUTPUT HI5762EVAL2 EVALUATION BOARD 10 DATA ACQUISITION SYSTEM GPIB PC FIGURE 1. HIGH-SPEED A/D PERFORMANCE TEST SYSTEM Refer to the HI5762 data sheet for a complete list of test definitions and the results that can be expected using the evaluation board with the test setup shown. Evaluating the part with a reconstruction DAC is only suggested when doing bandwidth or video testing. SINEWAVE CLK IN (J3) tPD1 HI5762 SAMPLE CLOCK INPUT (CLK AT U7-2) tOD HI5762 DIGITAL DATA OUTPUT (D0 - D13) DATA N-1 DATA N DATA N+1 CLOCK OUT (CLK AT U10,U11, P1-12 AND P2-12) tPD2 DIGITAL DATA OUTPUTS (74FCT2821) DATA N-1 DATA N FIGURE 2. EVALUATION BOARD CLOCK AND DATA TIMING RELATIONSHIPS (TYPICAL) 3-3 Application Note 9811 HI5762EVAL2 Typical Performance (Input Amplitude at -0.5dBFS) 75 9 70 65 8 7 -THD (dB) ENOB (BITS) 60 6 55 50 45 40 5 35 30 4 1 10 100 INPUT FREQUENCY 25 1000 FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT FREQUENCY 1 10 100 INPUT FREQUENCY 1000 FIGURE 4. TOTAL HARMONIC DISTORTION (THD) vs INPUT FREQUENCY 60 85 55 75 -2HD (dB) SINDAD (dB) 50 45 40 65 55 35 45 30 35 25 1 10 100 INPUT FREQUENCY 25 1000 FIGURE 5. SINAD vs INPUT FREQUENCY 1 10 100 INPUT FREQUENCY 1000 FIGURE 6. SECOND HARMONIC DISTORTION (2HD) vs INPUT FREQUENCY 60 85 55 75 -2HD (dB) SNR (dB) 50 45 40 65 55 35 45 30 35 25 1 10 100 INPUT FREQUENCY FIGURE 7. SNR vs INPUT FREQUENCY 3-4 1000 25 1 10 100 INPUT FREQUENCY 1000 FIGURE 8. THIRD HARMONIC DISTORTION (3HD) vs INPUT FREQUENCY Application Note 9811 Appendix A HI5762EVAL2 Board Layout FIGURE 9. HI5762EVAL2 EVALUATION BOARD PARTS LAYOUT (NEAR SIDE) FIGURE 10. HI5762EVAL2 EVALUATION BOARD COMPONENT NEAR SIDE (LAYER 1) 3-5 Application Note 9811 Appendix A HI5762EVAL2 Board Layout (Continued) FIGURE 11. HI5762EVAL2 EVALUATION BOARD GROUND PLANE LAYER (LAYER 2) FIGURE 12. HI5762EVAL2 EVALUATION BOARD POWER PLANE LAYER (LAYER 3) 3-6 Application Note 9811 Appendix A HI5762EVAL2 Board Layout (Continued) FIGURE 13. HI5762EVAL2 EVALUATION BOARD COMPONENT FAR SIDE (LAYER 4) FIGURE 14. HI5762EVAL2 EVALUATION BOARD PARTS LAYOUT (FAR SIDE) 3-7 + C18 10µF FB7 C17 0.1µF C14 0.1µF + C11 10µF R17 4.99K C10 0.1µF +5VD2 CLK4 CLK3 (CLK) (CLK) JP1 C79 0.1µF + C9 10µF C8 0.1µF ID0 - ID9, QD0 - QD9, CLK3 (CLK) U10 C73 0.1µF 2 C6 0.1µF IIN- 35 QIN- IVDC 36 QIN+ 37 AVCC1 39 NC 40 VRIN 23 QD3 24 QD4 25 27 QD5 28 QD6 29 QD7 30 QD8 31 QD9 32 26 CLK DVCC1 AGND DGND 22 7 21 8 20 9 19 10 18 11 12 17 1 16 2 15 3 14 4 5 13 6 12 7 ID3 ID4 6 8 9 11 10 DVCC3 ID2 DGND 9 1 8 IVDC 7 44 6 IVDC 5 IINAGND 43 ID5 ID1 IIN- ID6 ID0 ID7 IIN+ ID8 42 IIN+ HI5762 ID9 41 DVCC2 4 EXT VREF DGND 3 0.1µF C3 QD0 AVCC2 P4 5 QD2 VROUT 4 U1 QD1 2 38 C72 0.1µF QVDC DGND 34 DVCC3 IIN+ AVCC2 AGND 33 3 10 11 +5VA1 12 + C5 10µF C4 0.1µF OE VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 24 23 QD9 22 QD8 21 QD7 20 QD6 19 QD5 Q4 D4 FCT2821 18 Q5 D5 17 Q6 D6 16 Q7 D7 15 Q8 D8 14 Q9 D9 13 CP GND 24 VCC OE 23 D0 Q0 22 D1 Q1 21 D2 Q2 20 D3 Q3 19 D4 Q4 FCT2821 18 Q5 D5 17 Q6 D6 16 Q7 D7 15 Q8 D8 14 Q9 D9 13 CP GND QD4 QD3 QD2 QD1 QD0 P2 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 U11 P1 +5VD2 + C78 10µF +5VD1 C77 0.1µF C2 10µF C1 0.1µF C75 0.1µF + CLK1 (CLK) CLK2 CLK4 CLK3 (CLK) (CLK) (CLK) Application Note 9811 FIGURE 15. A/D CONVERTER AND DIGITAL DATA OUTPUT LATCHES/BUFFERS 3-8 1 +5VA1 Appendix B HI5762EVAL2 Evaluation Board Schematic Diagrams +5VD Application Note 9811 Appendix B HI5762EVAL2 Evaluation Board Schematic Diagrams (Continued) 1 J1 C12 0.1µF 7 3 I_IN NC + +5VA C15 0.1µF 8 V+ R1 56.2 NC NC 2 5 4 IIN+ 6 U3 V- - C17 0.1µF R22 10 HFA1109IB -5VA R6 100 R8 0 C13 0.1µF IVDC R2 499 C25 A/R R5 499 NC - R3 499 + C19 10µF C18 0.1µF 8 7 2 + 6 V- IINC20 0.1µF U4 5 3 C23 0.1µF R23 10 V+ NC NC R4 249 R7 100 +5VA 1 HFA1109IB 4 C21 0.1µF + -5VA C22 10µF FIGURE 16. I CHANNEL ANALOG FRONT END 1 J2 C81 0.1µF 7 3 Q_IN NC + + C64 0.1µF C67 0.1µF V+ 6 NC NC - C63 10µF 8 R24 56.2 2 +5VA QIN+ R29 10 U8 V5 HFA1109IB 4 R31 100 -5VA R25 499 C82 0.1µF +5VA C66 0.1µF 7 NC - R27 499 8 V+ NC NC + R28 249 V5 3 6 U9 R32 100 R30 10 C68 0.1µF HFA1109IB 4 C84 0.1µF + -5VA C85 10µF FIGURE 17. Q CHANNEL ANALOG FRONT END 3-9 QVDC R26 499 1 2 R33 0 C71 A/R C69 0.1µF QIN- Application Note 9811 Appendix B HI5762EVAL2 Evaluation Board Schematic Diagrams (Continued) +5VA +5VA + C37 10µF C38 0.1µF R10 C26 0.1µF 1 4.99K 7 1.2V NC + 3 8 4 8 NC NC D1 ICL8069CCBA - 2 R19 0 V+ V5 6 EXT VREF + U5 C58 0.1µF HFA1109IB 4 C34 0.1µF 2.5V C60 10µF -5VA C30 0.1µF R11 499 R12 249 EXT VREF+ 3(CW) VR1 1.0K 2 EXT VREF 1(CCW) FIGURE 18. EXTERNAL REFERENCE VOLTAGE GENERATION CIRCUIT +5VD + J3 C39 0.1µF C42 10µF U7 C40 0.1µF 13 AC04 12 C41 0.1µF U7 1 14 2 CLK IN R18 56.2 7 L1 1.5µH +5VD VR2 1.0K 1(CCW) 2 R21 100 6 AC04 U7 3 3(CW) C44 0.1µF U7 5 AC04 C43 0.1µF CLK3 (CLK) 4 AC04 U7 11 10 AC04 U7 9 8 AC04 FIGURE 19. SAMPLE CLOCK DRIVER CIRCUIT 3-10 CLK1 (CLK) CLK4 (CLK) CLK2 (CLK) Application Note 9811 Appendix B HI5762EVAL2 Evaluation Board Schematic Diagrams E1 E7 E2 (Continued) E8 FB1 FB4 +5VAIN + AGND E3 +5VA (ANALOG INPUT AND REFERENCE VOLTAGE GENERATOR OP AMPS, BANDGAP REFERENCE) C46 C47 10µF 0.1µF +5VDIN + DGND E4 E9 C52 C53 10µF 0.1µF E10 FB5 FB2 +5VA1IN AGND + C48 C49 10µF 0.1µF +5VA1 (A/D AVCC1 AND AVCC2) +5VD1IN + DGND +5VD (SAMPLE CLOCK GENERATOR, D F-F’s VIA LPF) C54 C55 10µF 0.1µF +5VD1 (A/D DVCC1 AND DVCC2) AGND AND DGND TIE TOGETHER AT A SINGLE POINT WHERE THE POWER SUPPLIES ENTER THE PWB E5 E6 E11 E12 FB3 FB6 -5VAIN AGND + C50 C51 10µF 0.1µF TP1 TP2 -5VA (ANALOG INPUT AND REFERENCE VOLTAGE GENERATOR OP AMPS) TP3 +5VD2IN + DGND TP4 TP5 C56 10µF TP6 DGND TEST POINTS AGND TEST POINTS FIGURE 20. ANALOG AND DIGITAL POWER SUPPLIES 3-11 C57 0.1µF +5VD2 (+5V/+3V) (A/D DVCC3) Application Note 9811 Appendix B HI5762EVAL2 Evaluation Board Schematic Diagrams (Continued) P3C P3A C1 A1 C2 A2 C3 A3 C4 ID1 ID2 C5 C7 ID8 A5 C6 ID4 ID6 A4 ID0 C8 A6 ID3 ID5 A7 A8 ID7 C9 A9 ID9 QD0 C10 A10 C11 A11 C12 A12 C13 A13 C14 C15 QD3 C16 QD5 C17 QD7 C18 QD9 C19 A14 QD1 QD2 QD4 QD6 QD8 A15 A16 A17 A18 A19 CLK3 (CLK) C20 A20 C21 A21 C22 A22 C23 A23 C24 A24 C25 A25 C26 A26 C27 A27 C28 A28 C29 A29 C30 A30 C31 A31 C32 A32 ID0 - ID9, QD0 - QD9, CLK3 (CLK) FIGURE 21. 96 PIN I/O CONNECTOR 3-12 Application Note 9811 Appendix C HI5762EVAL2 Evaluation Board Parts List REFERENCE DESIGNATOR QTY - 1 Printed Wiring Board R2, 3, 5, 11, 25, 26, 27 7 499Ω, 1/10W 805 Chip, 1% R1, 18, 24 3 56.2Ω, 1/10W 805 Chip, 1% R22, 23, 29, 30 4 10Ω, 1/10W 805 Chip, 1% R6, 7, 21, 31, 32 5 100Ω, 1/10W 805 Chip, 1% R13, 14, 15, 16 4 22.1Ω, 1/10W 805 Chip, 1% R8, 19, 33 3 0.0Ω, 1/4W 805 Chip, 5% R10, 17 2 4.99kΩ, 1/10W 805 Chip, 1% R4, 12, 28 3 249Ω, 1/10W 805 Chip, 1% VR1, 2 2 1kΩ Trim Pot C2, 5, 9, 11, 19, 22, 37, 42, 46, 48, 50,52, 54, 56, 60, 63, 78, 85 18 10µF Chip Tant Cap, 10WVDC, 20%, EIA Case B C1, 3, 4, 6, 8, 10, 12, 13, 15, 17, 18, 20, 21, 23, 26, 30, 34, 38, 39, 40, 41, 43, 44, 47, 49, 51, 53, 55, 57, 58, 64, 66, 67, 68, 69, 72, 73, 75, 77, 79, 81, 82, 84 43 0.1µF Cer Cap, 50WVDC, 10%, 805 Case, Y5V Dielectric C25, 71 2 A/R pF Cer Cap, 50WVDC, 10%, 805 Case L1 1 1.5µH Chip Inductor, 1210 Case FB1-7 7 10µH Ferrite Bead J1, 2, 3 3 SMA Straight Jack PCB Mount - 6 Protective Bumper JP1 1 1x2 Header JPH1 1 1x2 Header Jumper P4 1 1x3 2mm Header PH104 1 1x3 2mm Header Jumper P1, 2 2 2x13 Heade TP1, 2, 3, 4, 5, 6 6 Test Point U1 1 Intersil HI5762IN Dual 10-Bi,t 60 MSPS A/D Converter with Internal Voltage Reference U3, 4, 5, 8, 9 5 Intersil HFA1109IB 450MHz, Low Power, Current Feedback Video Operational Amplifier U10, 11 2 Intersil CD74FCT2821BTM10-Bit Fast CMOS D-type Flip-flop U7 1 Intersil CD74HC04M High Speed CMOS Logic Hex Inverter D1 1 Intersil ICL8069CCBA Low Voltage Bandgap Reference P3 1 64-Pin Eurocard RT Angle Receptacle 3-13 DESCRIPTION Application Note 9811 Appendix D HI5762 A/D Theory of Operation The HI5762 is a dual 10-bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 22 depicts the circuit for the front end differential-in-differentialout sample-and-hold (S/H) amplifiers. The switches are controlled by an internal sampling clock which is a nonoverlapping two phase signal, Φ1 and Φ2 , derived from the master sampling clock. During the sampling phase, Φ1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of Φ1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, Φ2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The front end sample-and-hold output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sampleand-hold function but will also convert a single-ended input to a fully-differential output for the converter core. During the sampling phase, the I/QIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 250MHz for the converter. Φ1 I/QIN+ Φ1 Φ1 Φ1 CS Φ2 I/QIN- CH -+ VOUT+ +- VOUT- CS Φ1 CH Φ1 controlled by the internal sampling clock. The function of the digital delay line is to time align the digital outputs of the eight identical two-bit subconverter stages with the corresponding output of the ninth stage flash converter before applying the eighteen bit result to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final ten bit digital data output of the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus following the 6th cycle of the clock after the analog sample is taken (see the timing diagram in Figure 24). This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital output data is provided in offset binary format. Internal Reference Voltage Output, VREFOUT The HI5762 is equipped with an internal reference voltage generator, therefore, no external reference voltage is required. VROUT must be connected to VRIN when using the internal reference voltage. An internal band-gap reference voltage followed by an amplifier/buffer generates the precision +2.5V reference voltage used by the converter. A band-gap reference circuit is used to generate a precision +1.25V internal reference voltage. This voltage is then amplified by a wideband uncompensated operational amplifier connected in a gain-of-two configuration. An external, user-supplied, 0.1µF capacitor connected from the VROUT output pin to analog ground is used to set the dominant pole and to maintain the stability of the operational amplifier. Reference Voltage Input, VREFIN FIGURE 22. ANALOG INPUT SAMPLE-AND-HOLD As illustrated in the functional block diagram and the timing diagram in Figures 23 and 24, eight identical pipeline subconverter stages, each containing a two-bit flash converter and a two-bit multiplying digital-to-analog converter, follow the S/H circuit with the ninth stage being a two bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. The output of each of the eight identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is 3-14 The HI5762 is designed to accept a +2.5V reference voltage source at the VRIN input pin. Typical operation of the converter requires VRIN to be set at +2.5V. The HI5762 is tested with VRIN connected to VROUT yielding a fully differential analog input voltage range of ±0.5V. The user does have the option of supplying an external +2.5V reference voltage. As a result of the high input impedance presented at the VRIN input pin, 1.25kΩ typically, the external reference voltage being used is only required to source 2mA of reference input current. In the situation where an external reference voltage will be used an external 0.1µF capacitor must be connected from the VROUT output pin to analog ground in order to maintain the stability of the internal operational amplifier. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, VRIN . Application Note 9811 Appendix D HI5762 A/D Theory of Operation I/QIN- (Continued) I/QVDC BIAS I/QIN+ S/H STAGE 1 2-BIT FLASH 2-BIT DAC + ∑ DVCC3 X2 I/QD9 (MSB) I/QD8 I/QD7 I/QD6 DIGITAL DELAY AND DIGITAL ERROR CORRECTION STAGE 8 I/QD5 I/QD4 I/QD3 2-BIT FLASH 2-BIT DAC I/QD2 I/QD1 + ∑ I/QD0 (LSB) - X2 STAGE 9 2-BIT FLASH I OR Q CHANNEL VREFOUT VREFIN CLOCK REFERENCE AVCC1,2 AGND DVCC1,2 DGND FIGURE 23. HI5762 FUNCTIONAL BLOCK DIAGRAM 3-15 CLK Application Note 9811 Appendix D HI5762 A/D Theory of Operation (Continued) ANALOG INPUT CLOCK INPUT SN - 1 HN - 1 SN HN SN + 1 H N + 1 SN + 2 SN + 5 HN + 5 SN + 6 H N + 6 SN + 7 H N + 7 SN + 8 HN + 8 INPUT S/H 1ST STAGE 2ND STAGE B1 , N - 1 B2 , N - 2 9TH STAGE B1 , N B2 , N - 1 B9 , N - 5 DATA OUTPUT B1 , N + 1 B1 , N + 5 B2 , N + 4 B2 , N B9 , N - 4 DN - 6 B1 , N + 4 B9 , N DN - 5 B2 , N + 5 B9 , N + 1 DN - 1 tLAT NOTES: 1. SN: N-th sampling period. 2. HN: N-th holding period. 3. BM, N: M-th stage digital output corresponding to the N-th sampled input. 4. DN: Final data output corresponding to N-th sampled input. FIGURE 24. HI5762 INTERNAL CIRCUIT TIMING 3-16 B1 , N + 6 B1 , N + 7 B2 , N + 6 B9 , N + 2 DN B9 , N + 3 DN + 1 DN + 2 Application Note 9811 Appendix E HI5762 Pin Descriptions PIN NO. NAME 1 AGND 2 AVCC2 3 DESCRIPTION PIN NO. NAME Analog Ground 23 QD3 Q-Channel, Data Bit 3 Output Analog Supply (+5.0V) 24 QD4 Q-Channel, Data Bit 4 Output ID9 I-Channel, Data Bit 9 Output (MSB) 25 DGND Digital Ground 4 ID8 I-Channel, Data Bit 8 Output 26 DVCC3 5 ID7 I-Channel, Data Bit 7 Output Digital Output Supply (+3.0V or +5.0V) 6 ID6 I-Channel Data Bit 6 Output 27 QD5 Q-Channel, Data Bit 5 Output 7 ID5 I-Channel, Data Bit 5 Output 28 QD6 Q-Channel, Data Bit 6 Output 8 DVCC3 29 QD7 Q-Channel, Data Bit 7 Output 30 QD8 Q-Channel, Data Bit 8 Output 31 QD9 Q-Channel, Data Bit 9 Output (MSB) 32 AVCC2 Analog Supply (+5.0V) 33 AGND Analog Ground 34 QVDC Q-Channel DC Bias Voltage Output 35 QIN- Q-Channel Negative Analog Input 36 QIN+ Q-Channel Positive Analog Input 37 AVCC1 Analog Supply (+5.0V) 38 VROUT +2.5V Reference Voltage Output 39 NC 40 VRIN +2.5V Reference Voltage Input 41 AGND Analog Ground 42 IIN+ I-Channel Positive Analog Input 43 IIN- I-Channel Negative Analog Input 44 IVDC Digital Output Supply (+3.0V or +5.0V) 9 DGND Digital Ground 10 ID4 I-Channel, Data Bit 4 Output 11 ID3 I-Channel, Data Bit 3 Output 12 ID2 I-Channel, Data Bit 2 Output 13 ID1 I-Channel, Data Bit 1 Output 14 ID0 I-Channel, Data Bit 0 Output (LSB) 15 DGND Digital Ground 16 DVCC1 Digital Supply (+5.0V) 17 CLK 18 DVCC2 Digital Supply (+5.0V) 19 DGND Digital Ground 20 QD0 Q-Channel, Data Bit 0 Output (LSB) 21 QD1 Q-Channel, Data Bit 1 Output 22 QD2 Q-Channel, Data Bit 2 Output Sample Clock Input DESCRIPTION No Connect I-Channel DC Bias Voltage Output All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 3-17