KDC5612EVAL Bead 100pF 100pF GND GND GND L25 BLM18AG102SN1D Vcm Vcm_out AINN AINP 8 9 10 11 12 13 14 15 16 17 18 R32 DNP anlg_1.8V HI= clk_div4 LO= clk_div2 Ft=clk_div1 R28 DNP OUTFMT R14 1K HI=2mA LVDS LO= LVCMOS Ft= 3mA LVDS output_mode R30 DNP anlg_1.8V ORP ORN D13P D13N D12P D12N D11P D11N VCM CLKDIV DNC DNC pin36 OVDD C29 0.1uF pin27 OVDD C25 0.1uF pin56 OVDD C17 0.1uF SDO C46 C45 100pF CSB SCLK 100pF OVDD DGND 56 55 OVDD OVSS 65 64 63 62 61 60 59 58 57 ORP ORN D13P D13N D12P D12N D11P D11N RLVDS OVSS D7P D7N D6P D6N D5P D5N D4P D4N 54 53 52 51 50 49 D10P D10N D9P D9N D8P D8N 48 47 CLKOUTP CLKOUTN 46 45 44 43 42 41 40 39 38 37 10K DGND R53 D7P D7N D6P D6N D5P D5N D4P D4N Under DUT. L15 bead L16 bead L17 bead L18 bead HI= Nap LO = Normal Ft= Sleep R33 DNP nap_sleep_normal clkdivn R29 DNP OVSS CLKOUTP CLKOUTN BINP BINN AVSS AVSS AVSS AINN AINP AVDD 19 20 21 R15 DNP anlg_1.8V SDIO SCLK CSB SDO AVDD AVSS clk_inp clk_inn HI= Gray_Code LO= Unsign Ft=Twos_Comp D10P D10N D9P D9N D8P D8N DNC DNC DNC DNC AVDD CLKP CLKN clkdivn anlg_1.8V 100pF SDIO BINP BINN 6 7 C44 100pF AVDD GND AVDD DGND C43 SCL SDA OVDD L12 C12 OVDD 36 100pF C11 NC NC NC NC D2N D2P D3N D3P 100pF 2 3 4 5 Bead 28 29 30 31 32 33 34 35 C9 U1 KAD5612P D0N D0P D1N D1P D2N D2P D3N D3P L11 C8 1 RESETN OVSS OVDD AVDD 25 DGND 26 OVDD 27 SDA RESETN Bead 69 68 67 66 L2 SDIO SCLK CSB SDO SD0 OUTMODE NAPSLP AVDD SCL GND AVDD OUTFMT Bead output_mode 22 nap_sleep_normal 23 AVDD 24 L3 C14 100pF GND SC0 pin70 pin23 C50 100pF OUTFMT pin22 C49 0.1uF 72 71 70 C48 0.1uF nap_sleep_normal pin16 C47 10000pF output_mode pin15 clkdivn Vcm_out pin24 C28 0.1uF 0 C27 0.1uF AVDD pin19 AVDD C21 0.1uF EP C18 0.1uF AVSS AVDD OUTFMT C16 0.1uF pin6 AVDD pin1 AVDD pin71 AVDD KDC5612EVAL Schematics R34 1K INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOS Title KDC5612P Size FIGURE 1. ADC, MODE PINS AND POWER SUPPLY BYPASS 1 Number page1 R KDC5612EVAL KDC5612EVAL Schematics (Continued) J3 C39 SMA ADT1-1WT ADT1-1WT 3 T6 3 T7 4 4 DNP R18 F_VinBm BINP J5 coplanar wave guide. 0.01uF 2 6 1 6 DNP R20 F_VinBp R58 DNP 2 1 BINN R51 L23 DNP C41 DNP C42 C40 DNP Vcm R16 L5 270nH DNP C10 1 6 coplanar wave guide. 0.01uF C13 0.1uF 4 DNP R26 AINP 3 4 T1 L4 ADTL1-12+ Bead L6 270nH DNP T2 ADTL1-12+ Tx_VinBp C54 DNP 0.1uF Tx_VinAm R22 0 L9 Bead J4 6 1 6 3 4 3 4 DNP C24 coplanar wave guide. 0.01uF R17 T3 L10 ADTL1-12+ Bead BINN L8 270nH DNP T4 ADTL1-12+ Tx_VinAp L21 BLM18AG102SN1D L20 1uH C63 0.1uF C15 0.01uF AINP L22 BLM18AG102SN1D C64 0.1uF C20 0.01uF C22 0.01uF C26 0.01uF Vcm EP GND C61 0.01uF IN VT VREFAC IN Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 49.9 49.9 49.9 49.9 49.9 49.9 49.9 R62 R60 R59 R63 R66 "CLOCK IN" SMA TC4-1W C36 C32 T5 J6 DNP C52 clk_inp coplanar wave guide. 1000pF 1000pF C34 R31 200 clk_inp C31 1000pF R57 100 clk_inn DNP C53 1000pF clk_inn INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGRE Title 0 13 1000pF C62 12 11 10 9 15 16 1 2 3 4 5 6 R61 NB6L14MMNG U5 49.9 8 7 14 C58 1000pF EN Vcc Vcc C60 1000pF R65 anlg_3.3V C59 0.1uF R64 anlg_3.3V SMA R23 Vcm Vcm "CLOCK IN" J7 R27 26.1 0 Vcm C57 0.1uF R25 26.1 C33 SMA R21 26.1 1 0.1uF 0 L14 1uH AINN L7 270nH DNP C30 R19 26.1 DNP C19 3 flux_VinAp C55 DNP BINP 0 6 6 L24 DNP C51 L19 1uH 0.1uF 1 AINN Vcm T_VinBm J2 1 0 L1 Bead SMA DNP R24 2 6 Vcm L13 1uH F_VinAm R55 0 Vcm 4 coplanar wave guide. 2 0.01uF 1 ADT1-1WT 3 T9 4 C56 SMA R49 DNP ADT1-1WT 3 T8 KDC5612P Size B FIGURE 2. CLOCK AND ANALOG INPUTS 2 Number page2 Revision KDC5612EVAL KDC5612EVAL Schematics (Continued) DGND GND AVDD AVDD 33uF anlg_1.8V C35 C_vdd3_anlg anlg_3.3V Anlg_5V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 VCC VCC 33uF C7 dig_1.8V VCC ORP ORN dig_1.8V dig_1.8V Dig_5V C1 C37 0.1uF D13P D13N C4 0.1uF 33uF C38 0.1uF C5 0.1uF dig_1.8V dig_1.8V dig_1.8V R45 D12P D12N C3 0.1uF ID EEPROM dig_1.8V dig_1.8V SCLK SDO R5 1K R6 1K SDIO CSB R7 1K D4P D4N D3P D3N TCK TMS TDI IO(1) VCCIO1 I/O(1) I/O(1) GND I/O(1) I/O(1) I/O(GCK) 11 TCK 10 TMS 9 TDI 8 R9 1K 7 VCC 6 R10 1K 5 R11 1K 4 3 R12 1K 2 R13 1K 1 CPLD SPARE1 R40 10K SPARE EEPROM U2 1 2 3 4 A0 A1 A2 Vss Vcc WP SCL SDA 8 7 6 DNP 5 DNP WP_2V R39 R38 R35 4.7K IO(2) TDO GND VCCIO2 IO(2) IO(2) IO(2) IO_GLB_S/R IO_GOE IO_GOE IO_GOE dig_1.8V C2 0.1uF SC0 SD0 24AA64-I/SN PC3 IO_GOE VAUX IO(2) IO(2) IO(2) IO(1) IO(1) IO(1) IO(1) IO(GCK) IO(GCK) D2P D2N 23 24 25 26 27 28 29 30 31 32 33 U4 XC2C64A-6VQG44C 4.7K R1 1K TDO D5P D5N WP_2V SC2 SD2 R37 D6P D6N 8 7 6 5 Vcc WP SCL SDA dig_1.8V 22 21 20 19 18 17 16 15 14 13 12 D7P D7N A0 A1 A2 Vss 24AA32A-I/SN IO(2) IO(2) IO(2) IO(2) I(2) GND IO(1) VCC IO(1) IO(1) IO(1) CLKOUTP CLKOUTN 1 2 3 4 1K R8 dig_1.8V 1K R47 1K R46 WP D8P D8N 1K D9P D9N R3 SPI_CONF 1K R41 RESETN 4.7K R43 PORn_ExtResetn_fpga 1K R4 dig_1.8V D10P D10N U3 PC1 4.7K D11P D11N R2 D1P D1N 34 35 36 37 38 39 40 41 42 43 44 D0P D0N PC6 PC7 PC0 daughter card detected PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC4 PC5 PC2 WP SPI_master_drive CPLD SPARE1 SCLK_3V CSB_3V MISO_3V MOSI_3V R36 1K VCC R42 1K R44 1K WP_2V SCLK_3V CSB_3V SPI_master_drive 1K R48 MISO_3V MOSI_3V 33uF C6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 4.7K dig_1.8V OVDD OVDD SD0 SC0 SD2 SC2 PORn_ExtResetn_fpga JTAG connector Programing PLCD J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DGND GND VCC TMS TCK TDO TDI DNP 2MM HDR 14P SMT INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEM Title KDC5612P Size J8 B 53475-1879 Date: File: FIGURE 3. INPUT/OUTPUT MEZZANINE CONNECTOR 3 Number Revision page3 1/30/2009 \\..\KDC5612-25_IO.SchDoc Sheet of Drawn By: KDC5612EVAL KDC5612EVAL Layers FIGURE 4. PRIMARY SIDE 4 KDC5612EVAL KDC5612EVAL Layers (Continued) FIGURE 5. GND PLANE 1 5 KDC5612EVAL KDC5612EVAL Layers (Continued) FIGURE 6. PWR PLANE 6 KDC5612EVAL KDC5612EVAL Layers (Continued) FIGURE 7. INTERNAL SIGNAL 7 KDC5612EVAL KDC5612EVAL Layers (Continued) FIGURE 8. GND PLANE 2 8 KDC5612EVAL KDC5612EVAL Layers (Continued) FIGURE 9. SECONDARY SIDE 9 KDC5612EVAL KDC5612EVAL Layers (Continued) FIGURE 10. SECONDARY SIDE SILKSCREEN 10 KDC5612EVAL KDC5612EVAL Layers (Continued) FIGURE 11. LAYER - PRIMARY SIDE SILKSCREEEN Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 11