isla216ir72ev1z schem layers

1
1
ISLA216IR72EV1Z
1 ADC Input FS - Neglects 3-4dB Input
Network Loss
19
20
21
AVDD
K=15uV
R=49.9K
OVDD
DGND
lvds_2
lvds_n2
lvds_3
lvds_n3
lvds_4
lvds_n4
62
61
60
59
58
57
56
55
OVDD
OVSS
DGND
lvds_1
lvds_n1
64
63
D0P
D0N
D1P
D1N
D2P
D2N
48
47
CSB
SCLK
C37
C36
100pF
SDIO
clk_out
clk_outn
10K
46
45 DGND
44
43
42
41
40
39
38
37
ISL214P50IRZ or
ISLA214P25IRZ or
ISLA216P25IRZ
lvds_5
lvds_n5
lvds_6
lvds_n6
lvds_7
lvds_n7
R46
lvds_8
lvds_n8
lvds_9
lvds_n9
lvds_10
lvds_n10
lvds_11
lvds_n11
Under DUT.
L15
bead
U5
anlg_3.3V
Temp=(V-RK)/Rm
m=9uV/160C
65
SDIO
SCLK
CSB
SDO
RESETN
Temp=(I-K)/m
or
ORP
ORN
AVDD
69
68
67
66
CLKDIV
IPTAT
DNC
AVDD
AVDD
AVDD
ExtResetn_PORn 18
D6P
D6N
D7P
D7N
D8P
D8N
D9P
D9N
54
53
52
51
50
49
D11N
D11P
D10N
D10P
15
16
17
RLVDS
OVSS
AVSS
AVDD
AVSS
33
34
35
36
clkdivn
IPTAT
spare
12
13
14
lvds_n13
lvds_13
lvds_n12
lvds_12
Bead
GND
AVDD
GND
OVDD
L2
ExtResetn_PORn
32
Bead
CLKOUTP
CLKOUTN
VINP
VINP
OVDD
L1
VINN
VINN
D13N
D13P
D12N
D12P
ExtResetn
10
11
28
29
30
31
VINP
lvds_n15
lvds_15
lvds_n14
lvds_14
8
9
VINN
OVSS
OVDD
Header 2x2
AVSS
AVDD
AVSS
CLKDIVRSTP
CLKDIVRSTN
5
6
7
R23
DNP
D3P
D3N
D4P
D4N
D5P
D5N
26
27
GND
AVDD
GND
clkdivn
2
4
DNC
DNC
NAPSLP
VCM
DGND
OVDD
1
3
1
2
3
4
CLKDIV_RESETP 24
CLKDIV_RESETN 25
JP2
SDA
SCL
NAP_SLEEP
Vcm
CLKP
CLKN
R22
DNP
22
23
HI= clk_div4
Float=clk_div1
LO= clk_div2
anlg_1.8V
U1 (ADC) = 72pin QFN
U1
D14
ISLA216IR72EV1Z
anlg_1.8V
OVSS
EP
Header 2x2
CLKP
CLKN
R28
DNP
SDIO
SCLK
CSB
SDO
NAP_SLEEP
2
4
AVDD
AVDD
AVDD
R26
DNP
JP1
72
71
70
anlg_1.8V
1
3
R61
1K
100pF
Bead
100pF
L12
C35
Bead
pin62
L14
C43
0.1uF
pin32
Bead
OVDD
L11
C27
Bead
0.1uF
SDL2
L13
pin27
SCL2
Bead
OVDD
Bead
L10
OVDD
L8
SD2
C24
SC2
SDA
C14
pin16
clkdivn
pin3
NAP_SLEEP
pin4
SCL
Bead
GND
R60
1K
HI= Nap
Float= Sleep
LO = Normal_Op
C45
100pF
Bead
L3
0
2
anlg_1.8V
C42
0.1uF
L4
SD0
0.1uF
C26
0.1uF
SC0
0.1uF
C22
0.1uF
Vcm
pin70
pin21
C20
0.1uF
AVDD
pin13
C15
0.1uF
AVDD
AVDD
pin6
AVDD
ISLA216IR72EV1Z Schematics
C8
10uF
C25
0.1uF
SCL2
SDL2
6
8
7
10
9
VDD
SCL
SDA
ADR1
ADR0
CH1+
CH1CH2+
CH2VSS
MCP3423T-E/UN
spare
1
2
4
5
3
L16
bead
IPTAT
R24
DNP
L17
bead
R25
DNP
L18
bead
INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGR
Title
Size
FIGURE 1. ADC
ADC
Number
page2
Revision
ISLA216IR72EV1Z Schematics
Sampling Clock
Populate
Depopulate
LVCMOS
C28, C29
C38, C39
LVDS
C38, C39
C28, C29
C28
T3
CLKN
3
1000pF
R27
200
2
4
50 Ohms coplanar
SMA
C29
1000pF
CLKP
1
TC4-19G2+
4:1 sec/pri
1000pF
DNP AT2,T1,T2
C16
1000pF
16
J5
SMA
1
2
"CLOCK IN"
"MAX=14 dBm"
3
4
0.01uF
C46
Vref
Q
Q
VT
D
D
NC
NC
J2
NC
NC
NC
NC
NC
C38
DNP
R63
0
12
11
VINP
AT2
3 dB
PAT-3
1
C21
50 Ohms coplanar
3
1 T1
6
3
R53
DNP
T2
L9
1uH
R17
DNP
SMA
0.1uF
CLKN
R21
13
6
4
R64
10
0
9
6
5
EP
R19
13
C17
CLKP
R43
100
R47
100
4
3
ADTL1-12+
1:1 sec/pri
0.1uF
C39
DNP
1
L7
1uH
R16
DNP
TC4-19G2+
4:1 sec/pri
C55
2pF
C9
5.6pF
2
C54
2pF
R45
0
R52
DNP
VINN
Vcm
C56
0.1uF
7
14
C47
0.1uF
Vee
Vee
15
Optional Path
C19
0.1uF
U6
ADCLK905
Vcc
Vcc
13
8
C13
1000pF
2
4
C57
0.1uF
anlg_3.3V
Pin6= Primary Dot
Vcm
C40
0.1uF
anlg_3.3V
anlg_3.3V
R18
0
T4
ADTL1-12+
1:1 sec/pri
C12
0.1uF
1
6
AT1
50 Ohms coplanar C41
3
3
4
3
6
L5
DNP
4
L6
DNP
"Analog Input"
C48
1uF
C50
1000pF
C49
1000pF
C51
1uF
5 2
1
2
"Synch_Reset"
"MAX=14 dBm"
0.01uF
C52
R100
1K
3
4
C53
0.1uF
Vref
VT
D
D
NC
NC
1
U7
ADCLK905
Q
Q
Vee
Vee
15
16
SMA
NC
NC
NC
NC
NC
12
11
10
9
6
5
EP
1
=Value
VINP
2
4
Vcc
Vcc
13
8
J3
J7
SMA
VINN
T5
TX-2-5-1
R48
54.9
PAT-3
3 dB
CLKDIV_RESETP
CLKDIV_RESETN
R20
0
Vcm
C18
0.1uF
R49
54.9
R50
95
R51
95
R100 was added to rev B pcb
Default Path
INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREE
Title
Rev B pcb also Cut trace at C53
Analog Front End, Clock, Sync Reset
Size
B
Date:
File:
FIGURE 2. ANALOG FRONT END, CLOCK, SYNC RESET
Number
Revision
page3
6-Apr-2011
Sheet of
C:\Documents and Settings\GHENDRIC\My
Drawn
Documents\D14
pcbs\Si
By:
ISLA216IR72EV1Z
anlg_3.3V
7
14
3
C30
0.01uF
6
"Clock
J4 Input"
C32
(Continued)
ISLA216IR72EV1Z Schematics
C31
33uF
anlg_1.8V
C_vdd3_anlg
anlg_3.3V
Anlg_5V
4.7K
4.7K
R58
R59
R2
4.7K
4.7K
R37
SDO
ExtResetn
PORn_ExtResetn_fpga
R39
DNP
DNP
R41
DNP
4.7K
22
21
20
19
18
17
16
15
14
13
12
clk_out
clk_outn
R40
DNP
R14
Resetn
lvds_6
lvds_n6
4.7K
S1
Tachtile Switch B3FS
4.7K
ExtResetn_sense R3
Resetn
R35
R55
4.7K
lvds_5
lvds_n5
R57
DNP
DNP
dig_1.8V
lvds_4
lvds_n4
PORn_ExtResetn_fpga
1K R4
DGND
config_spare0
dig_1.8V
config_spare1
config_spare2
config_spare3
lvds_3
lvds_n3
R56
config_spare0
config_spare1
config_spare2
config_spare3
ExtResetn
lvds_2
lvds_n2
R15
33uF
dig_1.8V
dig_1.8V
VCC
C1
dig_1.8V
VCC
dig_1.8V
0.1uF
C33
lvds_1
lvds_n1
0.1uF
lvds_0
lvds_n0
C4
33uF
C7
VCC
VCC
C3
0.1uF
U4
ID EEPROM
XC2C64A-6VQG44C
U3
IO(2)
IO(2)
IO(2)
IO(2)
I(2)
GND
IO(1)
VCC
IO(1)
IO(1)
IO(1)
23
TDO24
25
dig_1.8V
26
SCLK
27
SDO
28
R5
1K 29
R6
1K 30
SDIO
31
CSB
32
R7
1K 33
lvds_9
lvds_n9
lvds_10
lvds_n10
lvds_11
lvds_n11
TCK
TMS
TDI
IO(1)
VCCIO1
I/O(1)
I/O(1)
GND
I/O(1)
I/O(1)
I/O(GCK)
lvds_13
lvds_n13
MOSI_EN_3V
CPLD SPARE1
SCLK_3V
CSB_3V
MISO_3V
MOSI_3V
PC4
PC5
PC2
WP
PC0 daughter card detected
PC1
PC2
PC3
PC4
PC5
PC6
PC7
Vcc
WP
SCL
SDA
R12
1K
R13
1K
CPLD SPARE1
8
7
6
5
WP
SC2
SD2
VCC
C2
0.1uF
SPARE EEPROM
U2
1
2
3
4
JTAG connector
PLCD Programing
J1
1
3
5
7
9
11
13
PC6
PC7
lvds_15
lvds_n15
A0
A1
A2
Vss
24FC128-I/SN
34
35
36
37
38
39
40
41
42
43
44
lvds_14
lvds_n14
2
4
6
8
10
12
14
VCC
TMS
TCK
TDO
TDI
A0
A1
A2
Vss
Vcc
WP
SCL
SDA
VCC
8
7
6 R33
5 R32
WP
0
0
SC0
SD0
24FC128-I/SN
2MM HDR 14P SMT
SD0
SC0
SD2
SC2
PORn_ExtResetn_fpga
MH1
DGND
GND
1
2
3
4
TCK
TMS
TDI
R9
1K
VCC
R10
1K
R11
1K
IO_GOE
VAUX
IO(2)
IO(2)
IO(2)
IO(1)
IO(1)
IO(1)
IO(1)
IO(GCK)
IO(GCK)
lvds_12
lvds_n12
IO(2)
TDO
GND
VCCIO2
IO(2)
IO(2)
IO(2)
IO_GLB_S/R
IO_GOE
IO_GOE
IO_GOE
11
10
9
8
7
6
5
4
3
2
1
4.7K
4.7K
1K
R31
R29
R1
10K
lvds_8
lvds_n8
R34
lvds_7
lvds_n7
ISLA216IR72EV1Z
AVDD
C60
DNP
VCC
R30
1K
VCC
R36
1K
R38
1K
R8
1K
SCLK_3V
CSB_3V
MOSI_EN_3V
R42
1K
MISO_3V
MOSI_3V
4
DGND
GND
AVDD
Dig_5V
0.1uF
33uF
C6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
C5
C59
DNP
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
VCC
0.1uF
OVDD
OVDD
C34
J6
dig_1.8V
(Continued)
MH2
MH3
MH4
Tooling Hole Tooling Hole Tooling Hole Tooling Hole
INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NOND
Title
IO Level Translator ID PROM
Size
55091-1875
B
Date:
File:
FIGURE 3. IO LEVEL TRANSLATOR ID PROM
Number
R
page4
6-Apr-2011
Sheet of
C:\Documents and Settings\GHENDRIC\My
Drawn
Documents\D
By:
ISLA216IR72EV1Z
ISLA216IR72EV1Z Layers
FIGURE 4. TOP SILKSCREEN
5
ISLA216IR72EV1Z
ISLA216IR72EV1Z Layers
(Continued)
FIGURE 5. TOP LAYER ROUTING
6
ISLA216IR72EV1Z
ISLA216IR72EV1Z Layers
(Continued)
FIGURE 6. SPLIT GROUND PLANE
7
ISLA216IR72EV1Z
ISLA216IR72EV1Z Layers
(Continued)
FIGURE 7. SPLIT POWER PLANE
8
ISLA216IR72EV1Z
ISLA216IR72EV1Z Layers
(Continued)
FIGURE 8. INNER LAYER ROUTING
9
ISLA216IR72EV1Z
ISLA216IR72EV1Z Layers
(Continued)
FIGURE 9. 2ND SPLIT GROUND PLANE
10
ISLA216IR72EV1Z
ISLA216IR72EV1Z Layers
(Continued)
W
FIGURE 10. BOTTOM LAYER ROUTING
11
ISLA216IR72EV1Z
ISLA216IR72EV1Z Layers
(Continued)
FIGURE 11. BOTTOM SILKSCREEN
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
12