KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Schematics Vcm C22 0.1uF C38 0.1uF C39 100pF SDO SCLK 100pF 100pF SDIO 100pF pin37 pin20 C23 CSB C34 C19 0.1uF C33 C17 0.1uF C32 C12 0.1uF DNP DNP C36 100pF DNP R38 C31 Vcm 0.1uF 0 OVDD pin10 pin47 pin9 R37 C13 VinIp pin1 DNP R18 nap_sleep_normal flux_VinIp Vcm 6 AVDD 1 AVDD 50 Ohms differential routing 2 6 pin47 2 1 AVDD R41 DNP 10000pF OVDD VinIm 0.1uF DNP flux_VinIm R16 4 50 Ohms Coplanar Waveguide SMA pin16 C37 ADT1-1WT 3 T5 4 AVDD J3 ADT1-1WT 3 T4 C35 C14 L5 0.1uF Tx_VinIp R19 28 AVDD R14 SCL SDA VinIp GND 0 VinIm VinIp L8 1uH 0 R39 Vcm C16 0.1uF 6 7 GND AVDD C21 0.1uF Vcm Vcm C46 10000uF EP GND 220pF C47 SMA IN VT VREFAC IN DNP R49 49.9 R45 49.9 R46 49.9 R44 49.9 R43 49.9 R47 49.9 R50 49.9 U5 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 15 16 1 2 3 4 5 6 DNP C40 clk_inp R42 100 OVDD ORP ORN D6P D6N 41 40 39 38 37 SDIO SCLK CSB SDO DGND CLKOUTP CLKOUTN VINN VINP RLVDS AVSS AVDD VCM DNC AVSS OVSS D3P D3N D2P D2N 36 35 34 33 32 31 30 29 28 27 26 25 D9P D9N D8P D8N CLKOUTP CLKOUTN 10K R40 DGND D7P D7N D6P D6N DNP C41 clk_inn 0 13 "CLOCK IN" J5 12 11 10 9 R48 49.9 D5P D5N D4P D4N AVDD clk_inp clk_inn nap_sleep_normal AVDD C43 1000pF 8 9 10 11 12 AVDD DNC DNC DNC AVSS 13 14 15 16 17 anlg_3.3V C45 1000pF C44 0.1uF EN Vcc Vcc C42 0.1uF 8 7 14 anlg_3.3V 1 2 3 4 5 OVDD L9 270uH 4 T2 ADTL1-12+ D0N D0P D1N D1P 3 21 22 23 24 4 T1 L10 ADTL1-12+ Bead U1 KAD5514-48 D4N D4P D5N D5P 3 C15 0.1uF RESETN OVSS OVDD 0.01uF GND GND AVDD DNP C18 RESETN 18 DGND 19 OVDD 20 R17 28 270uH 46 45 44 43 42 6 50 Ohms differential routing SDIO SCLK CSB SDO OVSS 1 49 48 47 6 SMA EP AVSS AVDD 1 C20 VinIm L7 AVDD CLKP CLKN NAPSLP AVDD J2 Tx_VinIm R15 0 L6 Bead 50 Ohms Coplanar Waveguide D11P D11N D10P D10N 1uH NB6L14MMNG Place beads under DUT. L15 bead TC4-1W C25 T3 clk_inn L16 bead anlg_1.8V HI= Nap LO = Normal Ft= Sleep R20 DNP nap_sleep_normal SMA "CLOCK IN" C26 C28 coplanar wave guide. J4 1000pF 1000pF 1000pF L17 bead R22 200 R21 1K C24 clk_inp L18 bead 1000pF INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE Title Size KDC5512P/5512HP/5514P-Q48 Number Date: FIGURE 1. ADC, CLOCK AND ANALOG INPUTS, MODE PINS AND POWER SUPPLY BYPASS 1 Revision page1 B 1/30/2009 Sheet of KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Schematics (Continued) DGND GND AVDD AVDD 33uF anlg_1.8V C27 C_vdd3_anlg anlg_3.3V Anlg_5V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 Dig_5V C1 33uF dig_1.8V C4 0.1uF dig_1.8V C29 dig_1.8V 0.1uF C5 0.1uF dig_1.8V 4.7K R33 dig_1.8V C3 0.1uF dig_1.8V D5P D5N dig_1.8V SCLK SDO R5 1K R6 1K SDIO CSB R7 1K D4P D4N D3P D3N IO(2) IO(2) IO(2) IO(2) I(2) GND IO(1) VCC IO(1) IO(1) IO(1) U4 XC2C64A-6VQG44C 23 24 25 26 27 28 29 30 31 32 33 IO(2) TDO GND VCCIO2 IO(2) IO(2) IO(2) IO_GLB_S/R IO_GOE IO_GOE IO_GOE 11 TCK 10 TMS 9 TDI 1K 8 R9 7 VCC R10 1K 6 5 R11 1K 4 3 R12 1K R13 1K 2 CPLD SPARE1 1 C2 0.1uF 1 2 3 4 PC3 A0 A1 A2 Vss Vcc WP SCL SDA 10K 8 7 6 5 0 WP_2V SC0 SD0 R27 0 R26 24AA64-I/SN 34 35 36 37 38 39 40 41 42 43 44 D1P D1N dig_1.8V SPARE EEPROM U2 IO_GOE VAUX IO(2) IO(2) IO(2) IO(1) IO(1) IO(1) IO(1) IO(GCK) IO(GCK) D2P D2N dig_1.8V TCK TMS TDI IO(1) VCCIO1 I/O(1) I/O(1) GND I/O(1) I/O(1) I/O(GCK) 4.7K R1 1K TDO D6P D6N WP_2V SC2 SD2 R25 D7P D7N 8 7 6 5 Vcc WP SCL SDA 24AA32A-I/SN 22 21 20 19 18 17 16 15 14 13 12 dig_1.8V CLKOUTP CLKOUTN A0 A1 A2 Vss R28 D8P D8N U3 1 2 3 4 PC1 D9P D9N ID EEPROM 1K R8 dig_1.8V 1K R35 1K R34 WP see page 10 for J6 pinout notes D10P D10N dig_1.8V 1K R3 SPI_CONF 1K R29 RESETN 4.7K R31 PORn_ExtResetn_fpga 1K R4 D11P D11N R23 4.7K D12P D12N C30 D13P D13N 0.1uF VCC 33uF C7 VCC VCC ORP ORN D0P D0N SD0 SC0 SD2 SC2 PORn_ExtResetn_fpga PC6 PC7 PC0 daughter card detected PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC4 PC5 PC2 WP SPI_master_drive CPLD SPARE1 SCLK_3V CSB_3V MISO_3V MOSI_3V R24 1K VCC R30 1K R32 1K WP_2V SCLK_3V CSB_3V SPI_master_drive R36 1K MISO_3V MOSI_3V 33uF C6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 R2 OVDD OVDD 4.7K J6 dig_1.8V SC0 L4 Bead SCL SD0 L3 Bead SDA L13 Bead L14 Bead C8 C9 100pF 100pF C10 C11 100pF 100pF key face toward center JTAG connector Programing PLCD J1 DGND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC TMS TCK TDO TDI 2MM HDR 14P SMT INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEM Title Size 5509-11875 B Date: File: FIGURE 2. INPUT/OUTPUT MEZZANINE CONNECTOR 2 KDC5512P/5512HP/5514P-Q48 Number Revision page2 1/30/2009 \\..\KDC5512-Q48 IO.SchDoc A Sheet of Drawn By: KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers FIGURE 3. PRIMARY SIDE 3 KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued) FIGURE 4. GND PLANE 1 4 KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued) FIGURE 5. PWR PLANE 5 KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued) FIGURE 6. INTERNAL SIGNAL 6 KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued) FIGURE 7. GND PLANE 2 7 KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued) FIGURE 8. SECONDARY SIDE 8 KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued) FIGURE 9. SECONDARY SIDE SILKSCREEN 9 KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL KDC5512-Q48EVAL, KDC5512H-Q48EVAL, KDC5514-Q48EVAL Layers (Continued) FIGURE 10. LAYER - PRIMARY SIDE SILKSCREEN J6 pinout is shown for 14bit device. ADC Output Data pins are MSB justified at J6. Pins 38,40 at J6 are ADC signals D6P,D6N for 14 bit device. Pins 38,40 at J6 are ADC signals D5P,D5N for 12 bit device. Contact factory for additional information if needed. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. 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