1 AVDD DGND lvds_1 lvds_n1 OVDD DGND lvds_2 lvds_n2 lvds_3 lvds_n3 lvds_4 lvds_n4 65 64 63 62 61 60 59 58 57 56 55 R=49.9K D0P D0N D1P D1N D2P D2N OVDD OVSS ORP ORN 48 47 CSB SCLK C37 100pF C36 clk_out clk_outn 46 10K 45 DGND 44 43 42 41 40 39 38 37 ISL214P50IRZ or ISLA214P25IRZ or ISLA216P25IRZ lvds_5 lvds_n5 lvds_6 lvds_n6 lvds_7 lvds_n7 R46 lvds_8 lvds_n8 lvds_9 lvds_n9 lvds_10 lvds_n10 lvds_11 lvds_n11 D11N D11P D10N D10P 33 34 35 36 19 20 21 AVDD K=15uV 54 53 52 51 50 49 Under DUT. L15 bead U5 anlg_3.3V Temp=(V-RK)/Rm m=9uV/160C lvds_n13 lvds_13 lvds_n12 lvds_12 RESETN Temp=(I-K)/m or OVSS CLKDIV IPTAT DNC AVDD AVDD AVDD ExtResetn_PORn 18 D6P D6N D7P D7N D8P D8N D9P D9N OVDD 15 16 17 RLVDS OVSS AVSS AVDD AVSS 32 clkdivn IPTAT spare 12 13 14 OVDD Bead GND AVDD GND D13N D13P D12N D12P L2 ExtResetn_PORn 28 29 30 31 Bead lvds_n15 lvds_15 lvds_n14 lvds_14 L1 CLKOUTP CLKOUTN VINP VINP OVSS OVDD ExtResetn VINN VINN CLKDIVRSTP CLKDIVRSTN 10 11 VINP 26 27 8 9 VINN AVSS AVDD AVSS DGND OVDD Header 2x2 U1 D14 D3P D3N D4P D4N D5P D5N CLKDIV_RESETP 24 CLKDIV_RESETN 25 5 6 7 R23 DNP SDIO SCLK CSB SDO GND AVDD GND clkdivn 2 4 DNC DNC NAPSLP VCM CLKP CLKN 1 3 1 2 3 4 22 23 JP2 SDA SCL NAP_SLEEP Vcm CLKP CLKN R22 DNP AVDD AVDD AVDD EP HI= clk_div4 Float=clk_div1 LO= clk_div2 U1 (ADC) = 72pin QFN CONFIDENTIAL IN REVIEW anlg_1.8V anlg_1.8V SDIO SCLK CSB SDO Header 2x2 69 68 67 66 R28 DNP 72 71 70 GND NAP_SLEEP 2 4 0 2 R26 DNP JP1 1 3 R61 1K SDIO Bead 100pF L12 100pF Bead C35 L14 C43 0.1uF OVDD Bead pin62 L11 OVDD Bead pin32 SDL2 L13 C27 SCL2 Bead 0.1uF Bead L10 OVDD L8 SD2 pin27 SC2 SDA C14 SCL Bead C24 Bead L3 0.1uF pin16 clkdivn pin3 pin4 NAP_SLEEP C45 100pF L4 SD0 anlg_1.8V anlg_1.8V R60 1K C42 0.1uF SC0 0.1uF C26 0.1uF C22 0.1uF HI= Nap Float= Sleep LO = Normal_Op Vcm pin70 pin21 C20 0.1uF AVDD pin13 C15 0.1uF AVDD AVDD pin6 AVDD ISLA214IR72EV1Z Schematics C8 10uF C25 0.1uF SCL2 SDL2 6 8 7 10 9 VDD SCL SDA ADR1 ADR0 CH1+ CH1CH2+ CH2VSS MCP3423T-E/UN spare 1 2 4 5 3 L16 bead IPTAT R24 DNP L17 bead R25 DNP L18 bead INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGR Title Size FIGURE 1. ADC ADC Number page2 Revision ISLA214IR72EV1Z Schematics Sampling Clock Populate Depopulate LVCMOS C28, C29 C38, C39 LVDS C38, C39 C28, C29 T3 4 50 Ohms coplanar 1000pF 1000pF C29 1 TC4-19G2+ 4:1 sec/pri CONFIDENTIAL IN REVIEW anlg_3.3V C16 1000pF "CLOCK IN" "MAX=14 dBm" 1 2 3 4 0.01uF C46 VT D D NC NC 1 2 0.01uF C52 R100 1K 3 4 C53 0.1uF CLKP R43 100 R47 100 6 Vref Q Q VT D D NC NC NC NC NC NC NC 12 11 10 9 6 5 EP 3 T2 C17 4 3 ADTL1-12+ 1:1 sec/pri R17 DNP 6 2 0.1uF C39 DNP 1 R16 DNP TC4-19G2+ 4:1 sec/pri C56 0.1uF SMA J3 1 L9 1uH R21 13 R19 13 L7 1uH C54 2pF R52 DNP 1 T4 ADTL1-12+ 1:1 sec/pri 6 3 C40 0.1uF R18 0 T5 TX-2-5-1 6 L5 DNP 4 L6 DNP 4 1 VINP Vcm C18 0.1uF R49 54.9 R50 95 R51 95 R100 was added to rev B pcb Rev B pcb also Cut trace at C53 R20 0 INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREE Title Size B Date: File: FIGURE 2. ANALOG FRONT END, CLOCK, SYNC RESET VINN 5 2 AT1 50 Ohms coplanar C41 3 3 PAT-3 3 dB CLKDIV_RESETP CLKDIV_RESETN VINN Vcm =Value R48 54.9 C55 2pF C9 5.6pF R45 0 Pin6= Primary Dot "Analog Input" C51 1uF R53 DNP 4 Vcm U7 ADCLK905 Vcc Vcc 13 8 16 1 T1 0.1uF C12 0.1uF C50 1000pF Vee Vee "Synch_Reset" "MAX=14 dBm" 1 C21 50 Ohms coplanar 3 anlg_3.3V C49 1000pF 15 J7 SMA R64 10 0 9 6 5 EP SMA VINP AT2 3 dB PAT-3 optional path anlg_3.3V C48 1uF 12 11 CLKN 7 14 C47 0.1uF NC NC NC NC NC C38 DNP R63 0 J2 2 4 J5 SMA Q Q Vee Vee 16 Vref C19 0.1uF U6 ADCLK905 Vcc Vcc 13 8 C13 1000pF 15 CLKP 1000pF anlg_3.3V C57 0.1uF CLKN R27 200 2 4 SMA 2 C28 C30 0.01uF 7 14 3 "Clock J4 Input" C32 3 6 (Continued) Analog Front End, Clock, Sync Reset Number Revision page3 6-Apr-2011 Sheet of C:\Documents and Settings\GHENDRIC\My Drawn Documents\D14 By: pcbs\Si ISLA214IR72EV1Z Schematics AVDD C60 DNP C31 33uF anlg_1.8V C_vdd3_anlg anlg_3.3V Anlg_5V 4.7K 4.7K R58 R59 R2 4.7K 4.7K R37 SDO VCC VCC C3 0.1uF U4 CONFIDENTIAL IN REVIEW lvds_7 lvds_n7 ExtResetn PORn_ExtResetn_fpga R39 R41 R40 DNP DNP 4.7K 22 21 20 19 18 17 16 15 14 13 12 clk_out clk_outn DNP DNP R14 Resetn lvds_6 lvds_n6 4.7K S1 Tachtile Switch B3FS 4.7K ExtResetn_sense R3 Resetn R35 R55 4.7K lvds_5 lvds_n5 R56 DNP DNP dig_1.8V lvds_4 lvds_n4 PORn_ExtResetn_fpga 1K R4 DGND config_spare0 dig_1.8V config_spare1 config_spare2 config_spare3 lvds_3 lvds_n3 R57 config_spare0 config_spare1 config_spare2 config_spare3 ExtResetn lvds_2 lvds_n2 R15 33uF dig_1.8V dig_1.8V VCC C1 dig_1.8V VCC dig_1.8V 0.1uF C33 lvds_1 lvds_n1 0.1uF lvds_0 lvds_n0 C4 33uF C7 ID EEPROM XC2C64A-6VQG44C U3 IO(2) IO(2) IO(2) IO(2) I(2) GND IO(1) VCC IO(1) IO(1) IO(1) lvds_9 lvds_n9 lvds_10 lvds_n10 lvds_11 lvds_n11 TCK TMS TDI IO(1) VCCIO1 I/O(1) I/O(1) GND I/O(1) I/O(1) I/O(GCK) lvds_13 lvds_n13 R12 1K R13 1K CPLD SPARE1 MOSI_EN_3V CPLD SPARE1 SCLK_3V CSB_3V MISO_3V MOSI_3V PC4 PC5 PC2 WP PC0 daughter card detected PC1 PC2 PC3 PC4 PC5 PC6 PC7 C2 0.1uF SPARE EEPROM U2 1 2 3 4 J1 1 3 5 7 9 11 13 SD0 SC0 SD2 SC2 PORn_ExtResetn_fpga 2 4 6 8 10 12 14 8 7 6 5 WP SC2 SD2 VCC JTAG connector PLCD Programing PC6 PC7 lvds_15 lvds_n15 Vcc WP SCL SDA A0 A1 A2 Vss 24FC128-I/SN 34 35 36 37 38 39 40 41 42 43 44 lvds_14 lvds_n14 VCC TMS TCK TDO TDI Vcc WP SCL SDA A0 A1 A2 Vss VCC 8 7 6 R33 5 R32 WP 0 0 SC0 SD0 24FC128-I/SN 2MM HDR 14P SMT MH1 DGND GND 1 2 3 4 TCK TMS TDI R9 1K VCC R10 1K R11 1K IO_GOE VAUX IO(2) IO(2) IO(2) IO(1) IO(1) IO(1) IO(1) IO(GCK) IO(GCK) lvds_12 lvds_n12 IO(2) TDO GND VCCIO2 IO(2) IO(2) IO(2) IO_GLB_S/R IO_GOE IO_GOE IO_GOE 11 10 9 8 7 6 5 4 3 2 1 4.7K 4.7K 23 TDO24 25 dig_1.8V 26 SCLK 27 SDO 28 R5 1K 29 R6 1K 30 SDIO 31 CSB 32 R7 1K 33 R31 R29 1K 10K R1 R34 lvds_8 lvds_n8 R30 1K VCC R36 1K R38 1K R8 1K SCLK_3V CSB_3V MOSI_EN_3V R42 1K MISO_3V MOSI_3V 4 DGND GND AVDD Dig_5V VCC 0.1uF 33uF C6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 C5 C59 DNP 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 VCC 0.1uF OVDD OVDD C34 J6 dig_1.8V (Continued) MH2 MH3 MH4 Tooling Hole Tooling Hole Tooling Hole Tooling Hole INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NOND Title IO Level Translator ID PROM Size 55091-1875 B Date: File: FIGURE 3. IO LEVEL TRANSLATOR ID PROM R Number page4 6-Apr-2011 Sheet of Drawn By: C:\Documents and Settings\GHENDRIC\My Documents\D ISLA214IR72EV1Z Layers FIGURE 4. TOP SILKSCREEN 5 ISLA214IR72EV1Z Layers (Continued) FIGURE 5. TOP LAYER ROUTING 6 ISLA214IR72EV1Z Layers (Continued) CONFIDENTIAL IN REVIEW FIGURE 6. SPLIT GROUND PLANE 7 ISLA214IR72EV1Z Layers (Continued) FIGURE 7. SPLIT POWER PLANE 8 ISLA214IR72EV1Z Layers (Continued) FIGURE 8. INNER LAYER ROUTING 9 ISLA214IR72EV1Z Layers (Continued) FIGURE 9. 2ND SPLIT GROUND PLANE 10 ISLA214IR72EV1Z Layers (Continued) FIGURE 10. BOTTOM LAYER ROUTING 11 ISLA214IR72EV1Z Layers (Continued) FIGURE 11. BOTTOM SILKSCREEN Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 12