Si1865DDL Vishay Siliconix Load Switch with Level-Shift FEATURES PRODUCT SUMMARY VIN (VDS2) (V) 1.8 to 12 RDS(on) () Max. ID (A) 0.200 at VIN = 4.5 V 1.1 0.300 at VIN = 2.5 V 0.9 0.508 at VIN = 1.8 V 0.7 DESCRIPTION The Si1865DDL includes a p- and n-channel MOSFET in a single SC70-6 package. The low on-resistance p-channel TrenchFET is tailored for use as a load switch. The n-channel, with an external resistor, can be used as a levelshift to drive the p-channel load-switch. The n-channel MOSFET has internal ESD protection and can be driven by logic signals as low as 1.5 V. The Si1865DDL operates on supply lines from 1.8 V to 12 V, and can drive loads up to 1.1 A. • • • • • • • Low RDS(on) TrenchFET® 1.8 V to 12 V Input 1.5 V to 8 V Logic Level Control Low Profile, Small Footprint SC70-6 Package 2000 V ESD Protection On Input Switch, VON/OFF Adjustable Slew-Rate Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • Load Switch with Level-Shift • Slew-rate Control • Portable/Consumer Devices APPLICATION CIRCUITS Si1865DDL 14 IL = 1 A VON/OFF = 3 V Ci = 10 µF Co = 1 µF 2, 3 4 10.5 VOUT VIN tf Q2 R1 Time (us) C1 6 tr 6 5 7 td(off) 3.5 ON/OFF LOAD Co Q1 td(on) 0 Ci 0 2 1 4 6 8 10 R2 (kΩ) R2 Switching Variation R2 at VIN = 2.5 V, R1 = 20 k GND R2 COMPONENTS R1 Pull-Up Resistor Typical 10 k to 1 Ma R2 Optional Slew-Rate Control Typical 0 to 100 ka C1 Optional Slew-Rate Control Typical 1000 pF The Si1865DDL is ideally suited for high-side load switching in portable applications. The integrated n-channel level-shift device saves space by reducing external components. The slew rate is set externally so that rise-times can be tailored to different load types. Note: a. Minimum R1 value should be at least 10 x R2 to ensure Q1 turn-on. Document Number: 62888 S13-2618-Rev. B, 23-Dec-13 For technical questions, contact: [email protected] www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1865DDL Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM Si1865DDL SC70-6 4 2, 3 S2 R2 1 R1, C1 6 Marking Code VD D2 2 5 ON/OFF D2 3 4 S2 D2 Q2 6 XXX R1, C1 Lot Traceability and Date Code Part # Code Q1 5 ON/OFF Ordering Information: Si1865DDL-T1-GE3 (Lead (Pb)-free and Halogen-free) 1 R2 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Input Voltage On/Off Voltage Continuousa, b Load Current Pulsed Symbol Limit VIN(VDS2) 12 VON/OFF 8 a Continuous Intrinsic Diode Conduction Operating Junction and Storage Temperature Range ESD Rating, MIL-STD-883D Human Body Model (100 pF, 1500 ) A ±5 IS Maximum Power Dissipationa V ± 1.1 IL b, c Unit - 0.3 PD 0.357 W TJ, Tstg - 55 to 150 °C ESD 2 kV THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambient (continuous current)a Maximum Junction-to-Foot (Q2) Symbol Typical Maximum RthJA 290 350 RthJF 250 300 Unit °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Symbol Test Conditions Reverse Leakage Current IFL VIN = 12 V, VON/OFF = 0 V Diode Forward Voltage VSD IS = - 0.8 A Min. Typ. Max. Unit 1 µA - 0.84 - 1.2 V 12 V VON/OFF = 1.5 V, VIN = 4.5 V, ID = 1.1 A 0.165 0.200 VON/OFF = 1.5 V, VIN = 2.5 V, ID = 0.9 A 0.250 0.300 0.376 0.508 Off Characteristics On Characteristics VIN Input Voltage Range RDS(on) On-Resistance (P-Channel) 1.8 VON/OFF = 1.5 V, VIN = 1.8 V, ID = 0.2 A On-State (P-Channel) Drain-Current ID(on) VIN-OUT 0.2 V, VIN = 5 V, VON/OFF = 1.5 V 1 VIN-OUT 0.3 V, VIN = 3 V, VON/OFF = 1.5 V 1 A Notes: a. Surface mounted on FR4 board. b. VIN = 12 V, VON/OFF = 8 V, TA = 25 °C. c. Pulse test: pulse width 300 µs, duty cycle 2 %. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 For technical questions, contact: [email protected] Document Number: 62888 S13-2618-Rev. B, 23-Dec-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1865DDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 5 1.8 VGS = 5 V thru 3 V VON/OFF = 1.5 V to 8 V TJ = 125 oC VGS =2.5V 1.4 3 VDROP (V) ID - Drain Current (A) 4 VGS =2V 2 0.9 VGS =1.8V 0.5 1 TJ = 25 oC VGS = 1.5 V 0.0 0 0 0.5 1 1.5 0 2 1.5 3 IL (A) 4.5 6 VDS - Drain-to-Source Voltage (V) Output Characteristics VDROP vs. IL at VIN = 4.5 V 1.5 0.5 VON/OFF = 1.5 V to 8 V VON/OFF = 1.5 V to 8 V TJ = 125 oC TJ = 125 oC 0.4 0.9 VDROP (V) VDROP (V) 1.2 0.6 0.3 0.3 0.2 TJ = 25 oC 0.1 TJ = 25 oC 0.0 0.0 0 0.6 1.2 1.8 2.4 3 0 0.2 0.4 IL (A) 0.8 1 IL (A) VDROP vs. IL at VIN = 2.5 V VDROP vs. IL at VIN = 1.8 V 1.8 0.4 RDS(on) - On-Resistance (Normalized) IL = 1 A VON/OFF = 1.5 V to 8 V 0.3 VDROP (V) 0.6 TJ = 125 °C 0.2 TJ = 25 °C 0.1 0 1.6 IL = 1 A VON/OFF = 1.5 V to 8 V VGS = 4.5 V 1.4 VGS = 2.5 V 1.2 VGS = 1.8 V 1.0 0.8 0.6 0 2 4 VIN - (V) 6 8 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) VDROP vs. VIN at IL = 1 A Document Number: 62888 S13-2618-Rev. B, 23-Dec-13 Normalized On-Resistance vs. Junction Temperature For technical questions, contact: [email protected] www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1865DDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.4 10 0.3 IS - Source Current (A) RDS(on) - On-Resistance (Ω) IL = 1 A VON/OFF = 1.5 V to 8 V TJ = 125 °C 0.2 TJ = 25 °C 0.1 TJ = 150 °C TJ = 25 °C 1 0.1 0 0 2 4 6 0.0 8 On-Resistance vs. Input Voltage 18 0.4 0.6 0.8 1.0 1.2 Source-Drain Diode Forward Voltage 14 IL = 1 A VON/OFF = 3 V Ci = 10 µF Co = 1 µF tf 13.5 0.2 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) IL = 1 A VON/OFF = 3 V Ci = 10 µF Co = 1 µF 10.5 tr 9 Time (us) Time (us) tf td(off) 4.5 7 td(off) 3.5 tr td(on) td(on) 0 0 0 2 4 6 8 10 0 2 4 R2 (kΩ) Switching Variation R2 at VIN = 4.5 V, R1 = 20 k 20 10 150 tf 120 Time (us) tr Time (us) 8 Switching Variation R2 at VIN = 2.5 V, R1 = 20 k IL = 1 A VON/OFF = 3 V Ci = 10 µF Co = 1 µF 15 6 R2 (kΩ) 10 tf td(off) 90 IL = 1 A VON/OFF = 3 V Ci = 10 µF Co = 1 µF 60 5 30 td(off) td(on) 0 0 tr td(on) 0 2 4 6 8 10 0 20 Switching Variation R2 at VIN = 1.8 V, R1 = 20 k www.vishay.com 4 40 60 80 100 R2 (kΩ) R2 (kΩ) Switching Variation R2 at VIN = 4.5 V, R1 = 300 k For technical questions, contact: [email protected] Document Number: 62888 S13-2618-Rev. B, 23-Dec-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1865DDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 200 350 IL = 1 A VON/OFF = 3 V Ci = 10 µF Co = 1 µF tr 280 IL = 1 A VON/OFF = 3 V Ci = 10 µF Co = 1 µF tr Time (us) Time (us) 150 100 210 140 tf 50 70 td(off) 0 0 20 40 60 80 tf td(off) td(on) td(on) 0 100 0 20 40 60 80 100 R2 (kΩ) R2 (kΩ) Switching Variation R2 at VIN = 2.5 V, R1 = 300 k Switching Variation R2 at VIN = 1.8 V, R1 = 300 k 10 Limited by RDS(on)* ID - Drain Current (A) 100 μs 1 1 ms 10 ms 0.1 100 ms TA = 25 °C Single Pulse 0.01 0.1 1s DC, 10 s BVDSS Limited 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Foot Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 Notes: 0.1 PDM t1 t2 1. Duty Cycle, D = 0.05 0.02 t1 t2 2. Per Unit Base = R thJA = 130 °C/W 3. T JM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 0.0001 0.001 0.01 0.1 1 10 100 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62888. Document Number: 62888 S13-2618-Rev. B, 23-Dec-13 For technical questions, contact: [email protected] www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SCĆ70: 6ĆLEADS MILLIMETERS 6 5 Dim A A1 A2 b c D E E1 e e1 L 4 E1 E 1 2 3 -B- e b e1 D -Ac A2 A L A1 Document Number: 71154 06-Jul-01 INCHES Min Nom Max Min Nom Max 0.90 – 1.10 0.035 – 0.043 – – 0.10 – – 0.004 0.80 – 1.00 0.031 – 0.039 0.15 – 0.30 0.006 – 0.012 0.10 – 0.25 0.004 – 0.010 1.80 2.00 2.20 0.071 0.079 0.087 1.80 2.10 2.40 0.071 0.083 0.094 1.15 1.25 1.35 0.045 0.049 0.053 0.65BSC 0.026BSC 1.20 1.30 1.40 0.047 0.051 0.055 0.10 0.20 0.30 0.004 0.008 0.012 7_Nom 7_Nom ECN: S-03946—Rev. B, 09-Jul-01 DWG: 5550 www.vishay.com 1 AN814 Vishay Siliconix Dual-Channel LITTLE FOOTR SC-70 6-Pin MOSFET Recommended Pad Pattern and Thermal Performance INTRODUCTION This technical note discusses the pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for dual-channel LITTLE FOOT power MOSFETs in the SC-70 package. These new Vishay Siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 250 mA) need to be switched, either directly or by using a level shift configuration. Vishay provides these devices with a range of on-resistance specifications in 6-pin versions. The new 6-pin SC-70 package enables improved on-resistance values and enhanced thermal performance. PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification for the dual-channel SC-70 device in the 6-pin configuration. SOT-363 SC-70 (6-LEADS) S1 1 6 D1 G1 2 5 G2 D2 3 4 S2 applications for which this package is intended. For the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 20% when using a 1-inch square with full copper on both sides of the printed circuit board (PCB). EVALUATION BOARDS FOR THE DUAL SC70-6 The 6-pin SC-70 evaluation board (EVB) measures 0.6 inches by 0.5 inches. The copper pad traces are the same as described in the previous section, Basic Pad Patterns. The board allows interrogation from the outer pins to 6-pin DIP connections permitting test sockets to be used in evaluation testing. The thermal performance of the dual SC-70 has been measured on the EVB with the results shown below. The minimum recommended footprint on the evaluation board was compared with the industry standard 1-inch square FR4 PCB with copper on both sides of the board. THERMAL PERFORMANCE Top View FIGURE 1. For package dimensions see outline drawing SC-70 (6-Leads) (http://www.vishay.com/doc?71154) Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the dual SC-70 6-pin package measured as junction-to-foot thermal resistance is 300_C/W typical, 350_C/W maximum. The “foot” is the drain lead of the device as it connects with the body. Note that these numbers are somewhat higher than other LITTLE FOOT devices due to the limited thermal performance of the Alloy 42 lead-frame compared with a standard copper lead-frame. Junction-to-Ambient Thermal Resistance (dependent on PCB size) BASIC PAD PATTERNS See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286) for the 6-pin SC-70. This basic pad pattern is sufficient for the low-power Document Number: 71237 12-Dec-03 The typical RθJA for the dual 6-pin SC-70 is 400_C/W steady state. Maximum ratings are 460_C/W for the dual. All figures based on the 1-inch square FR4 test board. The following example shows how the thermal resistance impacts power dissipation for the dual 6-pin SC-70 package at two different ambient temperatures. www.vishay.com 1 AN814 Vishay Siliconix SC-70 (6-PIN) PD + Dual EVB Elevated Ambient 60 _C TJ(max) * TA Rq JA o o PD + 150 Co* 25 C 400 CńW PD + 312 mW PD + TJ(max) * TA Rq JA o o PD + 150 Co* 60 C 400 CńW PD + 225 mW NOTE: Although they are intended for low-power applications, devices in the 6-pin SC-70 will handle power dissipation in excess of 0.2 W. 400 Thermal Resistance (C/W) Room Ambient 25 _C 500 300 200 100 1” Square FR4 PCB 0 10-5 10-4 Testing LITTLE FOOT SC-70 (6-PIN) 1) Minimum recommended pad pattern (see Figure 2) on the EVB of 0.5 inches x 0.6 inches. 518_C/W 2) Industry standard 1” square PCB with maximum copper both sides. 413_C/W 2 10-2 10-1 1 10 100 1000 Time (Secs) To aid comparison further, Figure 2 illustrates the dual-channel SC-70 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state. The measured steady state values of RθJA for the dual 6-pin SC-70 are as follows: www.vishay.com 10-3 FIGURE 2. Comparison of Dual SC70-6 on EVB and 1” Square FR4 PCB. The results show that if the board area can be increased and maximum copper traces are added, the thermal resistance reduction is limited to 20%. This fact confirms that the power dissipation is restricted with the package size and the Alloy 42 leadframe. ASSOCIATED DOCUMENT Single-Channel LITTLE FOOT SC-70 6-Pin MOSFET Copper Leadframe Version, REcommended Pad Pattern and Thermal Performance, AN815, (http://www.vishay.com/doc?71334). Document Number: 71237 12-Dec-03 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead 0.067 0.026 (0.648) 0.045 (1.143) 0.096 (2.438) (1.702) 0.016 0.026 0.010 (0.406) (0.648) (0.241) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 18 Document Number: 72602 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000