VISHAY SI1926DL_10

Si1926DL
Vishay Siliconix
Dual N-Channel 60 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
60
RDS(on) (Ω)
ID (A)
1.4 at VGS = 10 V
0.37
3.0 at VGS = 4.5 V
0.25
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• ESD Protected: 1800 V
• Compliant to RoHS Directive 2002/95/EC
Qg (Typ.)
0.47
APPLICATIONS
SOT-363
SC-70 (6-LEADS)
S1
1
6
• Low Power Load Switch
D1
D1
D2
G1
2
5
G2
D2
3
4
S2
PD
XX
YY
Marking Code
Lot Traceability
and Date Code
G1
G2
Part # Code
Top View
Ordering Information: Si1926DL-T1-E3 (Lead (Pb)-free)
Si1926DL-T1-GE3 (Lead (Pb)-free and Halogen-free)
S1
S2
N-Channel MOSFET
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
60
Gate-Source Voltage
VGS
± 20
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
TC = 70 °C
TA = 25 °C
0.30
ID
0.34b, c
0.27b, c
IDM
Continuous Source-Drain Diode Current
Maximum Power Dissipation
TC = 25 °C
TA = 25 °C
0.43
IS
0.25b, c
TC = 25 °C
0.51
0.33
PD
W
0.30b, c
0.20b, c
TA = 70 °C
TJ, Tstg
Operating Junction and Storage Temperature Range
A
0.65
TC = 70 °C
TA = 25 °C
V
0.37
TA = 70 °C
Pulsed Drain Current
Unit
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
b, d
Maximum Junction-to-Ambient
Maximum Junction-to-Foot (Drain)
Symbol
Typical
Maximum
t≤5s
RthJA
360
415
Steady State
RthJF
300
350
Unit
°C/W
Notes:
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 400 °C/W.
Document Number: 73684
S10-0792-Rev. D, 05-Apr-10
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Si1926DL
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
60
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
ΔVDS/TJ
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
ΔVGS(th)/TJ
Gate-Source Threshold Voltage
ID = 250 µA
VGS(th)
VDS = VGS, ID = 250 µA
Gate-Source Leakage
IGSS
VDS = 0 V, VGS = ± 10 V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
Forward Transconductance
RDS(on)
gfs
V
56.7
mV/°C
-3
1
2.5
V
± 150
nA
VDS = 60 V, VGS = 0 V
1
VDS = 60 V, VGS = 0 V, TJ = 85 °C
10
VDS = ≥ 10 V, VGS = 4.5 V
0.50
VDS = ≥ 7.5 V, VGS = 10 V
0.65
A
VGS = 10 V, ID = 0.34 A
1.4
VGS = 4.5 V, ID = 0.23 A
3
VDS = 30 V, ID = 0.2 A
µA
159
Ω
ms
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
18.5
VDS = 30 V, VGS = 0 V, f = 1 MHz
7.5
VDS = 30 V, VGS = 10 V, ID = 0.34 A
0.9
1.4
0.5
0.75
4.2
VDS = 30 V, VGS = 4.5 V, ID = 0.34 A
tr
Turn-Off DelayTime
td(off)
Fall Time
0.2
nC
0.15
f = 1 MHz
td(on)
Rise Time
pF
VDD = 30 V, RL = 100 Ω
ID ≅ 0.3 A, VGEN = 10 V, Rg = 1 Ω
tf
160
240
6.5
10
12
18
13
22
14
21
Ω
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward
Currenta
Body Diode Voltage
IS
TC = 25 °C
0.43
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
0.65
IS = 0.3 A
IF = 0.6 A, dI/dt = 100 A/µs
A
0.8
1.2
V
16.5
25
nC
13
20
13.5
ns
3
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 73684
S10-0792-Rev. D, 05-Apr-10
Si1926DL
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.4
0.7
VGS = 10 V thru 5 V
VGS = 4 V
0.5
I D - Drain Current (A)
I D - Drain Current (A)
0.6
0.4
0.3
0.2
0.3
0.2
TC = 25 °C
0.1
VGS = 3 V
TC = 125 °C
0.1
0.0
0.0
TC = - 55 °C
0.0
0.5
1.0
1.5
2.0
2.5
0
3.0
1
2
3
4
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics Curves vs. Temperature
3.0
32
24
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
2.5
2.0
VGS = 4.5 V
1.5
VGS = 10 V
1.0
Ciss
16
Coss
8
0.5
Crss
0.0
0.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
10
ID - Drain Current (A)
20
50
60
Capacitance
10
1.6
VGS = 10 V, ID = 0.5 A
ID = 0.5 A
8
6
VDS = 48 V
4
2
(Normalized)
1.4
VDS = 30 V
R DS(on) - On-Resistance
VG S - Gate-to-Source Voltage (V)
40
VDS - Drain-Source Voltage (V)
On-Resistance vs. Drain Current
0
0.0
30
1.2
VGS = 4.5 V, ID = 0.2 A
1.0
0.8
0.3
0.6
0.9
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 73684
S10-0792-Rev. D, 05-Apr-10
1.2
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
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Si1926DL
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
5.0
1000
TA = 150 °C
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
ID = 0.5 A
TA = 25 °C
100
10
1
0.0
4.0
3.0
TA = 125 °C
2.0
TA = 25 °C
1.0
0.0
0.3
0.6
0.9
1.2
1.5
3
4
5
6
7
8
9
VSD - Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
RDS(on) vs. VGS vs. Temperature
2.0
5
1.8
4
10
Power (W)
VGS(th) (V)
ID = 250 µA
1.6
1.4
1.2
1.0
- 50
3
2
1
- 25
0
25
50
75
100
125
0
10-3
150
10 -2
10-1
1
10
TJ - Temperature (°C)
Time (s)
Threshold Voltage
Single Pulse Power
1
100
600
Limited by R DS(on)*
I D - Drain Current (A)
10 ms
0.1
100 ms
1s
10 s
0.01
TA = 25 °C
Single Pulse
DC
BVDSS Limited
0.001
0.1
* VGS
1
10
100
VDS - Drain-to-Source Voltage (V)
minimum VGS at which RDS(on) is specified
Safe Operating Area
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Document Number: 73684
S10-0792-Rev. D, 05-Apr-10
Si1926DL
Vishay Siliconix
0.5
0.5
0.4
0.4
Power Dissipation (W)
I D - Drain Current (A)
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.3
0.2
0.3
0.2
0.1
0.1
0.0
0.0
0
25
50
75
100
TC - Case Temperature (°C)
Current Derating*
125
150
0
25
50
75
100
125
150
TC - Case Temperature (°C)
Power Derating
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 73684
S10-0792-Rev. D, 05-Apr-10
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Si1926DL
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 400 °C/W
3. TJM - T A = PDMZthJA(t)
Single Pulse
0.01
10-4
4. Surface Mounted
10-3
10-2
10-1
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73684.
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Document Number: 73684
S10-0792-Rev. D, 05-Apr-10
Package Information
Vishay Siliconix
SCĆ70:
6ĆLEADS
MILLIMETERS
6
5
Dim
A
A1
A2
b
c
D
E
E1
e
e1
L
4
E1 E
1
2
3
-B-
e
b
e1
D
-Ac
A2 A
L
A1
Document Number: 71154
06-Jul-01
INCHES
Min
Nom
Max
Min
Nom
Max
0.90
–
1.10
0.035
–
0.043
–
–
0.10
–
–
0.004
0.80
–
1.00
0.031
–
0.039
0.15
–
0.30
0.006
–
0.012
0.10
–
0.25
0.004
–
0.010
1.80
2.00
2.20
0.071
0.079
0.087
1.80
2.10
2.40
0.071
0.083
0.094
1.15
1.25
1.35
0.045
0.049
0.053
0.65BSC
0.026BSC
1.20
1.30
1.40
0.047
0.051
0.055
0.10
0.20
0.30
0.004
0.008
0.012
7_Nom
7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
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AN814
Vishay Siliconix
Dual-Channel LITTLE FOOTR SC-70 6-Pin MOSFET
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
This technical note discusses the pin-outs, package outlines,
pad patterns, evaluation board layout, and thermal
performance for dual-channel LITTLE FOOT power
MOSFETs in the SC-70 package. These new Vishay Siliconix
devices are intended for small-signal applications where a
miniaturized package is needed and low levels of current
(around 250 mA) need to be switched, either directly or by
using a level shift configuration. Vishay provides these devices
with a range of on-resistance specifications in 6-pin versions.
The new 6-pin SC-70 package enables improved
on-resistance values and enhanced thermal performance.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel SC-70 device in the 6-pin configuration.
SOT-363
SC-70 (6-LEADS)
S1
1
6
D1
G1
2
5
G2
D2
3
4
S2
applications for which this package is intended. For the 6-pin
device, increasing the pad patterns yields a reduction in
thermal resistance on the order of 20% when using a 1-inch
square with full copper on both sides of the printed circuit board
(PCB).
EVALUATION BOARDS FOR THE DUAL
SC70-6
The 6-pin SC-70 evaluation board (EVB) measures 0.6 inches
by 0.5 inches. The copper pad traces are the same as
described in the previous section, Basic Pad Patterns. The
board allows interrogation from the outer pins to 6-pin DIP
connections permitting test sockets to be used in evaluation
testing.
The thermal performance of the dual SC-70 has been
measured on the EVB with the results shown below. The
minimum recommended footprint on the evaluation board was
compared with the industry standard 1-inch square FR4 PCB
with copper on both sides of the board.
THERMAL PERFORMANCE
Top View
FIGURE 1.
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the dual SC-70 6-pin package
measured as junction-to-foot thermal resistance is 300_C/W
typical, 350_C/W maximum. The “foot” is the drain lead of the
device as it connects with the body. Note that these numbers
are somewhat higher than other LITTLE FOOT devices due to
the limited thermal performance of the Alloy 42 lead-frame
compared with a standard copper lead-frame.
Junction-to-Ambient Thermal Resistance
(dependent on PCB size)
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the 6-pin
SC-70. This basic pad pattern is sufficient for the low-power
Document Number: 71237
12-Dec-03
The typical RθJA for the dual 6-pin SC-70 is 400_C/W steady
state. Maximum ratings are 460_C/W for the dual. All figures
based on the 1-inch square FR4 test board. The following
example shows how the thermal resistance impacts power
dissipation for the dual 6-pin SC-70 package at two different
ambient temperatures.
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AN814
Vishay Siliconix
SC-70 (6-PIN)
PD +
Dual EVB
Elevated Ambient 60 _C
TJ(max) * TA
Rq JA
o
o
PD + 150 Co* 25 C
400 CńW
PD + 312 mW
PD +
TJ(max) * TA
Rq JA
o
o
PD + 150 Co* 60 C
400 CńW
PD + 225 mW
NOTE: Although they are intended for low-power applications,
devices in the 6-pin SC-70 will handle power dissipation in
excess of 0.2 W.
400
Thermal Resistance (C/W)
Room Ambient 25 _C
500
300
200
100
1” Square FR4 PCB
0
10-5 10-4
Testing
LITTLE FOOT SC-70 (6-PIN)
1) Minimum recommended pad pattern (see
Figure 2) on the EVB of 0.5 inches x
0.6 inches.
518_C/W
2) Industry standard 1” square PCB with
maximum copper both sides.
413_C/W
2
10-2
10-1
1
10
100
1000
Time (Secs)
To aid comparison further, Figure 2 illustrates the dual-channel
SC-70 thermal performance on two different board sizes and
two different pad patterns. The results display the thermal
performance out to steady state. The measured steady state
values of RθJA for the dual 6-pin SC-70 are as follows:
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10-3
FIGURE 2.
Comparison of Dual SC70-6 on EVB and 1”
Square FR4 PCB.
The results show that if the board area can be increased and
maximum copper traces are added, the thermal resistance
reduction is limited to 20%. This fact confirms that the power
dissipation is restricted with the package size and the Alloy 42
leadframe.
ASSOCIATED DOCUMENT
Single-Channel LITTLE FOOT SC-70 6-Pin MOSFET Copper
Leadframe Version, REcommended Pad Pattern and Thermal
Performance, AN815, (http://www.vishay.com/doc?71334).
Document Number: 71237
12-Dec-03
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead
0.067
0.026
(0.648)
0.045
(1.143)
0.096
(2.438)
(1.702)
0.016
0.026
0.010
(0.406)
(0.648)
(0.241)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72602
Revision: 21-Jan-08
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Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
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including but not limited to the warranty expressed therein.
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Document Number: 91000
Revision: 11-Mar-11
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