For Communications Equipment MN86062 CODEC LSI for Facsimile Images Overview The MN86062 is a high-speed LSI codec for compressing and decompressing images using the MH, MR, and MMR standard compression methods specified in the ITU-T T.4 and T.6 recommendation. Registers and other settings provide flexible support for a variety of processing. Features Compression methods MH, MR, and MMR Operating mode: Page mode Bus configuration: Choice of dual- or single-bus operation Decoding error processing: Choice of replacing with the previous line or a white line Image bus configuration: 8 bits, maximum 16 megabytes address space of image bus, 2-channel master DMA System bus configuration: X80 interface compatible, 8 bits, 2-channel slave DMA Pixels per line: maximum 64K, in byte increments Concurrent DMA transfers over image bus and command processing Support for pointer management for image buffer Wide selection of independent parameters for coding, decoding, transfers between buses, and DMA transfersr Support for time-shared processing by line for both coding and decoding Applications Facsimile equipment MN86062 For Communications Equipment 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 IA19 IA20 IA21 IA22 IA23 NDCMP NDEND NDACK1 NDACK0 NDREQ1 NDREQ0 NIDACK IR/W NIAEN NDRUN NIBACK NIBREQ 2SYSCLK VDD1 VSS1 SYSCLK Pin Assignment 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS2 VDD2 TACK VSS3 VDD3 N.C.3 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 VDD4 VSS4 TEST2 TEST1 TEST0 NACKD NACKC N.C.1 N.C.2 IA18 IA17 IA16 IA15 IA14 IA13 IA12 IA11 IA10 IA9 IA8 IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0 (TOP VIEW) QFP084-P-1818 TEST3 TEST4 D0 D1 D2 D3 D4 D5 D6 D7 NIRQ NRESET A0 A1 A2 A3 NCS NRD NWT NREQC NREQD TEST(4:0) VSS VDD NACKD NREQD NACKC NREQC SYSCLK 2SYSCLK NRESET NIRQ NWT NRD NCS D(7:0) A(3:0) Master DMA (2 channels) 48 47 52 20 22 21 23 Decoding FIFO Coding FIFO Decoding table Coding table Table look-up block Image reconstruction block Change point detector Mode selection block Coding line FIFO Reference line FIFO 58 57 49 56 54 55 Slave DMA (2 channels) Image bus interface 50 51 53 Parameter register ALU2 Sub sequencer 43 Register bank ALU1 Main sequencer 46 31 32 24 25 System bus interface Microprogram control block NDCMP NDEND NDRUN NDACK1 NDREQ1 NDACK0 NDREQ0 NIBACK NIBREQ NIDACK NIAEN IR/W ID(7:0) IA(23:0) For Communications Equipment MN86062 Block Diagram MN86062 For Communications Equipment Pin Descriptions System Bus Interface Pin No. 27 Symbol A3 I/O I Function Description Address bus for accessing internal registers 28 A2 29 A1 30 A0 33 D7 I/O Data bus for bidirectional transfers over system bus 34 D6 Tristate 35 D5 36 D4 37 D3 38 D2 39 D1 40 D0 24 NWT I Connect to WR pin on X80-compatible microprocessor 25 NRD I Connect to RD pin on X80-compatible microprocessor 26 NCS I Chip select pin 23 NREQC O Tristate 22 NREQD O Tristate This output pin indicates a DMA transfer request from the 86062 to memory. This output pin indicates a DMA transfer request from the memory to 86062. 21 NACKC I This input pin accepts the response to the NREQC signal. 20 NACKD I This input pin accepts the response to the NREQD signal. 32 NIRQ O Open drain This output pin indicates an interrupt request. 31 NRESET I External input resets the 86062. 46 2SYSCLK I This input pin accepts a clock signal with twice the system clock frequency. 43 SYSCLK O This output pin provides a clock signal with half the frequency of 2SYSCLK. 15 VDD4 I Connect these power supply pins to a 5 volt power supply. I Connect these power supply pins to ground. I Do not use these test pins. O Do not use these test pins. 5 VDD3 2 VDD2 45 VDD1 16 VSS4 4 VSS3 1 VSS2 44 VSS1 41 TEST4 42 TEST3 17 TEST2 18 TEST1 19 TEST0 3 TACK For Communications Equipment MN86062 Pin Descriptions (continued) Image Bus Interface (continued) Pin No. 59 Symbol IA23 I/O O 60 IA22 Tristate 61 IA21 62 IA20 63 IA19 66 IA18 67 IA17 68 IA16 69 IA15 70 IA14 71 IA13 72 IA12 73 IA11 74 IA10 75 IA9 76 IA8 77 IA7 78 IA6 79 IA5 80 IA4 81 IA3 82 IA2 83 IA1 84 IA0 7 ID7 I/O 8 ID6 Tristate 9 ID5 10 ID4 11 ID3 12 ID2 13 ID1 14 ID0 47 IBREQ 48 50 51 IR/W Function Description Image address bus. The address is valid when the NIAEN pin is at "L" level. Image data bus for bidirectional transfers of image data O This output pin indicates a request for control of the image bus. IBACK I This input pin accepts the response to the NIBREQ signal. IAEN O This output pin indicates whether the values of image address bus are Tristate O Tristate valid. This output pin indicates the data transfer direction for the image bus. MN86062 For Communications Equipment Pin Descriptions (continued) Image Bus Interface (continued) Pin No. 52 Symbol IDACK I/O I Function Description This input pin indicates the end of a data read or write operation. 49 DRUN O This output pin indicates whether a DMA transfer is in progress. 57 DEND O 58 DCMP O This output pin indicates successful completion of a DMA block transfer. 53 DREQ0 I This input pin indicates a DMA transfer request from the I/O block to 54 DREQ1 I 55 DACK0 O This output pin gives the response to the NDREQ0 signal. 56 DACK1 O This output pin gives the response to the NDREQ1 signal. Tristate This output pin indicates the end of a DMA cycle. memory. This input pin indicates a DMA transfer request from the memory to I/O block. Test Pin Setting Symbol TEST0 Pin No. 19 Fixed Level GND TEST1 18 GND TEST2 17 GND TEST3 42 GND TEST4 41 GND For Communications Equipment MN86062 Package Dimensions (Unit: mm) QFP084-P-1818 22.90±0.40 18.00±0.20 63 43 42 84 22 0.15 SEATING PLANE (2.45±0.20) 0.15 +0.10 -0.05 0.35±0.10 2.90 max. 0.80 2.50±0.20 (1.00) 21 0.10±0.10 1 22.90±0.40 18.00±0.20 (1.00) 64 0 to 10° (1.30±0.20)