Si1922EDH Datasheet

Si1922EDH
Vishay Siliconix
Dual N-Channel 20 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
RDS(on) (Ω)
ID (A)a
0.198 at VGS = 4.5 V
1.3a
0.225 at VGS = 2.5 V
1.3a
0.263 at VGS = 1.8 V
1.3a
VDS (V)
20
Qg (Typ.)
0.9 nC
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• Typical ESD Protection 2100 V HBM
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
SOT-363
SC-70 (6-LEADS)
S1
1
6
2
5
• Load Switch for Portable Applications
D1
D1
D2
G1
D2
3
4
G2
S2
CG
XX
YY
Marking Code
1k
Lot Traceability
and Date Code
1k
G1
G2
Part # Code
Top View
Ordering Information:
Si1922EDH-T1-GE3 (Lead (Pb)-free and Halogen-free)
S1
S2
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
20
Gate-Source Voltage
VGS
±8
TC = 70 °C
TA = 25 °C
1.3a
ID
1.3a, b, c
1.2b, c
TA = 70 °C
Pulsed Drain Current
Continuous Source-Drain Diode Current
IDM
TC = 25 °C
TA = 25 °C
Maximum Power Dissipation
TA = 25 °C
1
IS
0.61b, c
1.25
0.8
PD
W
0.74b, c
0.47b, c
TA = 70 °C
Operating Junction and Storage Temperature Range
A
4
TC = 25 °C
TC = 70 °C
V
1.3a
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
Unit
TJ, Tstg
°C
- 55 to 150
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Maximum Junction-to-Ambientb, d
t≤5s
RthJA
130
170
Maximum Junction-to-Foot (Drain)
Steady State
RthJF
80
100
Unit
°C/W
Notes:
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 220 °C/W.
Document Number: 67192
S11-2307-Rev. B, 21-Nov-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1922EDH
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
20
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
ΔVDS/TJ
VGS(th) Temperature Coefficient
ΔVGS(th)/TJ
Gate-Source Threshold Voltage
VGS(th)
ID = 250 µA
VDS = VGS, ID = 250 µA
V
20
mV/°C
- 2.3
0.4
1
VDS = 0 V, VGS = ± 8 V
± 25
VDS = 0 V, VGS = ± 4.5 V
1
VDS = 20 V, VGS = 0 V
1
VDS = 20 V, VGS = 0 V, TJ = 55 °C
10
Gate-Source Leakage
IGSS
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
VDS ≤ 5 V, VGS = 4.5 V
VGS = 4.5 V, ID = 1 A
0.165
0.198
RDS(on)
VGS = 2.5 V, ID = 1 A
0.187
0.225
VGS = 1.8 V, ID = 0.2 A
0.210
0.263
VDS = 4 V, ID = 1.5 A
4
VDS = 10 V, VGS = 8 V, ID = 1.5 A
1.6
2.5
0.9
1.8
Drain-Source On-State Resistancea
Forward Transconductancea
gfs
4
V
µA
µA
A
Ω
S
Dynamicb
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-on Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
VDS = 10 V, VGS = 4.5 V, ID = 1.5 A
0.1
0.2
f = 1 MHz
0.4
1.9
3.8
43
65
80
120
480
720
tf
220
330
td(on)
22
33
td(on)
tr
td(off)
tr
td(off)
nC
VDD = 10 V, RL = 8.3 Ω
ID ≅ 1.2 A, VGEN = 4.5 V, Rg = 1 Ω
VDD = 10 V, RL = 8.3 Ω
ID ≅ 1.2 A, VGEN = 8 V, Rg = 1 Ω
tr
46
70
645
968
215
323
kΩ
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
TC = 25 °C
1
4
IS = 1.2 A, VGS = 0 V
IF = 1.2 A, dI/dt = 100 A/µs, TJ = 25 °C
A
0.8
1.2
V
9
18
ns
2
4
nC
5
4
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 67192
S11-2307-Rev. B, 21-Nov-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1922EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10-3
0.5
10-4
10-5
IG - Gate Current (A)
IG - Gate Current (mA)
0.4
0.3
TJ = 25 °C
0.2
TJ = 150 °C
10-6
10-7
TJ = 25 °C
10-8
0.1
10-9
10-10
0
0
3
6
9
12
VGS - Gate-to-Source Voltage (V)
0
15
Gate Current vs. Gate-to-Source Voltage
3
6
9
12
VGS - Gate-to-Source Voltage (V)
15
Gate Current vs. Gate-to-Source Voltage
1.0
4
V GS = 5 V thru 2 V
0.8
ID - Drain Current (A)
ID - Drain Current (A)
3
V GS = 1.5 V
2
0.6
T C = 25 °C
0.4
T C = 125 °C
1
0.2
V GS = 1 V
0
0.0
0.5
1.0
1.5
0.0
0.0
2.0
0.3
0.6
0.9
1.2
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
1.5
8
VGS - Gate-to-Source Voltage (V)
0.25
RDS(on) - On-Resistance (Ω)
T C = - 55 °C
V GS = 1.8 V
0.22
V GS = 2.5 V
0.19
V GS = 4.5 V
0.16
0.13
0
1
2
3
4
ID = 1.5 A
6
V DS = 10 V
V DS = 16 V
V DS = 5 V
4
2
0
0.0
0.5
1.0
1.5
ID - Drain Current (A)
Qg - Total Gate Charge (nC)
On-Resistance vs. Drain Current
Gate Charge
Document Number: 67192
S11-2307-Rev. B, 21-Nov-11
2.0
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1922EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10
ID = 1 A
1.5
V GS = 2.5 V
IS - Source Current (A)
RDS(on) - On-Resistance (Normalized)
1.7
1.3
V GS = 4.5 V
1.1
T J = 150 °C
T J = 25 °C
1
0.9
0.7
- 50
0.1
- 25
0
25
50
75
100
TJ - Junction Temperature (°C)
125
0.0
150
0.3
0.6
0.9
1.2
1.5
VSD - Source-to-Drain Voltage (V)
On-Resistance vs. Junction Temperature
Source-Drain Diode Forward Voltage
0.80
0.4
0.65
0.3
ID = 250 μA
T J = 125 °C
0.2
VGS(th) (V)
RDS(on) - On-Resistance (Ω)
ID = 1 A
T J = 25 °C
0.50
0.35
0.1
0.20
- 50
0.0
1
2
3
4
5
- 25
0
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
25
50
75
100
TJ - Temperature (°C)
125
150
Threshold Voltage
10
5
Limited by RDS(on)*
100 μs
ID - Drain Current (A)
Power (W)
4
3
2
1
1 ms
10 ms
0.1
100 ms
1
TA = 25 °C
Single Pulse
0
0.01
0.1
1
10
100
Time (s)
Single Pulse Power, Junction-to-Ambient
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4
600
0.01
0.1
1 s, 10 s
DC
BVDSS Limited
100
1
10
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
Document Number: 67192
S11-2307-Rev. B, 21-Nov-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1922EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2.4
ID - Drain Current (A)
1.8
Package Limited
1.2
0.6
0.0
0
25
50
75
100
TC - Case Temperature (°C)
125
150
1.5
0.75
1.2
0.60
0.9
0.45
Power (W)
Power (W)
Current Derating*
0.6
0.3
0.30
0.15
0.0
0.00
0
25
50
75
100
TF - Case Temperature (°C)
Power, Junction-to-Foot
125
150
0
25
50
75
100
125
150
TA - Ambient Temperature (°C)
Power, Junction-to-Ambient
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 67192
S11-2307-Rev. B, 21-Nov-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si1922EDH
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
P DM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 170 °C/W
0.02
3. T JM - TA = PDMZthJA(t)
Single Pulse
0.01
10 -4
4. Surface Mounted
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?67192.
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Document Number: 67192
S11-2307-Rev. B, 21-Nov-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SCĆ70:
6ĆLEADS
MILLIMETERS
6
5
Dim
A
A1
A2
b
c
D
E
E1
e
e1
L
4
E1 E
1
2
3
-B-
e
b
e1
D
-Ac
A2 A
L
A1
Document Number: 71154
06-Jul-01
INCHES
Min
Nom
Max
Min
Nom
Max
0.90
–
1.10
0.035
–
0.043
–
–
0.10
–
–
0.004
0.80
–
1.00
0.031
–
0.039
0.15
–
0.30
0.006
–
0.012
0.10
–
0.25
0.004
–
0.010
1.80
2.00
2.20
0.071
0.079
0.087
1.80
2.10
2.40
0.071
0.083
0.094
1.15
1.25
1.35
0.045
0.049
0.053
0.65BSC
0.026BSC
1.20
1.30
1.40
0.047
0.051
0.055
0.10
0.20
0.30
0.004
0.008
0.012
7_Nom
7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
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AN816
Vishay Siliconix
Dual-Channel LITTLE FOOTR 6-Pin SC-70 MOSFET
Copper Leadframe Version
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
87 (mil)
26 (mil)
The new dual 6-pin SC-70 package with a copper leadframe
enables improved on-resistance values and enhanced
thermal performance as compared to the existing 3-pin and
6-pin packages with Alloy 42 leadframes. These devices are
intended for small to medium load applications where a
miniaturized package is required. Devices in this package
come in a range of on-resistance values, in n-channel and
p-channel versions. This technical note discusses pin-outs,
package outlines, pad patterns, evaluation board layout, and
thermal performance for the dual-channel version.
6
5
96 (mil)
71 (mil)
48 (mil)
23 (mil)
61 (mil)
1
PIN-OUT
4
2
3
0.0 (mil)
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel SC-70 device in the 6-pin configuration.
Both n-and p-channel devices are available in this package –
the drawing example below illustrates the p-channel device.
26 (mil)
16 (mil)
FIGURE 2.
SOT-363
SC-70 (6-LEADS)
S1
1
6
D1
G1
2
5
G2
D2
3
4
S2
Top View
FIGURE 1.
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the SC-70
6-pin basic pad layout and dimensions. This pad pattern is
sufficient for the low-power applications for which this package
is intended. Increasing the drain pad pattern (Figure 2) yields
a reduction in thermal resistance and is a preferred footprint.
Document Number: 71405
12-Dec-03
8 (mil)
SC-70 (6 leads) Dual
EVALUATION BOARD FOR THE DUALCHANNEL SC70-6
The 6-pin SC-70 evaluation board (EVB) shown in Figure 3
measures 0.6 in. by 0.5 in. The copper pad traces are the same
as described in the previous section, Basic Pad Patterns. The
board allows for examination from the outer pins to the 6-pin
DIP connections, permitting test sockets to be used in
evaluation testing.
The thermal performance of the dual 6-pin SC-70 has been
measured on the EVB, comparing both the copper and Alloy
42 leadframes. This test was then repeated using the 1-inch2
PCB with dual-side copper coating.
A helpful way of displaying the thermal performance of the
6-pin SC-70 dual copper leadframe is to compare it to the
traditional Alloy 42 version.
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AN816
Vishay Siliconix
Front of Board SC70-6
Back of Board SC70-6
S1
D1
G1
G2
D2
S2
vishay.com
SC70−6 DUAL
FIGURE 3.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
COOPER LEADFRAME
Room Ambient 25 _C
Thermal performance for the dual SC-70 6-pin package is
measured as junction-to-foot thermal resistance, in which the
“foot” is the drain lead of the device as it connects with the
body. The junction-to-foot thermal resistance for this device is
typically 80_C/W, with a maximum thermal resistance of
approximately 100_C/W. This data compares favorably with
another compact, dual-channel package – the dual TSOP-6 –
which features a typical thermal resistance of 75_C/W and a
maximum of 90_C/W.
PD +
Elevated Ambient 60 _C
T J(max) * T A
Rq JA
PD +
T J(max) * T A
Rq JA
o
o
P D + 150 Co* 25 C
224 CńW
o
o
P D + 150 Co* 60 C
224 CńW
P D + 558 mW
P D + 402 mW
Although they are intended for low-power applications,
devices in the 6-pin SC-70 dual-channel configuration will
handle power dissipation in excess of 0.5 W.
TESTING
Power Dissipation
The typical RθJA for the dual-channel 6-pin SC-70 with a
copper leadframe is 224_C/W steady-state, compared to
413_C/W for the Alloy 42 version. All figures are based on the
1-inch2 FR4 test board. The following example shows how the
thermal resistance impacts power dissipation for the dual 6-pin
SC-70 package at varying ambient temperatures.
To further aid the comparison of copper and Alloy 42
leadframes, Figures 4 and 5 illustrate the dual-channel 6-pin
SC-70 thermal performance on two different board sizes and
pad patterns. The measured steady-state values of RθJA for
the dual 6-pin SC-70 with varying leadframes are as follows:
LITTLE FOOT 6-PIN SC-70
1) Minimum recommended pad pattern on
the EVB board (see Figure 3).
Alloy 42 Leadframe
1-inch2
2) Industry standard
PCB with
maximum copper both sides.
ALLOY 42 LEADFRAME
Room Ambient 25 _C
PD +
T J(max) * T A
PD +
T J(max) * T A
Rq JA
o
o
P D + 150 Co* 25 C
413 CńW
o
o
P D + 150 Co* 60 C
413 CńW
P D + 303 mW
P D + 218 mW
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2
Rq JA
Elevated Ambient 60 _C
Alloy 42
Copper
518_C/W
344_C/W
413_C/W
224_C/W
The results indicate that designers can reduce thermal
resistance (θJA) by 34% simply by using the copper leadframe
device as opposed to the Alloy 42 version. In this example, a
174_C/W reduction was achieved without an increase in board
area. If an increase in board size is feasible, a further 120_C/W
reduction can be obtained by utilizing a 1-inch2. PCB area.
The Dual copper leadframe versions have the following suffix:
Dual:
Compl.:
Si19xxEDH
Si15xxEDH
Document Number: 71405
12-Dec-03
AN816
500
500
400
400
Thermal Resistance (C/W)
Thermal Resistance (C/W)
Vishay Siliconix
300
Alloy 42
200
Copper
100
300
Alloy
42
200
100
Copper
0
0
10-5
10-4
10-3
10-2
10-1
1
10
100
1000
10-5
Dual SC70-6 Thermal Performance on EVB
Document Number: 71405
12-Dec-03
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
Time (Secs)
FIGURE 4.
10-4
FIGURE 5.
Dual SC70-6 Comparison on 1-inch2 PCB
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Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead
0.067
0.026
(0.648)
0.045
(1.143)
0.096
(2.438)
(1.702)
0.016
0.026
0.010
(0.406)
(0.648)
(0.241)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72602
Revision: 21-Jan-08
Legal Disclaimer Notice
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12
1
Document Number: 91000