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THC63LVD1024_Rev.2.5_E
THC63LVD1024
135MHz 67Bits LVDS Receiver
General Description
Features
The THC63LVD1024 receiver is designed to support
Dual Link transmission between Host and Flat Panel
Display up to 1080p/QXGA resolutions. The
THC63LVD1024 converts the LVDS data streams back
into 67bits of CMOS/TTL data with falling edge or rising edge clock for convenient with a variety of LCD
panel controllers.
In Dual Link, data transmit clock frequency of
135MHz, 67bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 1.1Gbytes per
second.
• Wide dot clock range suited for TV Signal(480i1080p), PC Signal(VGA-QXGA)
Dual LVDS port IN/Dual TTL port Out Mode:
8 - 135MHz(CLKOUT)
Dual LVDS port IN/Single TTL port Out Mode:
40 - 150MHz(CLKOUT)
• PLL requires No external components
• Flexible Input/Output mode
1. Single/Dual LVDS port IN /Single/Dual TTL port OUT
•
•
•
•
•
•
•
2. Double Edge output
50% output clock duty cycle
TTL clock edge selectable
TTL clock output timing programmable(3 step)
2 Output data mapping for simplifying PCB layout.
Power down mode
Low power single 3.3V CMOS design
144pin LQFP Exposed PAD
Block Diagram
LVDS INPUT
Port1
RC1 +/RD1 +/RE1 +/-
RA2 +/RB2 +/LVDS INPUT
Port2
RC2 +/RD2 +/RE2 +/-
RCLK +/(8 to 135MHz)
32
R1[9:0]
G1[9:0]
B1[9:0]
CONT1[2:1]
32
R2[9:0]
G2[9:0]
B2[9:0]
CONT2[2:1]
35
Data Formatter
1) DEMUX
2) MUX
3) DDR
RB1 +/-
SERIAL TO PARALLEL
RA1 +/-
SERIAL TO PARALLEL
LVDS INPUT
35
3
TTL OUTPUT
Port1
TTL OUTPUT
Port2
Hsync
Vsync
DE
RECEIVER CLOCK OUT
(8 to 150MHz)
PLL
/PDWN
MODE[2:0]
DK
R/F
O/E
MAP
Copyright©2012 THine Electronics, Inc.
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THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PGND
PVCC
VCC
CONT12
CONT11
DE
VSYNC
HSYNC
B19
B18
GND
VCC
B17
B16
B15
B14
B13
B12
B11
GND
VCC
B10
G19
G18
G17
G16
G15
GND
VCC
G14
G13
G12
G11
G10
R19
R18
Pin Out
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
TSSOP144
Exposed PAD
Top View
145GND(Exposed PAD)
R17
GND
VCC
R16
R15
R14
R13
R12
R11
R10
CGND
CVCC
CLKOUT
GND
GND
VCC
CONT22
CONT21
GND
VCC
B29
B28
B27
B26
B25
GND
VCC
B24
B23
B22
B21
B20
G29
GND
VCC
G28
PGND
PVCC
Reserved
/PDWN
MODE0
MODE1
DK
R/F
OE
MODE2
MAP
VCC
GND
R20
R21
R22
R23
R24
R25
R26
VCC
GND
R27
R28
R29
G20
G21
VCC
VCC
GND
G22
G23
G24
G25
G26
G27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LGND
RA1RA1+
RB1RB1+
LVCC
LGND
RC1RC1+
RCLKRCLK+
LVCC
LGND
RD1RD1+
RE1RE1+
LVCC
LGND
RA2RA2+
RB2RB2+
LVCC
LGND
RC2RC2+
LGND
LGND
LVCC
LGND
RD2RD2+
RE2RE2+
LGND
Copyright©2012 THine Electronics, Inc.
2/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Pin Description
Pin Name
Pin #
Type
RA1+, RA1-
111, 110
LVDS IN
RB1+, RB1-
113, 112
LVDS IN
RC1+, RC1-
117, 116
LVDS IN
RD1+, RD1-
123, 122
LVDS IN
RE1+, RE1-
125, 124
LVDS IN
RCLK+, RCLK-
119, 118
LVDS IN
RA2+, RA2-
129, 128
LVDS IN
RB2+, RB2-
131, 130
LVDS IN
RC2+, RC2-
135, 134
LVDS IN
RD2+, RD2-
141, 140
LVDS IN
RE2+, RE2-
143, 142
LVDS IN
R19 ~ R10
74 - 72, 69 - 63
OUT
G19 ~ G10
86 - 82, 79 - 75
OUT
B19 ~ B10
R29 ~ R20
G29 ~ G20
100, 99,
96-90, 87
25-23, 20-14
40, 37 - 31,
27, 26
B29 ~ B20
52 - 48, 45 - 41
CONT11,CONT12
104, 105
CONT21,CONT22
55, 56
DE
Description
The 1st Link. The 1st pixel input data when Dual Link.
LVDS Clock Input.
The 2nd Link. These pins are disabled when Single Link.
The 1st Pixel Data Outputs.
OUT
OUT
OUT
The 2nd Pixel Data Outputs.
OUT
OUT
User defined data output
103
OUT
Data Enable Output.
VSYNC
102
OUT
Vsync Output.
HSYNC
101
OUT
Hsync Output.
CLKOUT
60
OUT
Clock Output.
Power down and Output Control.(Table1)
/PDWN
4
IN
H: Normal operation
L: Power down
Pixel Data Mode.
MODE1, MODE0
6, 5
Copyright©2012 THine Electronics, Inc.
IN
MODE1
H
H
L
L
3/23
MODE0
H
L
H
L
Mode
Single Link (Single-in/Single-out)
Single Link (Single-in/Dual-out)
Dual Link (Dual-in/Single-out)
Dual Link (Dual-in/Dual-out)
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Pin Description (Continued)
Pin Name
Pin #
Type
Description
Output Clock Delay Timing Select.
tDOUT=Output Data Cycle
MODE[1:0
]
DK
L
DK
7
LL
HH
HL
IN
LH
R/F
8
IN
OE
9
IN
Offset
[nsec]
0
M
t DOUT
– 6 -------------28
H
t DOUT
6 --------------28
L
0
M
t DOUT
– 7 -------------28
H
t DOUT
7 -------------28
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge.
Output Enable.(Table1)
H: Output enable, L: Output disable
DDR function enable.
The use of this function depends on the setting of
MODE<1:0>.
MODE<1:0>=LH(Dual-in/Single-out Mode)
MODE2
10
IN
H: DDR (Double Edge Output) function enable.
L: DDR (Double Edge Output) function disable.
MODE<1:0>=Other
Must be tied to GND
LVDS mapping table select. See Fig9,10 and Table2 - 9.
MAP
11
IN
H: Mapping Mode1
L: Mapping Mode2
Reserved
3
IN
Must be tied to VCC.
VCC
12, 21, 28, 29,
38, 46, 53, 57,
70, 80, 88, 97,
106
Power
Power Supply Pins for TTL outputs and digital circuitry.
Ground
Ground Pins for TTL outputs and digital circuitry.
Power
Power Supply Pins for LVDS inputs.
Ground
Ground Pins for LVDS inputs.
13, 22, 30, 39,
GND
LVCC
47, 54, 58, 59,
71, 81, 89,
98,145
114, 120, 126,
132, 138
109, 115, 121,
LGND
127, 133, 136,
137, 139, 144
PVCC
2, 107
Power
Power Supply Pin for PLL circuitry.
PGND
1, 108
Ground
Ground Pin for PLL circuitry.
CVCC
61
Power
Power Supply Pins for TTL output of CLKOUT.
CGND
62
Ground
Ground Pins for TTL output of CLKOUT
Copyright©2012 THine Electronics, Inc.
4/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Pin Description (Continued)
Table 1. Output Control
PD
OE
Data Outputs
(Rxn)
CLKOUT
L
L
Hi-Z
Hi-Z
L
H
All Low
Fixed Low
H
L
Hi-Z
Hi-Z
H
H
Data Out
CLK Out
Absolute Maximum Ratings
Supply Voltage (VCC)
-0.3V ~ +4.0V
CMOS/TTL Input Voltage
-0.3V ~ (VCC + 0.3V)
CMOS/TTL Output Voltage
-0.3V ~ (VCC + 0.3V)
LVDS Receiver Input Voltage
-0.3V ~ (VCC + 0.3V)
Output Current
-30mA ~ 30mA
Junction Temperature
+125 °C
Storage Temperature Range
-55 °C ~ +125 °C
Reflow Peak Temperature / Time
+260 °C / 10sec.
Maximum Power Dissipation @+25 °C
4.4W
Copyright©2012 THine Electronics, Inc.
5/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Recommended Operating Conditions
CLK
Parameter
Min.
Typ
Max
Units
All Supply Voltage
3.0
3.3
3.6
V
Operating Ambient Temperature
0
70
°C
MODE<1:0>=LL
LVDS Input
8
135
MHz
Dual-in/Dual-out
Output
8
135
MHz
Single Edge Output
LVDS Input
20
75
MHz
MODE<1:0>=LH
(MODE2=L)
Output
40
150
MHz
Dual-in/Single-out
Double Edge Output
LVDS Input
20
75
MHz
(MODE2=H)
Output
20
75
MHz
MODE<1:0>=HL
LVDS Input
8
135
MHz
Single-in/Dual-out
Output
4
67.5
MHz
MODE<1:0>=HH
LVDS Input
8
135
MHz
Single-in/Single-out
Output
8
135
MHz
Differential CLKIN High Time (tRCIH) (Fig1)
t RCIP
2 ----------------7
t RCIP
5 ----------------7
nsec
Differential CLKIN Low Time (tRCIL) (Fig1)
t
RCIP
2 ----------------7
t
RCIP
5 ----------------7
nsec
Frequency
tRCIH
tRCIL
Vdiff = 0V
Vdiff = 0V
Vdiff = 0V
RCLK+
(Differential)
tRCIP
Fig1. Differential CLKIN
Copyright©2012 THine Electronics, Inc.
6/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Electrical Characteristics
CMOS/TTL DC Specifications
VCC=VCC=PVCC=LVCC=CVCC
Symbol
Parameter
Conditions
VIH
High Level Input Voltage
/PDWN, MODE[2:0]
VIL
Low Level Input Voltage
R/F, OE, MAP Pin
VIH3
High Level Input Voltage
VIM3
Middle Level Input Voltage
VIL3
Low Level Input Voltage
VOH
High Level Output Voltage
IOH= -8mA
VOL
Low Level Output Voltage
IOL= 8mA
3-Level Inputs
(DK Pin)
Min.
Typ
Max
Units
2.0
VCC
V
GND
0.8
V
0.8VCC
VCC
V
0.6VCC
0.4VCC
V
GND
0.2VCC
V
2.4
V
0.4
V
± 10
μA
± 10
μA
/PDWN, MODE[2:0]
IIL
Input Leakage Current
R/F, OE, MAP Pin
0V ≤ V IN ≤ V CC
3-Level Inputs
IIL3
3-Level Input Leakage Current
(DK Pin)
0V ≤ V IN ≤ V CC
LVDS Receiver DC Specifications
VCC=VCC=PVCC=LVCC=CVCC
Symbol
Parameter
Conditions
VTH
Differential Input High Threshold
VIC= 1.2V
VTL
Differential Input Low Threshold
VIC= 1.2V
IILD
Differential Input Leakage Current
VIN= 2.4V / 0V
Copyright©2012 THine Electronics, Inc.
7/23
Min.
Typ.
Max.
Units
100
mV
-100
mV
30
μA
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Electrical Characteristics (Continued)
Supply Current
VCC=VCC=PVCC=LVCC=CVCC
Symbol
Parameter
Receiver
IRCCW
Supply Current
(Worst Case
Pattern) Fig2.
Condition
Typ.
Max.
Units
CLKOUT=65MHz
MODE<1:0>=HH
201
mA
CLKOUT=85MHz
Single-in/Single-out
248
mA
CLKOUT=135MHz
MODE2=L
364
mA
CLKOUT=32.5MHz
MODE<1:0>=HL
138
mA
CLKOUT=42.5MHz
Single-in/
164
mA
CLKOUT=67.5MHz
Dual-out
233
mA
CLKOUT=65MHz
MODE<1:0>=LH
146
mA
CLKOUT=85MHz
Dual-in/Single-out
165
mA
MODE2=L
210
mA
CLKOUT=150MHz
DDR Output Off
223
mA
CLKOUT=32.5MHz
MODE<1:0>=LH
147
mA
CLKOUT=42.5MHz
Dual-in/Single-out
165
mA
CLKOUT=67.5MHz
MODE2=H
205
mA
DDR Output On
217
mA
366
mA
453
mA
671
mA
50
μA
CLKOUT=135MHz
CL=8pF
CLKOUT=75MHz
CLKIN=65MHz
MODE<1:0>=LL
CLKIN=85MHz
Dual-in/Dual-out
CLKIN=135MHz
Receiver
IRCCS
Power Down
/PDWN = L
Supply Current
Checker Pattern
CLKOUT
Rxn, Gxn, Bxn
x = 1,2
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
CONT21,22
Fig2. Test Pattern
Copyright©2012 THine Electronics, Inc.
8/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Electrical Characteristics (Continued)
Output load limitation
Output load is limited so that Junction temperature is not over 125 °C
calculating formula
Tj = Ta + θja * P
P = VCC * (IOUTDT + IOUTCK + ICORE)
IOUTDT = 1/2 * FCLK * VCC * CLOAD * n
IOUTCK = FCLK * VCC * CLOAD
Tj
: Junction temperature
Ta : Ambient temperature
θja : Package thermal resistance = 22 [ °C /W]
ICORE: Supply Current except all output buffers = 520mA
IOUTDT: Supply Current only output buffers of data output.
(R1,G1,B1,R2,G2,B2,HSYNC,VSYNC,DE,CONT11,CONT12,CONT21,CONT22)
IOUTCK: Supply Current only output buffer of CLKOUT.
FCLK : CLKOUT Frequency
n
: 67 (Number of data output pin)
Load Limitation
15
14
Output Load[pF]
13
12
11
10
9
8
100
105
110
115
120
125
130
135
Frequency[MHz]
Copyright©2012 THine Electronics, Inc.
9/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Switching Characteristics
VCC=VCC=PVCC=LVCC=CVCC
Symbol
Parameter
Min.
Typ.
Max.
Units
tRCP
CLKOUT Period (Fig4)
6.67
T
250
ns
tRCH
tRCL
CLKOUT High Time
(Fig4)
CLKOUT Low Time
(Fig4)
T
--2
ns
T
--2
ns
tDOUT
TTL Data OUT Period (Fig5,6)
6.67
tRS
TTL Data Setup to CLKOUT(Fig5,6)
0.45tDOUT -0.45
ns
tRH
TTL Data Hold to CLKOUT(Fig5,6)
0.45tDOUT -0.45
ns
tTLH
tTHL
tSK
tRIP1
TTL Low to High Transition Time
(Fig 3)
TTL High to Low Transition Time
(Fig 3)
T
250
ns
0.7
1.0
ns
0.7
1.0
ns
tRCIP=65MHz
-650
0
650
ps
Receiver Skew
Margin
tRCIP=85MHz
-450
0
450
ps
(Fig7)
tRCIP=108MHz
-250
0
250
ps
tRCIP=135MHz
-170
0
170
ps
-tSK
0
+tSK
ns
Input Data Position0
(Fig7)
tRIP0
Input Data Position1 (Fig7)
t RCIP
-------------- – t SK
7
t RCIP
-------------7
t RCIP
-------------- + t SK
7
ns
tRIP6
Input Data Position2 (Fig7)
t RCIP
- – t SK
2 ------------7
t RCIP
2 ------------7
t RCIP
- + t SK
2 ------------7
ns
tRIP5
Input Data Position3 (Fig7)
t RCIP
3 ------------- – t SK
7
t RCIP
3 ------------7
t RCIP
3 ------------- + t SK
7
ns
tRIP4
Input Data Position4 (Fig7)
t RCIP
4 ------------- – t SK
7
t RCIP
4 ------------7
t RCIP
4 ------------- + t SK
7
ns
tRIP3
Input Data Position5 (Fig7)
t RCIP
- – t SK
5 ------------7
t RCIP
5 ------------7
t RCIP
- + t SK
5 ------------7
ns
tRIP2
Input Data Position6 (Fig7)
t RCIP
6 ------------- – t SK
7
t RCIP
6 ------------7
t RCIP
6 ------------- + t SK
7
ns
tRPLL
Phase Lock Loop Set (Fig8)
10.0
ms
89.7
94
ns
7.4
125.0
ns
tRCD
tRCIP
RCLK +/- to CLK OUT Delay (Fig9)
MODE<1:0>=LL DK=L, 75MHz
CLKIN Period (Fig7)
tDEINT
MODE<1:0>=HL
tDEH
tDEL
(Single IN/ Dual
OUT Mode) Only
tRCIP*(2n)
DE input period
(Fig9-1)
4tRCIP
DE input High
time (Fig9-1)
2tRCIP
ns
DE input Low
time (Fig9-1)
2tRCIP
ns
Copyright©2012 THine Electronics, Inc.
10/23
n= integer
ns
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
AC Timing Diagrams
TTL Output
80%
80%
CL=8pF
20%
20%
TTL Output Load
tTHL
tTLH
Fig3. CMOS/TTL Output Load and Transition Time
tRCP
CLKOUT
tRCH
VCC/2
tRCL
VCC/2
VCC/2
VCC/2
Fig4. CLKOUT Period and High/Low Time
tRCP
R/F=L
CLKOUT
DK=L
VCC/2
VCC/2
VCC/2
R/F=H
R/F=H
CLKOUT
DK=M
VCC/2
R/F=L
t DOUT
6 -------------------28
t
DOUT
or 7 ------------------28
R/F=L
CLKOUT
DK=H
VCC/2
R/F=H
t
DOUT
6 -------------------28
Rxn, Gxn, Bxn
x = 1,2
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
CONT21,22
t
DOUT
or 7 -------------------
tRS
28
tRH
VCC/2
VCC/2
tDOUT
Fig5. CLKOUT Position and Setup/Hold Timing
Copyright©2012 THine Electronics, Inc.
11/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
AC Timing Diagrams (Continued)
tRCP
R/F=L
CLKOUT
DK=L
VCC/2
VCC/2
VCC/2
R/F=H
R/F=L
CLKOUT
DK=M
VCC/2
VCC/2
R/F=H
t
DOUT
7 -------------------28
t
DOUT
7 -------------------28
R/F=L
CLKOUT
DK=H
VCC/2
VCC/2
VCC/2
R/F=H
t
DOUT
7 -------------------28
t DOUT
7 -------------------28
R1n, G1n, B1n
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
tRS
VCC/2
tRH
1st Pixel
Data
tRS
tRH
2nd Pixel
Data
VCC/2
tDOUT
VCC/2
tDOUT
Fig6. CLKOUT Position and Setup/Hold Timing for Double Edge Output Mode
MODE<1:0>=LH, MODE2=H
tRCIP
Vdiff = 0V
Vdiff = 0V
RCLK+
(Differential)
Ryx+/x=1,2
y= A, B, C, D, E
Ryx3’
Ryx2’
Ryx1’
Ryx0’
Ryx6
Ryx5
Ryx4
Previous Cycle
Ryx3
Ryx2
Ryx1
Current Cycle
Ryx0
Ryx6’’
Next Cycle
tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
Fig7. LVDS Input Data Position
Copyright©2012 THine Electronics, Inc.
12/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
AC Timing Diagrams (Continued)
RCLK+/-
2.0V
/PDWN
tRPLL
CLKOUT
VCC/2
Fig8. PLL Lock Loop Set Time
RCLK+
Vdiff = 0V
Ryx+/x=1,2
y= A, B, C, D, E
Note:
1) Vdiff = (RCLK+) - (RCLK-)
Current Data
tRCD
CLKOUT
VCC/2
R/F=L
R1n, G1n, B1n
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
Current Data
Fig9. RCLK +/- to CLK OUT Delay
RCLK+
DE
DE
DE
DE
DE
DE
RC1+
tDEH
tDEL
tDEINT
Fig9-1. Single IN / Dual OUT mode RC1(DE) input timing
Copyright©2012 THine Electronics, Inc.
13/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Output Data Mapping
Table2. Output Color Data naming rule
X
Y
Z
Description
X=R
Red Color Data
X=G
Green Color Data
X=B
Blue Color Data
Y= None
Single Pixel
Y=O
Dual Pixel
Y=E
Z=0-9
1st Pixel Data
2nd Pixel Data
Bit number 0: LSB (Least Significant Bit)
9: MSB (Most Significant Bit)
Table3. TTL/CMOS Output Data Mapping (Single-out mode, MODE0=H)
Data Signals
30-bit
24-bit
Receiver Output Pin Names
18-bit
R0
30-bit
24-bit
18-bit
R10
R1
R11
R2
R0
R12
R12
R3
R1
R13
R13
R4
R2
R0
R14
R14
R14
R5
R3
R1
R15
R15
R15
R6
R4
R2
R16
R16
R16
R7
R5
R3
R17
R17
R17
R8
R6
R4
R18
R18
R18
R9
R7
R5
R19
R19
R19
G0
G10
G1
G11
G2
G0
G12
G12
G3
G1
G4
G2
G0
G13
G13
G14
G14
G14
G5
G3
G1
G15
G15
G15
G6
G4
G2
G16
G16
G16
G7
G8
G5
G3
G17
G17
G17
G6
G4
G18
G18
G18
G9
G7
G5
G19
G19
G19
B0
B10
B1
B11
B2
B0
B12
B12
B3
B1
B13
B13
B4
B2
B0
B14
B14
B14
B5
B3
B1
B15
B15
B15
B6
B4
B2
B16
B16
B16
B7
B5
B3
B17
B17
B17
B8
B6
B4
B18
B18
B18
B9
B7
B5
B19
B19
B19
Copyright©2012 THine Electronics, Inc.
14/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Output Data Mapping (Continued)
Table4. TTL/CMOS Output Data Mapping (Dual-out mode, MODE0=L)
1st Pixel Data
Data Signals
30-bit
24-bit
2nd Pixel Data
Receiver Output Pin
Names
18-bit
30-bit
24-bit
18-bit
Receiver Output Pin
Names
Data Signals
30-bit
24-bit
18-bit
30-bit
RE0
R10
RO0
R20
RE1
R11
RO1
R22
24-bit
18-bit
RE2
RE0
R12
R12
RO2
RO0
R22
R22
RE3
RE1
R13
R13
RO3
RO1
R23
R23
RE4
RE2
RE0
R14
R14
R14
RO4
RO2
RO0
R24
R24
R24
RE5
RE3
RE1
R15
R15
R15
RO5
RO3
RO1
R25
R25
R25
RE6
RE4
RE2
R16
R16
R16
RO6
RO4
RO2
R26
R26
R26
RE7
RE5
RE3
R17
R17
R17
RO7
RO5
RO3
R27
R27
R27
RE8
RE6
RE4
R18
R18
R18
RO8
RO6
RO4
R28
R28
R28
RE9
RE7
RE5
R19
R19
R19
RO9
RO7
RO5
R29
R29
R29
GE0
G10
GO0
G20
GE1
G11
GO1
G22
GE2
GE0
G12
G12
GO2
GO0
G22
G22
GE3
GE1
G13
G13
GO3
GO1
G23
G23
GE4
GE2
GE0
G14
G14
G14
GO4
GO2
GO0
G24
G24
G24
GE5
GE3
GE1
G15
G15
G15
GO5
GO3
GO1
G25
G25
G25
GE6
GE4
GE2
G16
G16
G16
GO6
GO4
GO2
G26
G26
G26
GE7
GE5
GE3
G17
G17
G17
GO7
GO5
GO3
G27
G27
G27
GE8
GE6
GE4
G18
G18
G18
GO8
GO6
GO4
G28
G28
G28
GE9
GE7
GE5
G19
G19
G19
GO9
GO7
GO5
G29
G29
G29
BE0
B10
BO0
B20
BE1
B11
BO1
B22
BE2
BE0
B12
B12
BO2
BO0
B22
B22
BE3
BE1
B13
B13
BO3
BO1
B23
B23
BE4
BE2
BE0
B14
B14
B14
BO4
BO2
BO0
B24
B24
B24
BE5
BE3
BE1
B15
B15
B15
BO5
BO3
BO1
B25
B25
B25
BE6
BE4
BE2
B16
B16
B16
BO6
BO4
BO2
B26
B26
B26
BE7
BE5
BE3
B17
B17
B17
BO7
BO5
BO3
B27
B27
B27
BE8
BE6
BE4
B18
B18
B18
BO8
BO6
BO4
B28
B28
B28
BE9
BE7
BE5
B19
B19
B19
BO9
BO7
BO5
B29
B29
B29
Copyright©2012 THine Electronics, Inc.
15/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
LVDS Input Data Mapping
Previous Cycle
(2nd Pixel Data)
Current Cycle
(1st Pixel Data)
RCLK+
Rx1+/Rx11(n-1) Rx10(n-1) Rx16(n)
x= A, B, C, D, E
Rx15(n)
Current Cycle
(1st Pixel Data)
Rx14(n)
Rx13(n)
Rx12(n)
Rx11(n)
Rx10(n)
Rx16(n+1)
Next Cycle
(2nd Pixel Data)
RCLK+
Rx1+/Rx11(n)
x= A, B, C, D, E
Rx10(n)
Rx16(n+1) Rx15(n+1) Rx14(n+1) Rx13(n+1) Rx12(n+1) Rx11(n+1) Rx10(n+1) Rx16(n+2)
Fig10. LVDS Inputs Mapped to TTL Data Outputs
MODE1= H (Single-in Mode)
Previous Cycle
Current Cycle
RCLK+
Rx1+/Rx11(n-1) Rx10(n-1) Rx16(n)
x= A, B, C, D, E
Rx15(n)
Rx14(n)
Rx13(n)
Rx12(n)
Rx11(n)
Rx10(n)
Rx16(n+1)
Rx2+/x= A, B, C, D, E Rx21(n-1) Rx20(n-1) Rx26(n)
Rx25(n)
Rx24(n)
Rx23(n)
Rx22(n)
Rx21(n)
Rx20(n)
Rx26(n+1)
Fig11. LVDS Inputs Mapped to TTL Data Outputs
MODE1= L (Dual-in Mode)
Copyright©2012 THine Electronics, Inc.
16/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
LVDS Input Data Mapping (Continued)
Table5. LVDS Input Data Mapping (Single-in/Single-out, MODE<1:0>=HH)
LVDS
Mapping Mode1
Input Data
(Output Pin Name)
Mapping Mode2
(Output Pin Name)
RA10
R14
R12
RA11
R15
R13
RA12
R16
R14
RA13
R17
R15
RA14
R18
R16
RA15
R19
R17
RA16
G14
G12
RB10
G15
G13
RB11
G16
G14
RB12
G17
G15
RB13
G18
G16
RB14
G19
G17
RB15
B14
B12
RB16
B15
B13
RC10
B16
B14
RC11
B17
B15
RC12
B18
B16
RC13
B19
B17
RC14
HSYNC
HSYNC
RC15
VSYNC
VSYNC
RC16
DE
DE
RD10
R12
R18
RD11
R13
R19
RD12
G12
G18
RD13
G13
G19
RD14
B12
B18
RD15
B13
B19
RD16
CONT11
CONT11
RE10
R10
R10
RE11
R11
R11
RE12
G10
G10
RE13
G11
G11
RE14
B10
B10
RE15
B11
B11
RE16
CONT12
CONT12
Copyright©2012 THine Electronics, Inc.
17/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
LVDS Input Data Mapping (Continued)
Table6. LVDS Input Data Mapping (Single-in/Dual-out, MODE<1:0>=HL)
1st Pixel Data
LVDS
2nd Pixel Data
Mapping Mode1
Mapping Mode2
(Output Pin Name)
(Input Pin Name)
RA10(n)
R14
R12
RA11(n)
R15
RA12(n)
LVDS
Mapping Mode1
Mapping Mode2
(Output Pin Name)
(Output Pin Name)
RA10(n+1)
R24
R22
R13
RA11(n+1)
R25
R23
R16
R14
RA12(n+1)
R26
R24
RA13(n)
R17
R15
RA13(n+1)
R27
R25
RA14(n)
R18
R16
RA14(n+1)
R28
R26
RA15(n)
R19
R17
RA15(n+1)
R29
R27
RA16(n)
G14
G12
RA16(n+1)
G24
G22
Input Data
(1st Pixel Data)
Input Data
(1st Pixel Data)
RB10(n)
G15
G13
RB10(n+1)
G25
G23
RB11(n)
G16
G14
RB11(n+1)
G26
G24
RB12(n)
G17
G15
RB12(n+1)
G27
G25
RB13(n)
G18
G16
RB13(n+1)
G28
G26
RB14(n)
G19
G17
RB14(n+1)
G29
G27
RB15(n)
B14
B12
RB15(n+1)
B24
B22
RB16(n)
B15
B13
RB16(n+1)
B25
B23
RC10(n)
B16
B14
RC10(n+1)
B26
B24
RC11(n)
B17
B15
RC11(n+1)
B27
B25
RC12(n)
B18
B16
RC12(n+1)
B28
B26
RC13(n)
B19
B17
RC13(n+1)
B29
B27
RC14(n)
HSYNC
HSYNC
RC14(n+1)
HSYNC
HSYNC
RC15(n)
VSYNC
VSYNC
RC15(n+1)
VSYNC
VSYNC
RC16(n)
DE
DE
RC16(n+1)
DE
DE
RD10(n)
R12
R18
RD10(n+1)
R22
R28
RD11(n)
R13
R19
RD11(n+1)
R23
R29
RD12(n)
G12
G18
RD12(n+1)
G22
G28
RD13(n)
G13
G19
RD13(n+1)
G23
G29
RD14(n)
B12
B18
RD14(n+1)
B22
B28
RD15(n)
B13
B19
RD15(n+1)
B23
B29
RD16(n)
CONT11
CONT11
RD16(n+1)
CONT21
CONT21
RE10(n)
R10
R10
RE10(n+1)
R20
R20
RE11(n)
R11
R11
RE11(n+1)
R21
R21
RE12(n)
G10
G10
RE12(n+1)
G20
G20
RE13(n)
G11
G11
RE13(n+1)
G21
G21
RE14(n)
B10
B10
RE14(n+1)
B20
B20
RE15(n)
B11
B11
RE15(n+1)
B21
B21
RE16(n)
CONT12
CONT12
RE16(n+1)
CONT22
CONT22
Copyright©2012 THine Electronics, Inc.
18/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
LVDS Input Data Mapping (Continued)
Table7. LVDS Input Data Mapping (Dual-in/Single-out DDR On or Off, MODE<1:0>=LH, MODE2=H or L)
1st Pixel Data
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin Name)
2nd Pixel Data
Mapping Mode2
(Output Pin Name)
LVDS
Input Data
(2nd Pixel Data)
Mapping Mode1
(Output Pin Name)
Mapping Mode2
(Output Pin Name)
RA10
R14(n)
R12(n)
RA20
R14(n+1)
R12(n+1)
RA11
R15(n)
R13(n)
RA21
R15(n+1)
R13(n+1)
RA12
R16(n)
R14(n)
RA22
R16(n+1)
R14(n+1)
RA13
R17(n)
R15(n)
RA23
R17(n+1)
R15(n+1)
RA14
R18(n)
R16(n)
RA24
R18(n+1)
R16(n+1)
RA15
R19(n)
R17(n)
RA25
R19(n+1)
R17(n+1)
RA16
G14(n)
G12(n)
RA26
G14(n+1)
G12(n+1)
RB10
G15(n)
G13(n)
RB20
G15(n+1)
G13(n+1)
RB11
G16(n)
G14(n)
RB21
G16(n+1)
G14(n+1)
RB12
G17(n)
G15(n)
RB22
G17(n+1)
G15(n+1)
RB13
G18(n)
G16(n)
RB23
G18(n+1)
G16(n+1)
RB14
G19(n)
G17(n)
RB24
G19(n+1)
G17(n+1)
RB15
B14(n)
B12(n)
RB25
B14(n+1)
B12(n+1)
RB16
B15(n)
B13(n)
RB26
B15(n+1)
B13(n+1)
RC10
B16(n)
B14(n)
RC20
B16(n+1)
B14(n+1)
RC11
B17(n)
B15(n)
RC21
B17(n+1)
B15(n+1)
RC12
B18(n)
B16(n)
RC22
B18(n+1)
B16(n+1)
RC13
B19(n)
B17(n)
RC23
B19(n+1)
B17(n+1)
RC14
HSYNC(n)
HSYNC(n)
RC24
HSYNC(n+1)
HSYNC(n+1)
RC15
VSYNC(n)
VSYNC(n)
RC25
VSYNC(n+1)
VSYNC(n+1)
RC16
DE(n)
DE(n)
RC26
DE(n+1)
DE(n+1)
RD10
R12(n)
R18(n)
RD20
R12(n+1)
R18(n+1)
RD11
R13(n)
R19(n)
RD21
R13(n+1)
R19(n+1)
RD12
G12(n)
G18(n)
RD22
G12(n+1)
G18(n+1)
RD13
G13(n)
G19(n)
RD23
G13(n+1)
G19(n+1)
RD14
B12(n)
B18(n)
RD24
B12(n+1)
B18(n+1)
RD15
B13(n)
B19(n)
RD25
B13(n+1)
B19(n+1)
RD16
CONT11(n)
CONT11(n)
RD26
CONT11(n+1)
CONT11(n+1)
RE10
R10(n)
R10(n)
RE20
R10(n+1)
R10(n+1)
RE11
R11(n)
R11(n)
RE21
R11(n+1)
R11(n+1)
RE12
G10(n)
G10(n)
RE22
G10(n+1)
G10(n+1)
RE13
G11(n)
G11(n)
RE23
G11(n+1)
G11(n+1)
RE14
B10(n)
B10(n)
RE24
B10(n+1)
B10(n+1)
RE15
B11(n)
B11(n)
RE25
B11(n+1)
B11(n+1)
RE16
CONT12(n)
CONT12(n)
RE26
CONT12(n+1)
CONT12(n+1)
Copyright©2012 THine Electronics, Inc.
19/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
LVDS Input Data Mapping (Continued)
Table8. LVDS Input Data Mapping (Dual-in/Dual-out, MODE<1:0>=LL)
1st Pixel Data
LVDS
Mapping Mode1
2nd Pixel Data
(Output Pin Name)
Mapping Mode2
(Output Pin Name)
RA10
R14
R12
RA11
R15
RA12
LVDS
Mapping Mode1
(Output Pin Name)
Mapping Mode2
(Output Pin Name)
RA20
R24
R22
R13
RA21
R25
R23
R16
R14
RA22
R26
R24
RA13
R17
R15
RA23
R27
R25
RA14
R18
R16
RA24
R28
R26
RA15
R19
R17
RA25
R29
R27
RA16
G14
G12
RA26
G24
G22
RB10
G15
G13
RB20
G25
G23
RB11
G16
G14
RB21
G26
G24
RB12
G17
G15
RB22
G27
G25
RB13
G18
G16
RB23
G28
G26
RB14
G19
G17
RB24
G29
G27
RB15
B14
B12
RB25
B24
B22
RB16
B15
B13
RB26
B25
B23
RC10
B16
B14
RC20
B26
B24
Input Data
(1st Pixel Data)
Input Data
(2nd Pixel Data)
RC11
B17
B15
RC21
B27
B25
RC12
B18
B16
RC22
B28
B26
RC13
B19
B17
RC23
B29
B27
RC14
HSYNC
HSYNC
RC24
RC15
VSYNC
VSYNC
RC25
RC16
DE
DE
RC26
RD10
R12
R18
RD20
R22
R28
RD11
R13
R19
RD21
R23
R29
RD12
G12
G18
RD22
G22
G28
RD13
G13
G19
RD23
G23
G29
RD14
B12
B18
RD24
B22
B28
RD15
B13
B19
RD25
B23
B29
RD16
CONT11
CONT11
RD26
CONT21
CONT21
RE10
R10
R10
RE20
R20
R20
RE11
R11
R11
RE21
R21
R21
RE12
G10
G10
RE22
G20
G20
RE13
G11
G11
RE23
G21
G21
RE14
B10
B10
RE24
B20
B20
RE15
B11
B11
RE25
B21
B21
RE16
CONT12
CONT12
RE26
CONT22
CONT22
Copyright©2012 THine Electronics, Inc.
20/23
N/A
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Note
1)Power On Sequence
Power on LVDS-Tx after THC63LVD1024.
2)Cable Connection and Disconnection
Don't connect and disconnect the LVDS cable, when the power is supplied to the system.
3)GND Connection
Connect the each GND of the PCB which LVDS-Tx and THC63LVD1024 on it. It is better for EMI reduction to place
GND cable as close to LVDS cable as possible.
4)Multi Drop Connection
Multi drop connection is not recommended.
TCLK+
LVDS-Tx
THC63LVD1024
TCLK-
THC63LVD1024
5)Asynchronous use
Asynchronous use such as following system is not recommended.
CLKOUT
CLKOUT
TCLK+
LVDS-Tx
DATA
TCLK-
THC63LVD1024
!
IC
CLKOUT
TCLK+
LVDS-Tx
DATA
TCLK-
THC63LVD1024
DATA
IC
DATA
.
TCLK+
TCLK-
CLKOUT
THC63LVD1024
!
IC
TCLK+
TCLK-
Copyright©2012 THine Electronics, Inc.
THC63LVD1024
21/23
DATA
IC
DATA
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Package
22.00 BSC.
1.40～1.60
20.00 BSC.
1.40 +/-0.05
0.05～0.15
73
108
72
22.00 BSC.
20.00 BSC.
109
1.00 REF
THC63LVD1024
37
144
0.09～0.20
36
1
0.20 +0.07/-0.03
0.08 M
0.50 BSC.
1 PIN INDEX
TOP VIEW
S SEATING PLANE
0°～7°
0.10 S
7.20
1
36
37
109
72
7.20
144
108
73
EXPOSED PAD
BOTTOM VIEW
11°～13°
0.08 R MIN
0.08～0.20R
11°～13°
GAGE PLANE
0.25ｍｍ
0.20 MIN
0.60 +/-0.15
Unit：mm
Exposed PAD is GND and must be soldered to PCB.
Copyright©2012 THine Electronics, Inc.
22/23
THine Electronics, Inc.
THC63LVD1024_Rev.2.5_E
Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not
always apply to the customer's design. We are not responsible for possible errors and omissions
in this material. Please note if errors or omissions should be found in this material, we may not
be able to correct them immediately.
3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to
third parties the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this
product, we will be exempted from the responsibility unless it directly relates to the production
process or functions of the product.
5. This product is presumed to be used for general electric equipment, not for the applications
which require very high reliability (including medical equipment directly concerning people's
life, aerospace equipment, or nuclear control equipment). Also, when using this product for the
equipment concerned with the control and safety of the transportation means, the traffic signal
equipment, or various Types of safety equipment, please do it after applying appropriate
measures to the product.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur
with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you
are encouraged to have sufficiently redundant or error preventive design applied to the use of
the product so as not to have our product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Customers are asked, if required, to judge by themselves if this product falls under the category
of strategic goods under the Foreign Exchange and Foreign Trade Control Law.
THine Electronics, Inc.
E-mail: [email protected]
Copyright©2012 THine Electronics, Inc.
23/23
THine Electronics, Inc.