5962-9855501VPA

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
REV
SHEET
REV
SHEET
15
16
17
REV STATUS
REV
OF SHEETS
SHEET
PMIC N/A
PREPARED BY
1
2
3
4
5
RICK OFFICER
STANDARD
MICROCIRCUIT
DRAWING
6
7
8
9
10
11
12
13
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
RAJESH PITHADIA
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
CHARLES F. SAFFLE
DRAWING APPROVAL DATE
MICROCIRCUIT, LINEAR, PRECISION TIMER,
MONOLITHIC SILICON
10-07-08
REVISION LEVEL
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
5962-98555
1 OF 17
5962-E104-10
14
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
P
A
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
98555
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
SE555
Precision timer
01
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device requirements documentation
Device class
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
P
Descriptive designator
Terminals
GDIP1-T8 or CDIP2-T8
8
Package style
Dual-in-line
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
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APR 97
SIZE
5962-98555
A
REVISION LEVEL
SHEET
2
1.3 Absolute maximum ratings. 1/
Positive supply voltage .................................................................................................
Discharge current ..........................................................................................................
Output sink current ........................................................................................................
Output source current ...................................................................................................
Maximum allowable power dissipation (PD) at TA = +125C ........................................
+18 V dc
+200 mA
+200 mA
-200 mA
370 mW
Junction temperature (TJ) .............................................................................................
Lead temperature (soldering, 60 seconds) ....................................................................
Storage temperature range ...........................................................................................
Thermal resistance, junction-to-case (JC) ...................................................................
+175C
+300C
-65C to +150C
45C/W
Thermal resistance, junction-to-ambient (JA) .............................................................. 135C/W
1.4 Recommended operating conditions.
Supply voltage range .................................................................................................... +4.5 V to +16.5 V
Breakdown voltage ....................................................................................................... 33.5 V
Ambient operating temperature range (TA) ................................................................... -55C to +125C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
_______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
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A
REVISION LEVEL
SHEET
3
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Block diagram and circuit operation table. The block diagram and circuit operation table shall be as specified on
figure 2.
3.2.4 Timing waveforms. Timing waveforms shall be as specified on figures 3, 4, 5, and 6.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
ambient operating temperature range.
3.3.1 Triggering. In the monostable mode, the device is triggered on the negative slope of a trigger pulse. The trigger pulse
must be of shorter duration than the “RC” time interval. The minimum pulse width is 1 microsecond (s).
3.3.2 Reset. In the monostable mode, the device may be reset (from VOH to VOL) on the negative slope of a reset pulse.
Once the reset is returned high, the output will remain low only of the trigger is high. If the trigger is low when reset is returned
high, the output will go high. The minimum reset pulse width is 2 s.
STANDARD
MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
SHEET
4
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 54 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
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APR 97
SIZE
5962-98555
A
REVISION LEVEL
SHEET
5
TABLE I. Electrical performance characteristics.
Test
Power supply current
Symbol
ICC
Conditions
-55C  TA +125C
unless otherwise specified
VCC = 4.5 V dc, RL = 
Group A
subgroups
Device
type
Limits
Min
1,2,3
01
VTR
Threshold voltage
ITR
VTH
1
VCC = 4.5 V dc
VCC = 16.5 V dc for
ITH
01
1.30
1.80
2
1.30
2.10
3
1.15
1.80
1
5.20
5.80
2
5.20
6.10
3
5.00
5.80
VOL
VCC = 4.5 V dc
01
-5.0
1
01
2.70
3.30
2,3
2.60
3.40
1
10.70
11.30
2,3
10.60
11.40
1,2
VCC = 16.5 V dc
VCC = 4.5 V dc, ISINK = 5 mA
01
1
01
nA
2.5
A
.250
V
.350
1,2
2.20
3
2.60
1,3
.150
2
.250
1,3
.500
ISINK = 50 mA
2
.700
VCC = 16.5 V dc,
1
2.20
2,3
2.80
ISINK = 50 mA
VCC = 16.5 V dc,
ISINK = 10 mA
VCC = 16.5 V dc,
ISINK = 100 mA
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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V
250
2,3
VCC = 4.5 V dc,
DSCC FORM 2234
APR 97
A
1,2,3
3
Low level output voltage
V
VTR = 5.0 V
VCC = 16.5 V dc
Threshold current
mA
20.0
VCC = 16.5 V dc
Trigger current
Max
5.0
VCC = 16.5 V dc, RL = 
Trigger voltage
Unit
SIZE
5962-98555
A
REVISION LEVEL
SHEET
6
TABLE I. Electrical performance characteristics – Continued.
Test
High level output voltage
Symbol
VOH
Conditions
-55C  TA +125C
unless otherwise specified
Group A
subgroups
ISOURCE = -100 mA
VCC = 16.5 V dc,
ISOURCE = -100 mA
01
Unit
Max
2.60
3
2.20
1,2
14.6
3
14.0
1,3
VCC = 16.5 V dc
Limits
Min
1,2
VCC = 4.5 V dc,
Device
type
01
V
100
nA
3.0
A
0.80
V
Discharge transistor leakage
current
ICEX
Discharge transistor
saturation voltage
VSAT
Reset voltage
VR
VCC = 16.5 V dc, see figure 6
1,2,3
01
0.1
1.3
Reset current
IR
VCC = 16.5 V dc, VR = 0 V dc
1,2,3
01
-1.60
0
mA
Propagation delay time, low
to high level output
(monostable)
tPLH
4.5 V dc  VCC  16.5 V dc,
9,11
01
800
ns
Transition time, low to high
level output (monostable)
2
VCC = 16.5 V dc, ID = 50 mA
1,3
01
2
RT = 1 k, CT = 0.1 F,
1.00
10
V
900
see figure 3
4.5 V dc  VCC  16.5 V dc,
tTLH
RT = 1 k, CT = 0.1 F,
9,10,11
01
300
ns
9,10,11
01
300
ns
9,10,11
01
106.7
113.3
s
10.67
11.33
ms
-220
220
see figure 3
Transition time, high to low
level output (monostable)
4.5 V dc  VCC  16.5 V dc,
tTHL
RT = 1 k, CT = 0.1 F,
see figure 3
Time delay, output high
(monostable)
4.5 V dc  VCC  16.5 V dc,
tD(OH)
RT = 1 k, CT = 0.1 F,
see figure 3
4.5 V dc  VCC  16.5 V dc,
RT = 100 k, CT = 0.1 F,
see figure 3
Drift in time delay versus
change in supply voltage
(monostable)
tD(OH) /
VCC
VCC = 12 V,
RT = 1 k, CT = 0.1 F,
01
ns/V
see figure 3, TA = +25C
STANDARD
MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
9
SIZE
5962-98555
A
REVISION LEVEL
SHEET
7
TABLE I. Electrical performance characteristics – Continued.
Test
Propagation delay time,
threshold to output
Temperature coefficient 1/
of time delay (monostable)
Capacitor charge time
(astable)
Symbol
tPHL
tD(OH) /
T
Conditions
-55C  TA +125C
unless otherwise specified
4.5 V dc  VCC  16.5 V dc,
Group A
subgroups
Device
type
Limits
Min
Unit
Max
12.0
s
9,10,11
01
10,11
01
-11
11
ns/C
9,10,11
01
120
156
s
11.3
15.0
ms
57.5
80
s
5.4
7.7
ms
RT = 1 k, see figure 4
VCC = 16.5 V,
RT = 1 k, CT = 0.1 F,
see figure 3
4.5 V dc  VCC  16.5 V dc,
tch
RTA = RTB = 1 k,
CT = 0.1 F, see figure 5
4.5 V dc  VCC  16.5 V dc,
RTA = RTB = 100 k,
CT = 0.1 F, see figure 5
Capacitor discharge time
(astable)
4.5 V dc  VCC  16.5 V dc,
tdis
9,10,11
RTA = RTB = 1 k,
01
CT = 0.1 F, see figure 5
4.5 V dc  VCC  16.5 V dc,
RTA = RTB = 100 k,
CT = 0.1 F, see figure 5
VCC = 12 V dc,
Drift in capacitor charge
time versus change in
supply voltage (astable)
tch /
RTA = RTB = 1 k,
VCC
CT = 0.1 F, see figure 5,
9
01
-820
820
ns/V
10,11
01
-68
68
ns/C
9,11
01
1.5
s
TA = +25C
VCC = 16.5 V dc,
Temperature coefficient 2/
of capacitor charge time
(astable)
tch / T
RTA = RTB = 1 k,
CT = 0.1 F, see figure 5,
TA = +25C
Reset time
tres
VCC = 16.5 V dc, see figure 6
10
2
1/
This parameter is guaranteed but, not production tested.
tD(OH) / T = (tD(OH) at 125C – tD(OH) at 25C) / (125C – 25C) and (tD(OH) at 25C – tD(OH) at -55C) / (25C – (-55C)).
2/
This parameter is guaranteed but, not production tested.
tch / T = (tch at 125C – tch at 25C) / (125C – 25C) and (tch at 25C – tch at -55C) / (25C – (-55C)).
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Device type
01
Case outline
P
Terminal
number
Terminal symbol
1
GND
2
TRIGGER
3
OUTPUT
4
RESET
5
CONTROL
VOLTAGE
6
THRESHOLD
7
DISCHARGE
8
VCC
FIGURE 1. Terminal connections.
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FIGURE 2. Block diagram and circuit operation table.
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INPUTS
OUTPUT
RESET
THRESHOLD
TRIGGER
 
0
1
 
1
1
0
 
0
0
 
 
1
0
 
RESETS (
1


1
RESETS
1


0
1
0


1
0
0


0
0
)
1
0
 
1
1
 
 
(SEE NOTE 1)
0
0
 
0
0
1
 
0
SETS ( 
)
NOTES:
1. Some devices latch high for VCC  10 V dc.
2. Discharge transistor follows the output as follows:
Output high = discharge transistor OFF
Output low = discharge transistor ON
FIGURE 2. Block diagram and circuit operation table – Continued.
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Notes:
1. This limit applies only during tests for tPLH, tTLH, and tTHL.
2. The pulse is applied to TRIGGER pin.
3. This measurement shall be made on OUTPUT pin.
4. A/B means value “A” for VCC = 15 V or 16.5 V and “B” for VCC = 4.5 V or 5 V.
FIGURE 3. Waveforms for switching and timing parameters (monostable).
Notes:
1. This limit applies only during tests for tPHL.
2. The pulse is applied to TRIGGER.
3. This measurement shall be made on OUTPUT pin.
4. A/B means value “A” for VCC = 15 V or 16.5 V and “B” for VCC = 4.5 V or 5 V.
FIGURE 4. Waveforms for switching and timing parameters (monostable).
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NOTES:
1. The timing capacitor voltage measurement (threshold) shall be made on TRIGGER pin.
2. The timing measurement (output) shall be made at OUTPUT pin.
FIGURE 5. Waveforms for timing parameters (astable).
NOTES:
1. Reset pulse rise and fall times shall be  10 ns.
2. Reset threshold are checked by applying the specified reset levels and verifying
a.
b.
3.
4.
5.
6.
7.
Output high after trigger pulse and before reset goes low and
Output goes low stays low 2 seconds minimum after rest is returned high.
This limit only applies during test for tRES.
This pulse shall be applied to TRIGGER pin.
This measurement shall be made on OUTPUT pin.
This pulse shall be applied to RESET.
A/B means value “A” for VCC = 15 V or 16.5 V and “B” for VCC = 4.5 V or 5 V.
FIGURE 6. Waveforms for reset tests.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
(2) TA = +125C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 4, 5, 6, 7, and 8 in table I, method 5005 of MIL-STD-883 shall be omitted.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98555
A
REVISION LEVEL
SHEET
14
TABLE IIA. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
1/
2/
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
1
1
1
1,2,3,9 1/
1,2,3,9 1/
1,2,3,9 2/
1,2,3,9,10,11
1,2,3,9,10,11
1,2,3,9,10,11
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3, 2/
9,10,11
1,2,3
Device
class Q
---
---
Device
class V
---
PDA applies to subgroup 1.
Delta limits as specified in table IIB shall be required where specified, and the delta limits
shall be computed with reference to the zero hour electrical parameters (see table I).
TABLE IIB. Burn-in and operating life test delta parameters. TA = +25C. 1/
Test
Limits
Delta limits
Min
Max
VTR
5.20 V
5.80 V
50 mV
VTH
10.70 V
11.30 V
50 mV
VOL at 10 mA
---
0.150 V
50 mV
ICEX
---
100 nA
50 nA
1/ Deltas are performed at room temperature.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98555
A
REVISION LEVEL
SHEET
15
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested.
All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at
TA = +25C 5C, after exposure, to the subgroups specified in table IIA herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98555
A
REVISION LEVEL
SHEET
16
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
Symbol
Description
VTR
Trigger voltage. The voltage at which the output latches from the “low” state to the
“high” state. This voltage is nominally 1/3 VCC.
ITR
Trigger current. The current flowing out of the trigger terminal while the output is in the
“high” state.
VTH
Threshold voltage. The voltage at which the output latches from the “high” state to the
“low” state. This voltage is nominally 2/3 VCC.
ITH
Threshold current. The current flowing into the threshold terminal while the output is in
the “low” state.
VCL
Control voltage. The control voltage is the reference voltage for the threshold
comparator. It is internally generated by a voltage divider (from VCC to ground) tapped
at 2/3 VCC. NOTE: The divider is also tapped at 1/3 VCC, which is the reference
voltage for the trigger comparator.
Reset voltage. The reset acts as an inhibit. If 1.3  VR  VCC, the device is free to
VR
IR
function. If 0 V  VR  0.1 V, the output is forced to the “low” state. The output will
remain low after the reset voltage goes high only if the trigger voltage is high. If the
trigger voltage is low, the output will go high when the reset voltage goes high. The
reset voltage going low also causes the discharge transistor to turn on, thus preventing
the timing capacitor (CT) from charging.
Reset current. The current out of the reset terminal after the reset voltage has been
applied and the output is latched low.
VSAT
Discharge transistor saturation voltage. When the output is low, the discharge terminal
is sinking current. VSAT is defined as the collector-emitter voltage of the discharge
transistor when sinking the specified current.
tD(OH)
Time delay, output high. In the monostable mode of operation, the interval of time the
output remains high once triggered. This delay is given by the following equation:
tD(OH) = 1.1 RT CT (see figure 4).
tch
Capacitor charge time. In the astable mode of operation, the time interval during which
the external timing capacitor (CT) is charging from 1/3 VCC to 2/3 VCC. This interval is
ideally given by the equation: tch = 0.693 (RTA + RTB) CT (see figure 5).
tdis
Capacitor discharge time. In the astable mode of operation, the time interval during
which the external timing capacitor (CT) is discharging from 2/3 VCC to 1/3 VCC. This
interval is ideally given by the equation: tdis = 0.693 RTB CT (see figure 5).
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-98555
A
REVISION LEVEL
SHEET
17
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 10-07-08
Approved sources of supply for SMD 5962-98555 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9855501VPA
01295
SE555JG
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
01295
Vendor name
and address
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.