96743

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Boilerplate update and part of five year review. tcr
06-04-19
Raymond Monnin
B
Update drawing to the current requirements of MIL-PRF-38535.
Removed class M requirements. - glg
14-08-18
Charles Saffle
REV
SHEET
REV
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
SHEET
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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32
REV STATUS
REV
B
B
B
B
B
B
B
B
B
B
B
B
B
B
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
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11
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PMIC N/A
PREPARED BY
Jeff Bowling
STANDARD MICROCIRCUIT
DRAWING
CHECKED BY
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
Jeff Bowling
APPROVED BY
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
Michael A. Frye
DRAWING APPROVAL DATE
96-02-28
REVISION LEVEL
B
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, 1 MEG X 16 DRAM,
MONOLITHIC SILICON
SIZE
A
SHEET
DSCC FORM 2233
APR 97
CAGE CODE
67268
1 OF
5962-96743
32
5962-E439-14
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and
space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
96743
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
Q
X
A
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
03
04
Generic number
416160-80
416160-70
418160-80
418160-70
Circuit function
Access time
1 MEG-word by 16-bit DRAM, 32 ms refresh
1 MEG-word by 16-bit DRAM, 32 ms refresh
1 MEG-word by 16-bit DRAM, 8 ms refresh
1 MEG-word by 16-bit DRAM, 8 ms refresh
80 ns
70 ns
80 ns
70 ns
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Descriptive designator
Terminals
See figure 1
50
Package style
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V.
________
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ All voltage values in this drawing are with respect to VSS.
STANDARD
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REVISION LEVEL
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1.3 Absolute maximum ratings. 1/ 2/
Voltage range on VCC .................................................................
Voltage range on any pin ...........................................................
Short circuit output current .........................................................
Maximum power dissipation (PD) ...............................................
Operating free-air temperature range TA ....................................
Storage temperature range Tstg.................................................
Lead temperature (soldering, 10 seconds) ................................
Thermal resistance, junction-to-case (θJC)
Case outline X..........................................................................
Junction temperature (TJ) 4/......................................................
-1 V dc to +7 V dc
-1 V dc to +7 V dc
+50 mA
1W
-55°C to +125°C
-65°C to +150°C
+300°C
5°C/W 3/
+175°C
1.4 Recommended operating conditions.
Supply voltage range (VCC) ........................................................
Supply voltage (VSS) ..................................................................
High-level input voltage (VIH)......................................................
Low-level input voltage (VIL) 5/ ...................................................
Transition time (tT)......................................................................
Operating free-air temperature range (TA) .................................
+4.5 V dc to +5.5 V dc
0 V dc
+2.4 V dc minimum to +6.5 V dc maximum
-1.0 V dc minimum to +0.8 V dc maximum
3 ns minimum to 30 ns maximum
-55°C to +125°C
1.5 Digital logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, method 5012) ................................. 100 percent
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.
________
3/ When the thermal resistance for this case is specified in MIL-STD-1835 that value shall supersede the value indicated
herein.
4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
5/ The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used in this drawing
for logic voltage levels only.
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APR 97
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REVISION LEVEL
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JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JESD78
-
IC Latch-Up Test.
(Copies of this document are available online at www.jedec.org or from JEDEC – Solid State Technology Association, 3103
th
North 10 Street, Suite 247, Arlington, VA 22201).
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute
the documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in
the QM plan shall not affect the form, fit, or function as described herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table. The truth table shall be as specified on figure 3.
3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns
cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be
allowed. For device classes Q and V, alternate test patterns shall be under the control of the device manufacturer's Technology
Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon
request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance
submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V.
STANDARD
MICROCIRCUIT DRAWING
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APR 97
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REVISION LEVEL
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3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall
be provided with each lot of microcircuits delivered to this drawing.
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
STANDARD
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TABLE I. Electrical performance characteristics.
Test
Symbol
High-level output voltage
VOH
Low-level output voltage
VOL
Input leakage current
II
Output leakage current
IO
Average operating power
Supply current (Random
read or write cycle)
ICC1
Standby power supply
current
ICC2
Conditions
-55°C ≤ TA ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
IOH = -5 mA, VIL = 0.8 V
VIH = 2.4 V
IOL = 4.2 mA, VIL = 0.8 V
VIH = 2.4 V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All other pins = 0 V to VCC
VCC = 5.5 V, CASx high,
VO = 0 V to VCC
VCC = 5.5 V, Minimum cycle
time, outputs open
measured with a maximum of
one address change while
Group A
subgroups
Device
type
1, 2, 3
All
1, 2, 3
All
0.4
V
1, 2, 3
All
±10
µA
1, 2, 3
All
±10
µA
1, 2, 3
01
02
03
04
70
80
170
180
mA
1, 2, 3
All
2
mA
1, 2, 3
All
1
1, 2, 3
01
70
02
80
03
170
04
180
01
70
02
80
03
170
04
180
All
5
Unit
Limits
Min
Max
2.4
V
RAS = 0.8 V
VCC = 5.5 V
after one
memory
cycle, RAS
Average operating power
ICC3
supply current ( RAS only
refresh, or CBR)
TTL
VIH = 2.4 V
CMOS
VIH = VCC -0.2V
and CASx
high
VCC = 5.5 V, Minimum cycle,
RAS cycling,
CASx high ( RAS only),
RAS low after CASx low
(CBR) measured with a
maximum of one address
change while RAS = 0.8 V
Average operating power
supply current (Page mode)
mA
ICC4
VCC = 5.5 V, tPC = minimum,
1, 2, 3
RAS low, CASx cycling,
outputs open measured with a
maximum of one address
V
change while CASx = 2.4 V
Standby power supply
current (outputs enabled)
ICC5
RAS = VIH, CASx = VIL, data
out is enabled, ouputs open
measured with a maximum of
one address change while
1, 2, 3
mA
CASx = 2.4 V
See footnotes at end of table.
STANDARD
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TA ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
f = 1 MHz, See 4.4.1e,
Bias on pins under test =
0 V, all other pins are open
TA = 25°C
Group A
subgroups
Device
Type
Unit
4
All
8
pF
4
All
8
pF
Limits
Min
Max
Input capacitance,
Address inputs A0-A11
CI(A)
Input capacitance, OE
Ci(OE)
Input capacitance,
CASx and RAS
Ci(RC)
4
All
8
pF
Input capacitance, W
Ci(W)
4
All
8
pF
Output capacitance
CO
4
All
10
pF
7, 8A, 8B
All
9, 10, 11
01, 03
40
ns
02, 04
35
01, 03
20
02, 04
18
01, 03
45
Functionals
See 4.4.1c
Access time from column
address
tAA
Access time from CASx low
tCAC
Access time from column
precharge
tCPA
See figures 4 and 5
1/ 2/
9, 10, 11
Access time from RAS low
Access time from OE low
Output disable time after
CASx high 3/
Output disable time after
OE high 3/
Cycle time, read 2/
9, 10, 11
02, 04
40
9, 10, 11
01, 03
80
02, 04
70
9, 10, 11
01, 03
20
02, 04
18
01, 03
20
02, 04
18
01, 03
20
tRAC
tOEA
9, 10, 11
tOFF
9, 10, 11
tOEZ
02, 04
9, 10, 11
tRC
ns
ns
ns
ns
ns
ns
18
01, 03
150
02, 04
130
ns
See footnotes at end of table.
STANDARD
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TA ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
1/ 2/
Group A
subgroups
Device
Type
Limits
Min
Max
9, 10, 11
01, 03
02, 04
01, 03
02, 04
01, 03
02, 04
01, 03
02, 04
01, 03
02, 04
All
01, 03
02, 04
150
130
205
181
50
45
105
96
80
70
Cycle time, write 2/
tWC
Cycle time, read-write 2/
tRWC
9, 10, 11
Cycle time, page-mode read
or write 2/ 4/
tPC
9, 10, 11
Cycle time, page-mode
read-write 2/
tPRWC
9, 10, 11
Pulse duration, page mode,
5/
RAS low
tRASP
9, 10, 11
Pulse duration, non-pagemode, RAS low 5/
tRAS
9, 10, 11
Unit
ns
ns
ns
ns
ns
100
µs
ns
10
µs
80
70
All
ns
01, 03
20
02, 04
All
18
01, 03
60
02, 04
50
9, 10, 11
All
10
ns
tASC
9, 10, 11
All
0
ns
tASR
9, 10, 11
All
0
ns
Pulse duration, CASx low
6/
tCAS
Pulse duration, RAS high
(precharge)
tRP
9, 10, 11
Pulse duration, W low
tWP
Setup time, column address
before CASx low
Setup time, row address
before RAS low
9, 10, 11
10
µs
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TA ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
1/ 2/
Group A
subgroups
Device
Type
Unit
9, 10, 11
All
0
ns
All
0
ns
01, 03
20
ns
02, 04
18
01, 03
20
02, 04
18
Limits
Min
Max
Setup time, data 7/
tDS
Setup time, W high before
CASx low
tRCS
9, 10, 11
Setup time, W low before
CASx high
tCWL
9, 10, 11
Setup time, W low before
RAS high
tRWL
9, 10, 11
Setup time, W low before
CASx low (early-write
operation only)
tWCS
9, 10, 11
All
0
ns
Hold time, column address
after CASx low
tCAH
9, 10, 11
All
15
ns
Hold time, data 7/
tDH
9, 10, 11
All
15
ns
Hold time, row address after
RAS low
tRAH
9, 10, 11
All
10
ns
Hold time, W high after
CASx high 8/
tRCH
9, 10, 11
All
0
ns
Hold time, W high after
RAS high 8/
tRRH
9, 10, 11
All
0
ns
Hold time, W low after
CASx low (early-write
operation only)
tWCH
9, 10, 11
All
15
ns
tCLCH
9, 10, 11
All
5
ns
9, 10, 11
01, 03
45
ns
tRHCP
02, 04
40
tOEH
9, 10, 11
01, 03
20
02, 04
18
Hold time, CASx low to
CASx high
Hold time, RAS high from
CASx precharge
Hold time OE command
ns
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Hold time, RAS referenced
to OE
Delay time, CASx high
(precharge)
Delay time, column address
to W low (read-write
operation only)
Symbol
Conditions
-55°C ≤ TA ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
1/ 2/
Group A
subgroups
Device
Type
9, 10, 11
All
10
ns
tCP
9, 10, 11
All
10
ns
01, 03
70
ns
tAWD
9, 10, 11
02, 04
63
tCHR
9, 10, 11
All
10
ns
tCRP
9, 10, 11
All
5
ns
01, 03
80
ns
tCSH
9, 10, 11
02, 04
70
All
5
ns
01, 03
50
ns
02, 04
46
01, 03
20
02, 04
18
01, 03
15
40
02, 04
15
35
01, 03
40
02, 04
35
01, 03
40
02, 04
35
01, 03
20
60
02, 04
20
52
tROH
Limits
Min
Max
Unit
Delay time, RAS low to
CASx high (CBR refresh
only)
Delay time, CASx high to
RAS low
Delay time, RAS low to
CASx high
Delay time, CASx low to
tCSR
9, 10, 11
tCWD
9, 10, 11
Delay time,
OE to data
tOED
9, 10, 11
Delay time, RAS low to
column address 9/
tRAD
9, 10, 11
Delay time, column address
to RAS high
tRAL
9, 10, 11
Delay time, column address
to CASx high
tCAL
9, 10, 11
tRCD
9, 10, 11
RAS low (CBR refresh only)
Delay time, CASx low to
W low (Read-write
operation only)
Delay time, RAS low to
CASx low
9/
ns
ns
ns
ns
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Delay time, RAS high to
CASx low
Delay time, CASx low to
RAS high
Symbol
tRPC
Conditions
-55°C ≤ TA ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
1/ 2/
tRSH
Group A
subgroups
Device
Type
9, 10, 11
All
0
ns
01, 03
20
ns
02, 04
18
01, 03
110
02, 04
98
01, 03
75
02, 04
68
9, 10, 11
Delay time, RAS low to W
low (read-write operation
only)
tRWD
Delay time, W low after
CASx precharge (Readwrite operation only)
tCPW
9, 10, 11
Refresh time interval
tREF
9, 10, 11
Unit
Limits
Min
Max
ns
9, 10, 11
ns
01, 03
32
02, 04
8
ns
1/ An initial pause of 200 μs is required after power-up followed by a minimum of 8 initialization cycles after full VCC level is
achieved. The 8 initialization cycles need to be RAS only refresh or CBR to assure proper device operation. The 8
initialization cycles should be repeated any time the refresh requirement is exceeded.
2/ All cycle times assume transition time tT = 5 ns, referenced to VIH (min) and VIL (max).
3/ tOFF and tOEZ are specified when the output is no longer driven. The outputs are disabled (high impedance) by bringing
either OE or CASx high.
4/ To guarantee tPC min, tASC should be greater than or equal to tCP.
5/ In a read-write cycle, tRWD and tRWL must be observed.
6/ In a read-write cycle, tCWD and tCWL must be observed.
7/ Referenced to the later of CASx or W in write operations.
8/ Either tRRH or tRCH must be satisfied for a read cycle.
9/ Maximum value specified only to guarantee access time.
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Case X
FIGURE 1. Case outline.
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Millimeters
Inches
Symbol
Min
Max
Min
Max
A
2.80
3.55
.110
.140
b
0.30
0.50
.012
.020
c
0.10
0.23
.004
.009
D
20.60
21.40
.811
.842
D1
18.95
19.45
.746
.766
E
16.10
16.90
.634
.665
E2
14.10
14.90
.555
.587
E3
0.76
-----
.030
-----
e
0.80 BSC
.031 BSC
L
6.35
9.40
.250
.370
Q
0.66
-----
.026
-----
S1
0.38
-----
.015
-----
NOTE: The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outline - continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
13
Device types
01, 02, 03, and 04
Case Outlines
X
Terminal
number
Terminal symbol
Terminal
number
Terminal
symbol
1
VCC
26
VSS
2
DQ0
27
A4
3
DQ1
28
A5
4
DQ2
29
A6
5
DQ3
30
A7
6
VCC
31
A8
7
DQ4
32
A9
8
DQ5
33
OE
9
DQ6
34
CASU
10
DQ7
35
CASL
11
NC
36
NC
12
NC
37
NC
13
NC
38
NC
14
NC
39
NC
15
NC
40
NC
16
NC
41
DQ8
17
W
42
DQ9
18
RAS
43
DQ10
19
A11 1/
44
DQ11
20
A10 1/
45
VSS
21
A0
46
DQ12
22
A1
47
DQ13
23
A2
48
DQ14
24
A3
49
DQ15
25
VCC
50
VSS
1/ A10 and A11 are NC for devices 03 and 04.
FIGURE 2. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
14
Operation
Inputs
Row address
Column address
Input / Output
D
Q
RAS
CAS
W
OE
Read
ACT
ACT
NAC
ACT
APD
APD
NAC
VLD
Write (early write)
ACT
ACT
ACT
DNC
APD
APD
APD
ILD
Write (late write)
ACT
ACT
ACT
NAC
APD
APD
APD
ILD
Read-modify-write
ACT
ACT
ACT
ACT
APD
APD
APD
VLD
RAS - only refresh
ACT
NAC
DNC
DNC
APD
DNC
DNC
OPN
Hidden refresh (read)
ACT
ACT
NAC
ACT
APD
APD
NAC
VLD
Hidden refresh (write)
ACT
ACT
ACT
DNC
APD
APD
APD
DNC
CAS before RAS refresh
ACT
ACT
DNC
DNC
DNC
DNC
DNC
OPN
Standby
NAC
NAC
DNC
DNC
DNC
DNC
DNC
OPN
ACT = active
NAC = nonactive
DNC = don't care
VLD = valid
ILD = invalid
APD = applied
OPN = open
FIGURE 3. Truth table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
15
NOTE: The ac timing parameters are specified with reference to the minimum valid high-level voltage and the maximum valid
low-level voltage for each signal. This corresponds to 2.4 V and 0.8 V for inputs; 2.4 V and 0.4 V for outputs with the
given load circuit.
FIGURE 4. Load circuit and voltage waveforms.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
16
NOTES:
1. CASx order is arbitrary.
2. To hold the address latched by the first CASx going low, the parameter tCLCH must be met.
3. tCAC is measured from CASx to its corresponding DQx.
4. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
FIGURE 5. Timing waveforms.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
17
NOTES:
1. CASx order is arbitrary.
2. To hold the address latched by the first CASx going low, the parameter tCLCH must be met.
3. Referenced to the first CASx or W , whichever occurs last.
FIGURE 5. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
18
NOTES:
1. CASx order is arbitrary.
2. To hold the address latched by the first CASx going low, the parameter tCLCH must be met.
FIGURE 5. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
19
NOTES:
1. CASx order is arbitrary.
2. To hold the address latched by the first CASx going low, the parameter tCLCH must be met.
3. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
4. tCAC is measured from CASx to its corresponding DQx.
FIGURE 5. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
20
NOTES:
1. CASx order is arbitrary.
2. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write-timing
specifications are not violated.
3. To hold the address latched by the first CASx going low, the parameter tCLCH must be met.
4. tCAC is measured from CASx to its corresponding DQx.
5. Access time is tCPA or tAA dependent.
6. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
FIGURE 5. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
21
NOTES:
1. CASx order is arbitrary.
2. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify- writetiming specifications are not violated.
3. To hold the address latched by the first CASx going low, the parameter tCLCH must be met.
4. Referenced to the first CASx or W , whichever occurs last.
FIGURE 5. Timing waveforms - Continued
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
22
NOTES:
1. CASx order is arbitrary.
2. A read or write cycle can be mixed with read-modify-write cycles as long as the read- and write-cycle timing specifications
are not violated.
3. tCAC is measured from CASx to its corresponding DQx.
4.
5.
6.
To hold the address latched by the first CASx going low, the parameter tCLCH must be met.
Access time is tCPA or tAA dependent.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
FIGURE 5. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
23
NOTE: All CASx must be high.
FIGURE 5. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
24
FIGURE 5. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
25
NOTE: Any CASx can be used.
FIGURE 5. Timing waveforms - Continued
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
26
TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/
Line
no.
Test
requirements
1
Interim electrical
parameters (see 4.2)
2
Static burn-in I and
II (method 1015)
3
Same as line 1
4
Dynamic burn-in
(method 1015)
5
6
Subgroups
(per MIL-PRF-38535,
table III)
Device
Device
class Q
class V
1, 7, 9
Not Required
Required
Required
1*, 7* ∆
Required
Same as line 1
Final electrical
parameters
1*, 2, 3, 7*,
8A, 8B, 9, 10, 11
1*, 7* ∆
1*, 2, 3, 7*,
8A, 8B, 9, 10, 11
7
Group A test
requirements
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
8
Group C end-point
electrical parameters
1, 2, 3, 7, 8A, 8B
9
Group D end-point
electrical parameters
2, 3, 8A, 8B
1, 2, 3, 7,
8A, 8B, 9,
10, 11 ∆
2, 3, 8A, 8B
10
Group E end-point
electrical parameters
1, 7, 9
1, 7, 9
1/
2/
3/
4/
5/
6/
Blank spaces indicate tests are not applicable.
Any or all subgroups may be combined when using high-speed testers.
Subgroups 7 and 8 functional tests shall verify functionality of the device.
* indicates PDA applies to subgroup 1 and 7.
** see 4.4.1e.
Δ indicates delta limit shall be required where specified, and the delta values shall be computed
with reference to the previous interim electrical parameters (see line 1). For device classes Q
and V, performance of delta limits shall be as specified in the manufacturer's QM plan.
7/ See 4.4.1d.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
27
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits
alternate in-line control testing.
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c.
For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall
have been fault graded in accordance with MIL-STD-883, method 5012 (see 1.5 herein).
d.
O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device classes Q and V, the procedures and circuits shall be under the
control of the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the
preparing activity or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures.
Latch-up test shall be considered destructive. Information contained in JESD 78 may be used for reference.
e.
Subgroup 4 (capacitance measurements) shall be measured only for initial qualification and after any process or design
changes which may affect input or output capacitance. Capacitance shall be measured between the designated
terminal and GND at a frequency of 1MHz. Sample size is 15 devices with no failures, and all input and output
terminals tested.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
28
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point
electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in table
IIA herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
29
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331 and as follows:
CIN COUT ............................... Input and bidirectional output, terminal-to-GND capacitance.
ICC .......................................... Supply current.
IIL ............................................ Input current low
IIH .................................................................. Input current high
TC ........................................... Case temperature
TA ........................................... Ambient temperature
VCC ......................................... Positive supply voltage
VSS ......................................... Ground zero voltage potential
VIC .......................................... Positive input clamp voltage
O/V ......................................... Latch-up over-voltage
O/I .......................................... Latch-up over-current
A0-A11 ................................... Address inputs
DQ0-DQ11 ............................. Data In/Data out
CASL .................................... Lower Column-Address Strobe
CASU .................................... Upper Column-Address Strobe
NC .......................................... No Internal Connection
OE ........................................ Output Enable
RAS ...................................... Row-Address Strobe
W .......................................... Write Enable
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535
and MIL-HDBK-103. The vendors listed in QML-38535 and MIL-HDBK-103 have submitted a certificate of compliance (see 3.6
herein) to DLA Land and Maritime-VA and have agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
30
APPENDIX A
APPENDIX A forms a part of SMD 5962-96743
FUNCTIONAL ALGORITHMS
A.1 SCOPE
A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper
operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is
understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each
manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be
used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be
applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The information
contained herein is intended for compliance.
A.2 APPLICABLE DOCUMENTS. This section is not applicable to this appendix.
A.3 ALGORITHMS
A.3.1 Algorithm A (pattern 1).
A.3.1.1 Output high impedance (tOFF). This pattern verifies the output buffer switches to high impedance
(three-state) within the specified tOFF after the rise of CAS . It is performed in the following manner:
Step 1:
Step 2:
Step 3:
Perform 8 pump cycles.
Load address location with data.
Raise CAS and read address location and guarantee VOL < VOUT < VOH after tOFF delay.
A.3.2 Algorithm B (pattern 2).
A.3.2.1 VCC slew). This pattern indicates sense amplifier margin by slewing the supply voltage between memory
writing and reading. It is performed in the following manner:
Step 1: Perform 8 pump cycles.
Step 2: Load memory with background data with VCC at 5.0 V.
Step 3: Change VCC to 5.5 V.
Step 4: Read memory with background data.
Step 5: Load memory with background data complement.
Step 6: Change VCC to 4.5 V.
Step 7: Read memory with background data complement.
A.3.3 Algorithm C (pattern 3).
A.3.3.1 March data. This pattern tests for address uniqueness and multiple selection. It is performed in the following
manner:
Step 1: Perform 8 pump cycles.
Step 2: Load memory with background data.
Step 3: Read location 0.
Step 4: Write data complement in location 0.
Step 5: Repeat steps 3 and 4 for all other locations in the memory (sequentially).
Step 6: Read data complement in maximum address location.
Step 7: Write data in maximum address location.
Step 8: Repeat steps 6 and 7 for all other locations in the memory from maximum to minimum address.
Step 9: Read data in maximum address location.
Step 10: Write data complement in maximum address location.
Step 11: Repeat steps 6 and 7 for all other locations in the memory from maximum to minimum address.
Step 12: Read memory with data complement.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
31
APPENDIX A – continued.
APPENDIX A forms a part of SMD 5962-96743
A.3.4 Algorithm D (pattern 4).
A.3.4.1 Refresh test (cell retention) +125°C only. This test is used to check the retention time of the memory cells. It is
performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load memory with background data.
Pause tREF (stop all clocks).
Read memory with background data.
Repeat steps 2 through 4 with data complement.
A.3.5 Algorithm E (pattern 5).
A.3.5.1 Read-modify-write (RMW). This pattern verifies the Read-modify-write mode for the memory. It is performed in the
following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load memory with background data.
Read memory with data and load with data complement using RMW cycle.
Repeat step 3 for all address locations.
Repeat steps 2 and 3 using data complement.
A.3.6 Algorithm F (pattern 6).
A.3.6.1 Page mode. This pattern verifies the Page mode for the memory. It is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load first page of memory with background data using Page mode cycle.
Read first page of memory with data and load with data complement using Page mode cycle.
Read first page of memory with data complement and load with data using Page mode cycle.
Repeat steps 2 through 4 for remaining memory locations.
A.3.7 Algorithm G (pattern 7).
A.3.7.1 CAS-before-RAS refresh test. This test is used to verify the functionality of the CAS before RAS mode of cell
refreshing. It is done at +125°C only and is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Perform 8 pump cycles.
Load memory with background data.
Pause for tREF (stop all clocks).
Perform 4096 CAS -before- RAS cycles for device types 01 and 02 and 1024 for device types 03 and 04,
while attempting to modify data.
Step 5: Read memory with background data.
A.3.8 Algorithm H (pattern 8).
A.3.8.1 RAS-only refresh test. This test is used to verify the functionality of the RAS -only mode of cell refreshing. It is done
at +125°C only and is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Perform 8 pump cycles.
Load memory with background data.
Pause for tREF (stop all clocks).
Perform 4096 RAS -only cycles for device types 01 and 02 and 1024 for device types 03 and 04,
while attempting to modify data.
Step 5: Read memory with background data.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96743
A
REVISION LEVEL
B
SHEET
32
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 14-08-18
Approved sources of supply for SMD 5962-96743 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9674301QXA
57300
SMJ416160-80HKD
5962-9674302QXA
57300
SMJ416160-70HKD
5962-9674303QXA
57300
SMJ418160-80HKD
5962-9674304QXA
57300
SMJ418160-70HKD
1/ The lead finish shown for each PIN representing a hermetic package
is the most readily available from the manufacturer listed for that part.
If the desired lead finish is not listed contact the vendor to determine
Its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired to
this number may not satisfy the performance requirements of this drawing.
Vendor CAGE
number
57300
Vendor name
and address
Micross Components
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.