IRF644S, SiHF644S www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • 250 RDS(on) () VGS = 10 V 0.28 Qg max. (nC) 68 Qgs (nC) 11 Qgd (nC) 35 Configuration Single Surface mount Available in tape and reel Dynamic dV/dt rating Available Repetitive avalanche rated Fast switching Ease of paralleling Available Simple drive requirements Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. D D2PAK (TO-263) DESCRIPTION Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK is a surface mount power package capable of accommodating die size up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. G G D S S N-Channel MOSFET ORDERING INFORMATION Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) Lead (Pb)-free and Halogen-free SiHF644S-GE3 SiHF644STRL-GE3 a SiHF644STRR-GE3 a IRF644SPbF IRF644STRLPbF a IRF644STRRPbF a Lead (Pb)-free SiHF644S-E3 SiHF644STL-E3 a SiHF644STR-E3 a Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 250 Gate-Source Voltage VGS ± 20 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID IDM Linear Derating Factor V 14 8.5 A 56 1.0 Linear Derating Factor (PCB mount) e UNIT 0.025 W/°C Single Pulse Avalanche Energy b EAS 550 Avalanche Current a IAR 14 A Repetitive Avalanche Energy a EAR 13 mJ Maximum Power Dissipation TC = 25 °C Maximum Power Dissipation (PCB mount) e TA = 25 °C Peak Diode Recovery dV/dt c Operating Junction and Storage Temperature Range Soldering Recommendations (Peak temperature) d for 10 s PD 125 3.1 dV/dt 4.8 TJ, Tstg -55 to +150 300 mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 4.5 mH, Rg = 25 , IAS = 14 A (see fig. 12). c. ISD 14 A, dI/dt 150 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). S16-0754-Rev. D, 02-May-16 Document Number: 91040 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF644S, SiHF644S www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Ambient (PCB mount) a RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 1.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VDS VGS = 0, ID = 250 μA 250 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.34 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V nA IGSS IDSS VGS = ± 20 V - - ± 100 VDS = 250 V, VGS = 0 V - - 25 VDS = 200 V, VGS = 0 V, TJ = 125 °C - - 250 μA - - 0.28 gfs VDS = 50 V, ID = 8.4 A b 6.7 - - S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 1300 - - 330 - - 85 - - - 68 RDS(on) ID = 8.4 A b VGS = 10 V Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs - - 11 Gate-Drain Charge Qgd - - 35 Turn-On Delay Time td(on) - 11 - tr - 24 - - 53 - - 49 - - 4.5 - - 7.5 - 0.3 - 1.2 - - 14 - - 56 Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance td(off) VGS = 10 V ID = 7.9 A, VDS = 200 V, see fig. 6 and 13 b VDD = 125 V, ID = 7.9 A, Rg = 9.1 , RD = 8.7 , see fig. 10 b tf LD Internal Source Inductance LS Gate Input Resistance Rg Between lead, 6 mm (0.25") from package and center of die contact pF nC ns D nH G S f = 1 MHz, open drain Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Current a Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 14 A, VGS = 0 V S b TJ = 25 °C, IF = 7.9 A, dI/dt = 100 A/μs b - - 1.8 V - 250 500 ns - 2.3 4.6 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. S16-0754-Rev. D, 02-May-16 Document Number: 91040 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF644S, SiHF644S www.vishay.com Vishay Siliconix VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V ID, Drain Current (A) Top 101 100 4.5 V 20 µs Pulse Width TC = 25 °C 10-1 100 101 VDS, Drain-to-Source Voltage (V) 91040_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 ID = 7.9 A VGS = 10 V 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 TJ, Junction Temperature (°C) 91040_04 Fig. 1 - Typical Output Characteristics, TC = 25 °C 20 40 60 80 100 120 140 160 Fig. 4 - Normalized On-Resistance vs. Temperature 3000 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 101 2400 4.5 V 100 Capacitance (pF) ID, Drain Current (A) Top 1800 Ciss 1200 Coss 600 20 µs Pulse Width TC = 150 °C 100 10-1 0 101 100 VDS, Drain-to-Source Voltage (V) 91040_02 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 25 °C 100 20 µs Pulse Width VDS = 50 V 10-1 4 91040_03 5 6 7 8 9 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S16-0754-Rev. D, 02-May-16 VGS, Gate-to-Source Voltage (V) ID, Drain Current (A) 20 150 °C 101 VDS, Drain-to-Source Voltage (V) 91040_05 Fig. 2 - Typical Output Characteristics, TC = 150 °C 101 Crss ID = 7.9 A VDS = 200 V 16 VDS = 125 V VDS = 50 V 12 8 4 For test circuit see figure 13 0 10 0 91040_06 10 20 30 40 50 60 70 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91040 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF644S, SiHF644S www.vishay.com Vishay Siliconix 12 101 ID, Drain Current (A) ISD, Reverse Drain Current (A) 14 150 °C 25 °C 100 8 6 4 2 VGS = 0 V 10-1 0.5 0 0.6 0.7 0.9 0.8 1.1 1.0 25 VSD, Source-to-Drain Voltage (V) 91040_07 103 50 100 125 RD VDS VGS D.U.T. Rg 2 + - VDD 102 5 10 µs 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 2 100 µs 10 5 Fig. 10a - Switching Time Test Circuit 1 ms TC = 25 °C TJ = 150 °C Single Pulse 2 1 2 1 5 10 2 5 VDS 10 ms 102 2 5 150 Fig. 9 - Maximum Drain Current vs. Case Temperature Operation in this area limited by RDS(on) 5 75 TC, Case Temperature (°C) 91040_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage ID, Drain Current (A) 10 90 % 103 VDS, Drain-to-Source Voltage (V) 91040_08 Fig. 8 - Maximum Safe Operating Area 10 % VGS td(on) td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 0 − 0.5 PDM 0.2 0.1 0.1 t1 0.05 t2 0.02 0.01 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC Single Pulse (Thermal Response) 10-2 10-5 91040_11 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S16-0754-Rev. D, 02-May-16 Document Number: 91040 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF644S, SiHF644S www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD Rg D.U.T + - I AS V DD VDS 10 V 0.01 Ω tp IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12a - Unclamped Inductive Test Circuit EAS, Single Pulse Energy (mJ) 1200 ID 6.3 A 8.9 A Bottom 14 A Top 1000 800 600 400 200 0 VDD = 50 V 25 91040_12c 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S16-0754-Rev. D, 02-May-16 Fig. 13b - Gate Charge Test Circuit Document Number: 91040 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF644S, SiHF644S www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive Period P.W. D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91040. S16-0754-Rev. D, 02-May-16 Document Number: 91040 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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