IRF510S, SiHF510S Datasheet

IRF510S, SiHF510S
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
100
RDS(on) ()
VGS = 10 V
Qg max. (nC)
0.54
8.3
Qgs (nC)
2.3
Qgd (nC)
3.8
Configuration
Single
D
•
•
•
•
•
•
•
•
Surface mount
Available in tape and reel
Dynamic dV/dt rating
Available
Repetitive avalanche rated
175 °C operating temperature
Available
Fast switching
Ease of paralleling
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
D2PAK (TO-263)
G
DESCRIPTION
G D
S
S
N-Channel MOSFET
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package
capable of accommodating die sizes up to HEX-4. It
provides the highest power capability and the lowest
possible on-resistance in any existing surface mount
package. The D2PAK (TO-263) is suitable for high current
applications because of its low internal connection
resistance and can dissipate up to 2.0 W in a typical surface
mount application.
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
D2PAK (TO-263)
SiHF510S-GE3
IRF510SPbF
SiHF510S-E3
D2PAK (TO-263)
SiHF510STRL-GE3 a
IRF510STRLPbF a
SiHF510STL-E3 a
D2PAK (TO-263)
SiHF510STRR-GE3 a
IRF510STRRPbF a
SiHF510STR-E3 a
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
SYMBOL
VDS
VGS
VGS at 10 V
TC = 25 °C
TC = 100 °C
ID
IDM
Pulsed Drain Current a
Linear Derating Factor
Linear Derating Factor (PCB mount) e
EAS
Single Pulse Avalanche Energy b
IAR
Avalanche Current a
EAR
Repetitive Avalanche Energy a
Maximum Power Dissipation
TC = 25 °C
PD
Maximum Power Dissipation (PCB mount) e
TA = 25 °C
c
dV/dt
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range
TJ, Tstg
for 10 s
Soldering Recommendations (Peak temperature) d
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 4.8 mH, Rg = 25 , IAS = 5.6 A (see fig. 12).
c. ISD  5.6 A, dI/dt  75 A/μs, VDD  VDS, TJ  175 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
S15-2693-Rev. D, 16-Nov-15
LIMIT
100
± 20
5.6
4.0
20
0.29
0.025
75
5.6
4.3
43
3.7
5.5
-55 to +175
300
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Document Number: 91016
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF510S, SiHF510S
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Maximum Junction-to-Ambient 
(PCB mount) a
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
3.5
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0, ID = 250 μA
100
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.12
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 100 V, VGS = 0 V
-
-
25
VDS = 80 V, VGS = 0 V, TJ = 150 °C
-
-
250
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
μA
-
-
0.54

gfs
VDS = 50 V, ID = 3.4 A b
1.3
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
180
-
-
81
-
-
15
-
-
-
8.3
-
-
2.3
RDS(on)
ID = 3.4 A b
VGS = 10 V
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
3.8
Turn-On Delay Time
td(on)
-
6.9
-
tr
-
16
-
-
15
-
-
9.4
-
-
4.5
-
-
7.5
-
-
-
5.6
-
-
20
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 10 V
ID = 5.6 A, VDS = 80 V,
see fig. 6 and fig. 13 b
VDD = 50 V, ID = 5.6 A,
Rg = 24 , RD = 8.4 , see fig. 10 b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
pF
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current a
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the 
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 5.6 A, VGS = 0
S
Vb
TJ = 25 °C, IF = 5.6 A, dI/dt = 100 A/μs b
-
-
2.5
V
-
100
200
ns
-
0.44
0.88
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
S15-2693-Rev. D, 16-Nov-15
Document Number: 91016
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF510S, SiHF510S
www.vishay.com
Vishay Siliconix
VGS
Top
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
100
4.5 V
20 μs pulse width
TC = 25 °C
10-1
100
101
VDS, Drain-to-Source Voltage (V)
91016_01
Fig. 1 - Typical Output Characteristics, TC = 25 °C
ID, Drain Current (A)
ID = 5.6 A
VGS = 10 V
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
400
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
101
3.0
91016_04
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
Top
100
320
4.5 V
Capacitance (pF)
ID, Drain Current (A)
101
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
240
Ciss
160
Coss
80
Crss
20 μs pulse width
TC = 175 °C
100
10-1
100
VDS, Drain-to-Source Voltage (V)
91016_02
25 °C
175 °C
100
20 μs pulse width
VDS = 50 V
10-1
4
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S15-2693-Rev. D, 16-Nov-15
VGS, Gate-to-Source Voltage (V)
ID, Drain Current (A)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
101
101
VDS, Drain-to-Source Voltage (V)
91016_05
Fig. 2 - Typical Output Characteristics, TC = 175 °C
91016_03
0
101
ID = 5.6 A
VDS = 80 V
16
VDS = 50 V
VDS = 20 V
12
8
4
For test circuit
see figure 13
0
10
0
91016_06
2
4
6
8
10
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91016
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF510S, SiHF510S
www.vishay.com
Vishay Siliconix
175 °C
100
5.0
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
6.0
25 °C
4.0
3.0
2.0
1.0
10-1
VGS = 0 V
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0.0
1.2
25
VSD, Source-to-Drain Voltage (V)
91016_07
50
ID, Drain Current (A)
125
150
RD
VDS
Operation in this area limited
by RDS(on)
VGS
2
D.U.T.
Rg
10
175
Fig. 9 - Maximum Drain Current vs. Case Temperature
102
5
100
TC, Case Temperature (°C)
91016_09
Fig. 7 - Typical Source-Drain Diode Forward Voltage
75
+
- VDD
100 µs
5
10 V
1 ms
2
1
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
10 ms
Fig. 10a - Switching Time Test Circuit
5
TC = 25 °C
TJ = 175 °C
single pulse
2
0.1
2
1
5
10
2
5
VDS
102
2
5
90 %
103
VDS, Drain-to-Source Voltage (V)
91016_08
Fig. 8 - Maximum Safe Operating Area
10 %
VGS
td(on)
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
0 - 0.5
1
0.2
0.1
0.1
0.05
0.02
0.01
PDM
t1
Single pulse
(thermal response)
t2
Notes:
1. Duty factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5
91016_11
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S15-2693-Rev. D, 16-Nov-15
Document Number: 91016
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF510S, SiHF510S
www.vishay.com
Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
QG
VGS
D.U.T
Rg
+
-
I AS
QGS
QGD
V DD
VG
10 V
0.01 Ω
tp
Charge
Fig. 13a - Basic Gate Charge Waveform
Fig. 12a - Unclamped Inductive Test Circuit
Current regulator
Same type as D.U.T.
VDS
tp
50 kΩ
VDD
12 V
0.2 µF
0.3 µF
+
VDS
D.U.T.
-
VDS
VGS
IAS
3 mA
IG
ID
Current sampling resistors
Fig. 12b - Unclamped Inductive Waveforms
Fig. 13b - Gate Charge Test Circuit
EAS, Single Pulse Energy (mJ)
300
ID
Top
2.3 A
4.0 A
Bottom 5.6 A
250
200
150
100
50
VDD = 25 V
0
25
91016_12c
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
S15-2693-Rev. D, 16-Nov-15
Document Number: 91016
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF510S, SiHF510S
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
+
-
-
Rg
•
•
•
•
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91016.
S15-2693-Rev. D, 16-Nov-15
Document Number: 91016
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
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1
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12
1
Document Number: 91000