IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • - 200 RDS(on) () VGS = - 10 V 3 Qg (Max.) (nC) 11 Qgs (nC) 7 Qgd (nC) 4 Configuration Single Surface Mount Available in Tape and Reel Dynamic dV/dt Rating P-Channel Fast Switching Ease of Paralleling Simple Drive Requirements Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 Note * Lead (Pb)-containing terminations are not RoHS-compliant. Exemptions may apply. S D2PAK (TO-263) DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK (TO-263) is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK (TO-263) is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2 W in a typical surface mount application. G G D D S P-Channel MOSFET ORDERING INFORMATION D2PAK (TO-263) Package SiHF9610S-GE3 Lead (Pb)-free and Halogen-free SiHF9610STRR-GE3 SiHF9610STRL-GE3 IRF9610SPbF SiHF9610S-E3 Lead (Pb)-free IRF9610STRRPbF IRF9610STRLPbF ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS - 200 Gate-Source Voltage VGS ± 20 Continuous Drain Current VGS at - 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID IDM -1 0.16 0.025 TC = 25 °C TA = 25 °C Peak Diode Recovery dV/dtb Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s PD A -7 Linear Derating Factor (PCB Mount)d Maximum Power Dissipation (PCB Mount)d V - 1.8 Linear Derating Factor Maximum Power Dissipation UNIT 20 3 dV/dt -5 TJ, Tstg - 55 to + 150 300c W/°C W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5). b. ISD - 1.8 A, dI/dt 70 A/μs, VDD VDS, TJ 150 °C. c. 1.6 mm from case. d. When mounted on 1" square PCB (FR-4 or G-10 material). S12-1558-Rev. D, 02-Jul-12 Document Number: 91081 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - 62 Maximum Junction-to-Ambient (PCB Mount)a RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 6.4 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS VGS = 0, ID = - 250 μA - 200 - - V VDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.23 - V/°C VGS(th) VDS = VGS, ID = - 250 μA -2 - -4 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = - 200 V, VGS = 0 V - - - 100 VDS = - 160 V, VGS = 0 V, TJ = 125 °C - - - 500 Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs μA - - 3 VDS = - 50 V, ID = - 0.90 Ab 0.90 - - S VGS = 0 V, VDS = - 25 V, f = 1 MHz, see fig. 10 - 170 - - 50 - - 15 - - - 11 ID = - 0.90 Ab VGS = - 10 V Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs - - 7 Gate-Drain Charge Qgd - - 4 Turn-On Delay Time td(on) - 8 - tr - 15 - - 1 - - 8 - - 4.5 - - 7.5 - - - - 1.8 - - -7 - - - 5.8 - 240 360 ns - 1.7 2.6 μC Rise Time Turn-Off Delay Time Fall Time td(off) VGS = - 10 V ID = - 3.5 A, VDS = - 160 V, see fig. 11 and 18b VDD = - 100 V, ID = - 0.90 A, RG = 50 , RD = 110 , see fig. 17b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = - 1.8 A, VGS = 0 Vb TJ = 25 °C, IF = - 1.8 A, dI/dt = 100 A/μsb V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5). b. Pulse width 300 μs; duty cycle 2 %. S12-1558-Rev. D, 02-Jul-12 Document Number: 91081 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) - 2.40 - 2.40 -7V VGS = - 10, - 9, - 8 V VGS = - 10, - 9, - 8, - 7 V - 1.92 - 1.44 ID, Drain Current (A) ID, Drain Current (A) - 1.92 -6V - 0.96 -5V - 0.48 - 1.44 - 0.96 -5V - 0.48 80 µs Pulse Test 80 µs Pulse Test -4V -4V 0.00 0.00 - 10 0 - 30 - 20 - 40 - 50 -2 0 VDS, Drain-to-Source Voltage (V) 91081_01 102 TJ = 25 °C TJ = 125 °C - 0.96 - 0.48 80 µs Pulse Test VDS > ID(on) x RDS(on) max. 0.00 -2 0 -4 -6 -8 2 5 100 µs 2 1 ms 1 5 10 ms TC = 25 °C TJ = 150 °C Single Pulse 2 0.1 1 2 5 2 10 5 2 102 5 103 Negative VDS, Drain-to-Source Voltage (V) 91081_04 Fig. 2 - Typical Transfer Characteristics ZthJC(t)/RthJC, Normalized Effective Transie Thermal Impedence (Per Unit) - 10 10 - 10 VGS, Gate-to-Source Voltage (V) 91081_02 -8 Operation in this area limited by RDS(on) 5 Negative ID, Drain Current (A) TJ = - 55 °C - 1.44 -6 Fig. 3 - Typical Saturation Characteristics - 2.40 - 1.92 -4 VDS, Drain-to-Source Voltage (V) 91081_03 Fig. 1 - Typical Output Characteristics ID, Drain Current (A) -6V Fig. 4 - Maximum Safe Operating Area 2.0 1.0 0.5 D = 0.5 0.2 0.2 0.1 0.1 0.05 0.02 PDM t1 t2 0.05 0.02 0.01 0.01 10-5 Notes: 1. Duty Factor, D = t1/t2 2. Per Unit Base = RthJC = 6.4 °C/W 3. TJM - TC = PDM ZthJC(t) Single Pulse (Transient Thermal Impedence) 2 5 10-4 2 5 10-3 2 5 10-2 2 5 0.1 2 5 1.0 2 5 10 t1, Square Wave Pulse Duration (s) 91081_05 Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to.Case vs. Pulse Duration S12-1558-Rev. D, 02-Jul-12 Document Number: 91081 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9610S, SiHF9610S www.vishay.com 2.0 gfs,Transconductance (S) 80 µs Pulse Test VDS > ID(on) x RDS(on) max. 1.6 TJ = - 55 °C 1.2 TJ = 25 °C TJ = 125 °C 0.8 0.4 0.0 0 - 0.48 - 0.96 - 1.44 - 1.92 2.5 ID = - 0.6 A VGS = - 10 V 2.0 1.5 1.0 0.5 0.0 - 40 - 2.40 ID, Drain Current (A) 91081_06 RDS(on), Drain-to-Source On Resistance (Normalized) Vishay Siliconix 91081_09 Fig. 6 - Typical Transconductance vs. Drain Current 0 40 500 C, Capacitance (pF) ID, Drain Current (A) - 1.0 TJ = 150 °C TJ = 25 °C - 0.5 160 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd C ,C Coss = Cds + gs gd Cgs + Cgd 400 - 2.0 120 Fig. 9 - Normalized On-Resistance vs. Temperature - 10.0 - 5.0 80 TJ, Junction Temperature (°C) ≈ Cgs + Cgd 300 Ciss 200 Coss 100 Crss - 0.2 0 - 0.1 - 2.0 - 10 0 - 3.2 - 4.4 - 5.6 - 6.8 - 8.0 - 30 - 40 - 50 VSD, Source-to-Drain Voltage (V) 91081_07 1.25 1.15 1.05 0.95 0.85 0.75 - 40 91081_08 Fig. 10 - Typical Capacitance vs. Drain-to-Source Voltage Negative VGS, Gate-to-Source Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage BVDSS, Drain-to-Source Breakdown Voltage (Normalized) - 20 VDS, Drain-to-Source Voltage (V) 91081_10 0 40 80 120 TJ, Junction Temperature (°C) Fig. 8 - Breakdown Voltage vs. Temperature S12-1558-Rev. D, 02-Jul-12 160 91081_11 20 ID = - 1.8 A VDS = - 100 V 16 VDS = - 60 V VDS = - 40 V 12 8 4 For test circuit see figure 18 0 0 2 4 6 8 QG, Total Gate Charge (nC) Fig. 11 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91081 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9610S, SiHF9610S www.vishay.com 7 20 5 PD, Power Dissipation (W) RDS(on) measured with current pulse of 2.0 µs duration. Initial TJ = 25 °C. (Heating effect of 2.0 µs pulse is minimal.) 6 RDS(on), Drain-to-Source On Resistance (Ω) Vishay Siliconix VGS = - 10 V 4 3 VGS = - 20 V 2 1 15 10 5 0 0 0 -1 -2 -3 -4 -5 -6 ID, Drain Current (A) 91081_12 0 -7 20 Fig. 12 - Typical On-Resistance vs. Drain Current 40 60 80 100 120 140 TC, Case Temperature (°C) 91081_14 Fig. 14 - Power vs. Temperature Derating Curve L Vary tp to obtain required IL VGS = - 10 V 2.0 VDS V DD D.U.T. tp + EC Negative ID, Drain Current (A) 0.05 Ω IL 1.6 VDD = 0.5 VDS EC = 0.75 VDS Fig. 15 - Clamped Inductive Test Circuit 1.2 0.8 VDD 0.4 IL 0.0 25 91081_13 50 75 100 125 150 TC, Case Temperature (°C) Fig. 13 - Maximum Drain Current vs. Case Temperature S12-1558-Rev. D, 02-Jul-12 tp VDS EC Fig. 16 - Clamped Inductive Waveforms Document Number: 91081 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix RD VDS QG - 10 V VGS D.U.T. Rg QGS +VDD QGD VG - 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Charge Fig. 17a - Switching Time Test Circuit Fig. 18a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. td(on) tr td(off) tf VGS 50 kΩ 12 V 0.2 µF 0.3 µF 10 % - D.U.T. 90 % VDS + VDS VGS - 3 mA IG ID Current sampling resistors Fig. 17b - Switching Time Waveforms S12-1558-Rev. D, 02-Jul-12 Fig. 18b - Gate Charge Test Circuit Document Number: 91081 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg + • dV/dt controlled by Rg • ISD controlled by duty factor “D” • D.U.T. - device under test + - VDD Note • Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = - 5 V for logic level and - 3 V drive devices Fig. 19 - For P-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91081. S12-1558-Rev. D, 02-Jul-12 Document Number: 91081 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000