IRF820S, SiHF820S, IRF820L, SiHF820L www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • 500 RDS(on) () VGS = 10 V 3.0 Qg (Max.) (nC) 24 Qgs (nC) 3.3 Qgd (nC) 13 Configuration Single D D2PAK (TO-263) I2PAK (TO-262) G G D S Surface mount Available in tape and reel Available Dynamic dV/dt rating Repetitive avalanche rated Available Fast switching Ease of paralleling Simple drive requirements Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. G D DESCRIPTION S Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK (TO-263) is a surface mount power package capable of accommodating die size up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK (TO-263) is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. S N-Channel MOSFET ORDERING INFORMATION Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) I2PAK (TO-262) Lead (Pb)-free and halogen-free SiHF820S-GE3 SiHF820STRL-GE3 a SiHF820STRR-GE3 a SiHF820L-GE3 Lead (Pb)-free IRF820SPbF IRF820STRLPbF a IRF820STRRPbF a IRF820LPbF Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 500 Gate-Source Voltage VGS ± 20 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID IDM 1.6 0.40 0.025 Avalanche Current Repetitive Avalanche Energy a Maximum Power Dissipation TC = 25 °C Maximum Power Dissipation (PCB mount) e TA = 25 °C Peak Diode Recovery dV/dt c Operating Junction and Storage Temperature Range Soldering Recommendations (Peak temperature) d for 10 s A 8.0 Linear Derating Factor a V 2.5 Linear Derating Factor (PCB mount) e Single Pulse Avalanche Energy b UNIT W/°C EAS 210 IAR 2.5 A EAR 5.0 mJ PD 50 3.1 dV/dt 3.5 TJ, Tstg -55 to +150 300 mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 60 mH, Rg = 25 , IAS = 2.5 A (see fig. 12). c. ISD 2.5 A, dI/dt 50 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). S15-1659-Rev. D, 20-Jul-15 Document Number: 91060 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820S, SiHF820S, IRF820L, SiHF820L www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - 62 Maximum Junction-to-Ambient (PCB mount) a RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 2.5 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0, ID = 250 μA 500 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.59 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance μA - - 3.0 gfs VDS = 50 V, ID = 1.5 Ab 1.5 - - S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 360 - - 92 - - 37 - - - 24 - - 3.3 RDS(on) ID = 1.5 Ab VGS = 10 V Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd - - 13 Turn-On Delay Time td(on) - 8.0 - tr - 8.6 - - 33 - - 16 - - 4.5 - - 7.5 - - - 2.5 - - 8.0 Rise Time Turn-Off Delay Time Fall Time td(off) VGS = 10 V ID = 2.1 A, VDS = 400 V, see fig. 6 and 13b VDD = 250 V, ID = 2.1 A, Rg = 18 , RD = 100 , see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 2.5 A, VGS = 0 S Vb TJ = 25 °C, IF = 2.1 A, dI/dt = 100 A/μsb - - 1.6 V - 260 520 ns - 0.70 1.4 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. S15-1659-Rev. D, 20-Jul-15 Document Number: 91060 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820S, SiHF820S, IRF820L, SiHF820L www.vishay.com Vishay Siliconix VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V ID, Drain Current (A) Top 100 4.5 V 20 µs Pulse Width TC = 25 °C 10-1 100 101 VDS, Drain-to-Source Voltage (V) 91060_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 ID = 2.1 A VGS = 10 V 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 TJ, Junction Temperature (°C) 91060_04 Fig. 1 - Typical Output Characteristics, TC = 25 °C 20 40 60 80 100 120 140 160 Fig. 4 - Normalized On-Resistance vs. Temperature 800 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 100 4.5 V Capacitance (pF) ID, Drain Current (A) Top 600 Ciss 400 Coss 200 20 µs Pulse Width TC = 150 °C 10-1 100 VDS, Drain-to-Source Voltage (V) 91060_02 Crss 0 100 101 VDS, Drain-to-Source Voltage (V) 91060_05 Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 25 °C 100 10-1 20 µs Pulse Width VDS = 50 V VGS, Gate-to-Source Voltage (V) ID, Drain Current (A) 20 150 °C 101 ID = 2.1 A VDS = 400 V 16 VDS = 250 V VDS = 100 V 12 8 4 For test circuit see figure 13 0 4 91060_03 5 6 7 8 9 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S15-1659-Rev. D, 20-Jul-15 10 0 91060_06 4 8 12 16 20 24 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91060 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820S, SiHF820S, IRF820L, SiHF820L www.vishay.com Vishay Siliconix 100 ID, Drain Current (A) ISD, Reverse Drain Current (A) 2.5 150 °C 25 °C 2.0 1.5 1.0 0.5 VGS = 0 V 0.4 0.6 0.8 0.0 1.2 1.0 25 VSD, Source-to-Drain Voltage (V) 91060_07 ID, Drain Current (A) 125 VGS 10 µs D.U.T. Rg 5 + - VDD 100 µs 2 1 10 V 1 ms Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 5 10 ms 2 150 RD VDS 2 10 100 Fig. 9 - Maximum Drain Current vs. Case Temperature Operation in this area limited by RDS(on) 5 75 TC, Case Temperature (°C) 91060_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage 102 50 0.1 Fig. 10a - Switching Time Test Circuit 5 TC = 25 °C TJ = 150 °C Single Pulse 2 10-2 0.1 2 5 2 1 5 10 2 5 102 VDS 2 5 2 103 5 90 % 104 VDS, Drain-to-Source Voltage (V) 91060_08 Fig. 8 - Maximum Safe Operating Area 10 % VGS td(on) td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 D = 0.5 0.2 PDM 0.1 0.05 0.1 0.02 0.01 t1 Single Pulse (Thermal Response) t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-2 10-5 91060_11 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S15-1659-Rev. D, 20-Jul-15 Document Number: 91060 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820S, SiHF820S, IRF820L, SiHF820L www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T Rg + - I AS V DD VDS 10 V 0.01 W tp IAS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms EAS, Single Pulse Energy (mJ) 500 ID 1.1 A 1.6 A Bottom 2.5 A Top 400 300 200 100 0 VDD = 50 V 25 91060_12c 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S15-1659-Rev. D, 20-Jul-15 Fig. 13b - Gate Charge Test Circuit Document Number: 91060 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820S, SiHF820S, IRF820L, SiHF820L www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91060. S15-1659-Rev. D, 20-Jul-15 Document Number: 91060 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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