IRFBC40AS, SiHFBC40AS www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Low gate charge Qg results in simple drive requirement 600 RDS(on) () VGS = 10 V 1.2 Qg max. (nC) 42 Qgs (nC) 10 Qgd (nC) 20 Configuration • Effective Coss specified D • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 D2PAK (TO-263) Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. G APPLICATIONS S S Available • Fully characterized capacitance and avalanche voltage and current Single G D Available • Improved gate, avalanche and dynamic dV/dt ruggedness • Switch mode power supply (SMPS) N-Channel MOSFET • Uninterruptible power supply • High speed power switching TYPICAL SMPS TOPOLOGIES • Single transistor forward ORDERING INFORMATION Package D2PAK (TO-263) D2PAK (TO-263) Lead (Pb)-free and Halogen-free SiHFBC40AS-GE3 SiHFBC40ASTRL-GE3 a SiHFBC40ASTRR-GE3 a IRFBC40ASPbF IRFBC40ASTRLPbF a IRFBC40ASTRRPbF a SiHFBC40AS-E3 SiHFBC40ASTL-E3 a SiHFBC40ASTR-E3 a Lead (Pb)-free D2PAK (TO-263) Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current e VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a, e ID UNIT V 6.2 3.9 A IDM 25 1.0 W/°C EAS 570 mJ Current a IAR 6.2 A Repetitive Avalanche Energy a EAR 13 mJ Linear Derating Factor Single Pulse Avalanche Energy b Repetitive Avalanche Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dt c, e Operating Junction and Storage Temperature Range Soldering Recommendations (Peak temperature) d for 10 s PD 125 W dV/dt 6.0 V/ns TJ, Tstg -55 to +150 300 °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 29.6 mH, Rg = 25 , IAS = 6.2 A (see fig. 12). c. ISD 6.2 A, dI/dt 88 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. e. Uses IRFBC40A, SiHFBC40A data and test conditions. S16-0763-Rev. D, 02-May-16 Document Number: 91113 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40AS, SiHFBC40AS www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 1.0 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VDS VGS = 0 V, ID = 250 μA 600 - - VDS/TJ Reference to 25 °C, ID = 1 mA d - 0.66 - V V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V nA IGSS IDSS VGS = ± 30 V - - ± 100 VDS = 600 V, VGS = 0 V - - 25 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 250 μA - - 1.2 gfs VDS = 50 V, ID = 3.7 A 3.4 - - S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 1036 - - 136 - - 7.0 - - 1487 - RDS(on) ID = 3.7 A b VGS = 10 V Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Output Capacitance Output Capacitance Effective Total Gate Charge Gate-Source Charge Coss VDS = 1.0 V, f = 1.0 MHz VGS = 0 V Coss eff. VDS = 480 V, f = 1.0 MHz - 36 - VDS = 0 V to 480 V c - 48 - - - 42 - - 10 Qg Qgs VGS = 10 V ID = 6.2 A, VDS = 480 V, see fig. 6 and 13 b Gate-Drain Charge Qgd - - 20 Turn-On Delay Time td(on) - 13 - Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VDD = 300 V, ID = 6.2 A, Rg = 9.1 , RD = 47 see fig. 10 b - 23 - - 31 - - 18 - f = 1 MHz, open drain 0.6 - 3.9 - - 6.2 - - 25 pF nC ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Current a Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 6.2 A, VGS = 0 S Vb TJ = 25 °C, IF = 6.2 A, dI/dt = 100 A/μs b - - 1.5 V - 431 647 ns - 1.8 2.8 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. c. COSS eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS. d. Uses IRHFBC40A, SiHFBC40A data and test conditions. S16-0763-Rev. D, 02-May-16 Document Number: 91113 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40AS, SiHFBC40AS www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature S16-0763-Rev. D, 02-May-16 Document Number: 91113 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40AS, SiHFBC40AS www.vishay.com Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area S16-0763-Rev. D, 02-May-16 Document Number: 91113 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40AS, SiHFBC40AS www.vishay.com Vishay Siliconix RD VDS VGS D.U.T. Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS 15 V tp L VDS Rg D.U.T IAS 20 V tp Driver + A - VDD IAS 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit S16-0763-Rev. D, 02-May-16 Fig. 12b - Unclamped Inductive Waveforms Document Number: 91113 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40AS, SiHFBC40AS www.vishay.com Vishay Siliconix QG 10 V QGS QGD VG Charge Fig. 13a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. Fig. 12c - Maximum Avalanche Energy vs. Drain Current 50 kΩ 12 V 0.2 µF 0.3 µF + D.U.T. - VDS VGS 3 mA IG ID Current sampling resistors Fig. 13b - Gate Charge Test Circuit Fig. 12d - Maximum Avalanche Energy vs. Drain Current S16-0763-Rev. D, 02-May-16 Document Number: 91113 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40AS, SiHFBC40AS www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91113. S16-0763-Rev. D, 02-May-16 Document Number: 91113 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000