IRFR9310, IRFU9310, SiHFR9310, SiHFU9310 Datasheet

IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
•
•
•
•
•
•
•
- 400
RDS(on) ()
VGS = - 10 V
7.0
Qg (Max.) (nC)
13
Qgs (nC)
3.2
Qgd (nC)
5.0
Configuration
Single
S
DPAK
(TO-252)
DESCRIPTION
Third generation power MOSFETs from Vishay utilize
advanced processing techniques to achieve low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU/SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
IPAK
(TO-251)
G
D
D
G
S
G
P-Channel
Surface Mount (IRFR9310, SiHFR9310)
Straight Lead (IRFU9310, SiHFU9310)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
D S
D
P-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
IPAK (TO-251)
Lead (Pb)-free and
Halogen-free
SiHFR9310-GE3
SiHFR9310TRL-GE3
SiHFR9310TR-GE3
SiHFR9310TRR-GE3
SiHFU9310-GE3
IRFR9310PbF
IRFR9310TRLPbFa
IRFR9310TRPbFa
IRFR9310TRRPbFa
IRFU9310PbF
SiHFR9310-E3
SiHFR9310TL-E3a
SiHFR9310T-E3a
SiHFR9310TR-E3a
SiHFU9310-E3
Lead (Pb)-free
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
- 400
Gate-Source Voltage
VGS
± 20
Continuous Drain Current
VGS at - 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
IDM
Linear Derating Factor
Energyb
UNIT
V
- 1.8
- 1.1
A
- 7.2
0.40
W/°C
mJ
EAS
92
Repetitive Avalanche Currenta
IAR
- 1.8
A
Repetitive Avalanche Energya
EAR
5.0
mJ
Single Pulse Avalanche
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d
for 10 s
PD
50
W
dV/dt
- 24
V/ns
TJ, Tstg
- 55 to + 150
300
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 57 mH, Rg = 25 , IAS = - 1.8 A (see fig. 12).
c. ISD  - 1.1 A, dI/dt  450 A/μs, VDD  VDS, TJ  150 °C.
d. 1.6 mm from case.
S13-0166-Rev. D, 04-Feb-13
Document Number: 91284
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
-
-
50
Maximum Junction-to-Case (Drain)
RthJC
-
-
2.5
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = - 250 μA
- 400
-
-
V
VDS/TJ
Reference to 25 °C, ID = - 1 mA
-
- 0.41
-
V/°C
VGS(th)
VDS = VGS, ID = - 250 μA
- 2.0
-
- 4.0
V
nA
IGSS
IDSS
VGS = ± 20 V
-
-
± 100
VDS = - 400 V, VGS = 0 V
-
-
- 100
VDS = - 320 V, VGS = 0 V, TJ = 125 °C
-
-
- 500
μA
-
-
7.0

gfs
VDS = - 50 V, ID = - 1.1 A
0.91
-
-
S
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
-
270
-
-
50
-
-
8.0
-
-
-
13
RDS(on)
ID = - 1.1 Ab
VGS = - 10 V
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
3.2
Gate-Drain Charge
Qgd
-
-
5.0
Turn-On Delay Time
td(on)
-
11
-
tr
-
10
-
-
25
-
-
24
-
-
4.5
-
-
7.5
-
-
-
- 1.9
S
-
-
- 7.6
TJ = 25 °C, IS = - 1.1 A, VGS = 0 Vb
-
-
- 4.0
V
-
170
260
ns
-
640
960
nC
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
VGS = - 10 V
ID = - 1.1 A, VDS = - 320 V,
see fig. 6 and 13b
VDD = - 200 V, ID = - 1.1 A,
Rg = 21 , RD = 180 , see fig. 10b
Between lead,
6 mm (0.25") from
package and center of
die contactc
D
pF
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IF = -1.1 A, dI/dt = 100 A/μsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. This is applied for IPAK, LS of DPAK is measured between lead and center of die contact.
S13-0166-Rev. D, 04-Feb-13
Document Number: 91284
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10
10
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
-I D , Drain-to-Source Current (A)
-I D , Drain-to-Source Current (A)
TOP
1
-4.5V
20μs PULSE WIDTH
TJ = 25 °C
0.1
1
10
100
TJ = 25 ° C
TJ = 150 ° C
1
V DS = -50V
20μs PULSE WIDTH
0.1
4
-VDS , Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
2.5
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
-I D , Drain-to-Source Current (A)
TOP
1
-4.5V
0.1
20μs PULSE WIDTH
TJ = 150 °C
1
10
-VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
S13-0166-Rev. D, 04-Feb-13
6
7
8
9
10
Fig. 3 - Typical Transfer Characteristics
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
10
5
-VGS, Gate-to-Source Voltage (V)
ID = -1.8A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = -10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91284
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
400
Ciss
300
200
Coss
100
Crss
10
-ISD , Reverse Drain Current (A)
500
Vishay Siliconix
0
1
10
TJ = 150 ° C
1
TJ = 25 ° C
0.1
1.0
100
-VDS , Drain-to-Source Voltage (V)
3.0
4.0
5.0
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
ID = -1.1A
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VDS =-320V
VDS =-200V
VDS =-80V
16
-IID , Drain Current (A)
-VGS , Gate-to-Source Voltage (V)
2.0
-VSD ,Source-to-Drain Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
V GS = 0 V
12
8
10
10us
100us
1
1ms
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
4
8
12
16
QG , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S13-0166-Rev. D, 04-Feb-13
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
10
10ms
100
1000
-VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91284
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
RD
VDS
2.0
VGS
1.6
-ID , Drain Current (A)
D.U.T.
Rg
+VDD
- 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
1.2
Fig. 10a - Switching Time Test Circuit
0.8
td(on)
0.4
td(off) tf
tr
VGS
10 %
0.0
25
50
75
100
125
150
TC , Case Temperature ( °C)
90 %
VDS
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
0.01
0.00001
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S13-0166-Rev. D, 04-Feb-13
Document Number: 91284
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
L
VDS
IAS
Rg
+ VDD
A
D.U.T.
IAS
- 20 V
tp
Driver
0.01 Ω
tp
15 V
VDS
Fig. 12b - Unclamped Inductive Waveforms
EAS , Single Pulse Avalanche Energy (mJ)
Fig. 12a - Unclamped Inductive Test Circuit
300
ID
-0.49A
-0.7A
BOTTOM -1.1A
TOP
250
200
150
100
50
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
QGS
-
QGD
D.U.T.
VG
+ VDS
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S13-0166-Rev. D, 04-Feb-13
Fig. 13b - Gate Charge Test Circuit
Document Number: 91284
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
+
• dV/dt controlled by Rg
• ISD controlled by duty factor “D”
• D.U.T. - device under test
+
-
VDD
Note
• Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91284.
S13-0166-Rev. D, 04-Feb-13
Document Number: 91284
7
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-252AA Case Outline
E
MILLIMETERS
A
C2
e
b2
D1
e1
E1
L
gage plane height (0.5 mm)
L4
b
L5
H
D
L3
b3
C
A1
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
2.18
2.38
0.086
0.094
A1
-
0.127
-
0.005
b
0.64
0.88
0.025
0.035
b2
0.76
1.14
0.030
0.045
b3
4.95
5.46
0.195
0.215
0.024
C
0.46
0.61
0.018
C2
0.46
0.89
0.018
0.035
D
5.97
6.22
0.235
0.245
D1
4.10
-
0.161
-
E
6.35
6.73
0.250
0.265
E1
4.32
-
0.170
-
H
9.40
10.41
0.370
0.410
e
2.28 BSC
e1
0.090 BSC
4.56 BSC
0.180 BSC
L
1.40
1.78
0.055
0.070
L3
0.89
1.27
0.035
0.050
L4
-
1.02
-
0.040
L5
1.01
1.52
0.040
0.060
ECN: T16-0236-Rev. P, 16-May-16
DWG: 5347
Notes
• Dimension L3 is for reference only.
Revision: 16-May-16
Document Number: 71197
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-251AA (HIGH VOLTAGE)
4
3
E1
E
Thermal PAD
4
b4
θ2
4
A
0.010 0.25 M C A B
L2 4
c2
A
θ1
B
D
D1
A
C
3
Seating
plane
5
C
L1 L3
(Datum A)
C
L
B
B
A
A1
3 x b2
View A - A
2xe
c
3xb
0.010 0.25 M C A B
Plating
5
b1, b3
Base
metal
Lead tip
c1
(c)
5
(b, b2)
Section B - B and C - C
MILLIMETERS
DIM.
MIN.
MAX.
INCHES
MIN.
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
2.18
2.39
0.086
0.094
D1
5.21
-
0.205
-
A1
0.89
1.14
0.035
0.045
E
6.35
6.73
0.250
0.265
4.32
-
0.170
-
b
0.64
0.89
0.025
0.035
E1
b1
0.65
0.79
0.026
0.031
e
b2
0.76
1.14
0.030
0.045
L
8.89
9.65
0.350
0.380
b3
0.76
1.04
0.030
0.041
L1
1.91
2.29
0.075
0.090
b4
4.95
5.46
0.195
0.215
L2
0.89
1.27
0.035
0.050
2.29 BSC
2.29 BSC
c
0.46
0.61
0.018
0.024
L3
1.14
1.52
0.045
0.060
c1
0.41
0.56
0.016
0.022
θ1
0'
15'
0'
15'
c2
0.46
0.86
0.018
0.034
θ2
25'
35'
25'
35'
D
5.97
6.22
0.235
0.245
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
Document Number: 91362
Revision: 15-Sep-08
www.vishay.com
1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72594
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000