IRFR9310, IRFU9310, SiHFR9310, SiHFU9310 Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • - 400 RDS(on) (Ω) VGS = - 10 V 7.0 Qg (Max.) (nC) 13 Qgs (nC) 3.2 Qgd (nC) 5.0 Configuration Single P-Channel Surface Mount (IRFR9310/SiHFR9310) Straight Lead (IRFU9310/SiHFU9310) Advanced Process Technology Fast Switching Fully Avalanche Rated Lead (Pb)-free Available Available RoHS* COMPLIANT DESCRIPTION S D PAK (TO-252) IPAK (TO-251) Third generation Power MOSFETs from Vishay utilize advanced processing techniques to achieve low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU/SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. G D P-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251) IRFR9310PbF IRFR9310TRLPbFa IRFR9310TRPbFa IRFR9310TRRPbFa IRFU9310PbF SiHFR9310-E3 SiHFR9310TL-E3a SiHFR9310T-E3a SiHFR9310TR-E3a SiHFU9310-E3 IRFR9310 IRFR9310TRLa IRFR9310TRa - IRFU9310 SiHFR9310 SiHFR9310TLa SiHFR9310Ta - SiHFU9310 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) SYMBOL VDS VGS VGS at - 10 V TC = 25 °C TC = 100 °C ID IDM TC = 25 °C for 10 s EAS IAR EAR PD dV/dt TJ, Tstg LIMIT - 400 ± 20 - 1.8 - 1.1 - 7.2 0.40 92 - 1.8 5.0 50 - 24 - 55 to + 150 300d UNIT V A W/°C mJ A mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 57 mH, RG = 25 Ω, IAS = - 1.8 A (see fig. 12). c. ISD ≤ - 1.1 A, dI/dt ≤ 450 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. www.kersemi.com 1 IRFR9310, IRFU9310, SiHFR9310, SiHFU9310 THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 2.5 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VDS VGS = 0 V, ID = - 250 µA - 400 - - V ΔVDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.41 - V/°C VGS(th) VDS = VGS, ID = - 250 µA - 2.0 - - 4.0 V nA VGS = ± 20 V - - ± 100 VDS = - 400 V, VGS = 0 V - - - 100 VDS = - 320 V, VGS = 0 V, TJ = 125 °C - - - 500 IGSS IDSS RDS(on) gfs ID = - 1.1 Ab VGS = - 10 V VDS = - 50 V, ID = - 1.1 A µA - - 7.0 Ω 0.91 - - S - 270 - - 50 - - 8.0 - - - 13 Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg VGS = 0 V, VDS = - 25 V, f = 1.0 MHz, see fig. 5 Gate-Source Charge Qgs - - 3.2 Gate-Drain Charge Qgd - - 5.0 Turn-On Delay Time td(on) - 11 - tr - 10 - - 25 - - 24 - - 4.5 - - 7.5 - - - - 1.9 - - - 7.6 - - - 4.0 - 170 260 ns - 640 960 nC Rise Time Turn-Off Delay Time Fall Time td(off) VGS = - 10 V ID = - 1.1 A, VDS = - 320 V, see fig. 6 and 13b pF VDD = - 200 V, ID = - 1.1 A, RG = 21 Ω, RD = 180 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contactc D nC ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode A G S TJ = 25 °C, IS = - 1.1 A, VGS = 0 Vb TJ = 25 °C, IF = -1.1 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. c. This is applied for IPAK, LS of DPAK is measured between lead and center of die contact. www.kersemi.com 2 D V IRFR9310, IRFU9310, SiHFR9310, SiHFU9310 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 10 10 VGS -15V -10V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V -I D , Drain-to-Source Current (A) -I D , Drain-to-Source Current (A) TOP 1 -4.5V 20μs PULSE WIDTH TJ = 25 °C 0.1 1 10 100 TJ = 25 ° C TJ = 150 ° C 1 V DS = -50V 20μs PULSE WIDTH 0.1 4 -VDS , Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics 2.5 VGS -15V -10V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V -I D , Drain-to-Source Current (A) TOP 1 -4.5V 0.1 20μs PULSE WIDTH TJ = 150 °C 1 10 -VDS , Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics 6 7 8 9 10 Fig. 3 - Typical Transfer Characteristics 100 RDS(on) , Drain-to-Source On Resistance (Normalized) 10 5 -VGS, Gate-to-Source Voltage (V) ID = -1.8A 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 VGS = -10V 0 20 40 60 80 100 120 140 160 TJ , Junction Temperature ( °C) Fig. 4 - Normalized On-Resistance vs. Temperature www.kersemi.com 3 IRFR9310, IRFU9310, SiHFR9310, SiHFU9310 VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd C, Capacitance (pF) 400 Ciss 300 200 Coss 100 Crss 10 -ISD , Reverse Drain Current (A) 500 0 1 10 TJ = 150 ° C 1 TJ = 25 ° C 0.1 1.0 100 -VDS , Drain-to-Source Voltage (V) 3.0 4.0 5.0 Fig. 7 - Typical Source-Drain Diode Forward Voltage 100 ID = -1.1A OPERATION IN THIS AREA LIMITED BY RDS(on) VDS =-320V VDS =-200V VDS =-80V 16 -IID , Drain Current (A) -VGS , Gate-to-Source Voltage (V) 2.0 -VSD ,Source-to-Drain Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 20 V GS = 0 V 12 8 10 10us 100us 1 1ms 4 FOR TEST CIRCUIT SEE FIGURE 13 0 0 4 8 12 16 QG , Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.kersemi.com 4 0.1 TC = 25 °C TJ = 150 °C Single Pulse 10 10ms 100 -VDS , Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area 1000 IRFR9310, IRFU9310, SiHFR9310, SiHFU9310 RD VDS 2.0 VGS 1.6 +VDD - 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 1.2 Fig. 10a - Switching Time Test Circuit 0.8 td(on) 0.4 td(off) tf tr VGS 10 % 0.0 25 50 75 100 125 150 TC , Case Temperature ( °C) 90 % VDS Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms 10 Thermal Response (Z thJC ) -ID , Drain Current (A) D.U.T. RG D = 0.50 1 0.20 0.10 0.05 0.1 0.01 0.00001 0.02 0.01 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case www.kersemi.com 5 IRFR9310, IRFU9310, SiHFR9310, SiHFU9310 L VDS IAS + VDD A D.U.T. RG IAS - 20 V tp Driver 0.01 Ω tp 15 V VDS EAS , Single Pulse Avalanche Energy (mJ) Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms 300 ID -0.49A -0.7A BOTTOM -1.1A TOP 250 200 150 100 50 0 25 50 75 100 125 150 Starting TJ , Junction Temperature ( °C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG - 10 V 12 V 0.2 µF 0.3 µF QGS - QGD D.U.T. VG + VDS VGS - 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.kerseemi.com 6 Fig. 13b - Gate Charge Test Circuit IRFR9310, IRFU9310, SiHFR9310, SiHFU9310 Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG + • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test + - VDD Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % * ISD VGS = - 5 V for logic level and - 3 V drive devices Fig. 14 - For P-Channel www.kersemi.com 7