SiHF8N50D www.vishay.com Vishay Siliconix D Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Optimal Design - Low Area Specific On-Resistance - Low Input Capacitance (Ciss) - Reduced Capacitive Switching Losses - High Body Diode Ruggedness - Avalanche Energy Rated (UIS) • Optimal Efficiency and Operation - Low Cost - Simple Gate Drive Circuitry - Low Figure-of-Merit (FOM): Ron x Qg - Fast Switching • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 550 RDS(on) max. at 25 °C () VGS = 10 V 0.85 Qg (max.) (nC) 30 Qgs (nC) 4 Qgd (nC) 7 Configuration Single D TO-220 FULLPAK APPLICATIONS • Consumer Electronics - Displays (LCD or Plasma TV) • Server and Telecom Power Supplies - SMPS • Industrial - Welding - Induction Heating - Motor Drives • Battery Chargers G S G D S N-Channel MOSFET ORDERING INFORMATION Package TO-220 FULLPAK Lead (Pb)-free SiHF8N50D-E3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage LIMIT VDS 500 VGS Gate-Source Voltage AC (f > 1 Hz) Continuous Drain Current (TJ = 150 °C)e SYMBOL VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID IDM Linear Derating Factor Single Pulse Avalanche Energyb Maximum Power Dissipation Operating Junction and Storage Temperature Range Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dtd Soldering Recommendations (Peak Temperature)c for 10 s ± 30 UNIT V 30 8.7 5.5 A 18 0.26 W/°C EAS 29 mJ PD 33 W TJ, Tstg - 55 to + 150 °C dV/dt 24 0.37 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 5 A. c. 1.6 mm from case. d. ISD ID, starting TJ = 25 °C. e. Limited by maximum junction temperature. S12-0691-Rev. A, 02-Apr-12 Document Number: 91490 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50D www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 65 Maximum Junction-to-Case (Drain) RthJC - 3.8 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) VDS VGS = 0 V, ID = 250 μA 500 - - V VDS/TJ Reference to 25 °C, ID = 250 μA - 0.58 - V/°C VGS(th) VDS = VGS, ID = 250 μA 3 - 5 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS Drain-Source On-State Resistance Forward Transconductancea RDS(on) VDS = 500 V, VGS = 0 V - - 1 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 10 - 0.70 0.85 S VGS = 10 V ID = 4 A gfs VDS = 20 V, ID = 4 A - 3 - VGS = 0 V, VDS = 100 V, f = 1 MHz - 527 - - 52 - - 8 - - 46 - - 64 - μA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Effective Output Capacitance, Energy Relatedb Co(er) Effective Output Capacitance, Time Relatedc Co(tr) pF VDS = 0 V to 400 V, VGS = 0 V Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time - 15 30 - 4 - Qgd - 7 - td(on) - 13 26 tr VDD = 400 V, ID = 4 A Rg = 9.1 , VGS = 10 V - 16 32 - 17 34 - 11 22 f = 1 MHz, open drain - 1.8 - - - 8 - - 32 - - 1.2 - 308 - ns - 1.8 - μC - 11 - A td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 4 A, VDS = 400 V nC ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 4 A, VGS = 0 V TJ = 25 °C, IF = IS = 4 A, dI/dt = 100 A/μs, VR = 20 V S V Note a. Repetitive rating; pulse width limited by maximum junction temperature. b. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. c. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S12-0691-Rev. A, 02-Apr-12 Document Number: 91490 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50D www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V 16 12 TJ = 25 °C RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 20 8 4 2.5 2 1.5 1 VGS = 10 V 0.5 0 0 5 10 15 20 25 ID = 4 A 0 - 60 - 40 - 20 0 30 Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics 1000 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V 5.0 V 12 9 Ciss TJ = 150 °C Capacitance (pF) ID, Drain-to-Source Current (A) 15 6 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Coss 100 Crss 10 3 0 1 0 5 10 15 20 25 30 0 VDS, Drain-to-Source Voltage (V) 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 24 VGS, Gate-to-Source Voltage (V) 20 ID, Drain-to-Source Current (A) 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) VDS, Drain-to-Source Voltage (V) 16 12 8 TJ = 150 °C 4 TJ = 25 °C VDS = 400 V VDS = 250 V VDS = 100 V 20 16 12 8 4 0 0 0 5 10 15 20 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S12-0691-Rev. A, 02-Apr-12 25 0 5 10 15 20 25 Qg, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91490 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50D www.vishay.com Vishay Siliconix 10 ISD, Reverse Drain Current (A) 100 ID, Drain Current (A) TJ = 150 °C TJ = 25 °C 10 1 8 6 4 2 VGS = 0 V 0 0.1 0.2 0.4 0.6 0.8 1 1.2 1.4 25 1.6 VSD, Source-Drain Voltage (V) 50 75 100 125 150 TJ, Case Temperature (°C) Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature 625 100 Operation in this area limited by RDS(on) VDS, Drain-to-Source Brakdown Voltage (V) ID, Drain Current (A) 600 10 100 μs 1 1 ms Limited by R DS(on)* 0.1 TC = 25 °C TJ = 150 °C Single Pulse 10 ms 575 550 525 500 BVDSS Limited 0.01 475 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (˚C) Fig. 8 - Maximum Safe Operating Area Fig. 10 - Typical Drain-to-Source Voltage vs. Temperature Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.0001 Single Pulse 0.001 0.01 0.1 1 10 Pulse Time (s) Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case S12-0691-Rev. A, 02-Apr-12 Document Number: 91490 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50D www.vishay.com Vishay Siliconix RD VDS QG 10 V VGS D.U.T. RG QGS + - VDD QGD VG 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Charge Fig. 12 - Switching Time Test Circuit Fig. 16 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. VDS 90 % 50 kΩ 12 V 0.2 µF 0.3 µF + 10 % VGS D.U.T. td(on) td(off) tf tr - VDS VGS 3 mA Fig. 13 - Switching Time Waveforms IG ID Current sampling resistors Fig. 17 - Gate Charge Test Circuit L Vary tp to obtain required IAS VDS D.U.T RG + - IAS V DD 10 V 0.01 Ω tp Fig. 14 - Unclamped Inductive Test Circuit VDS tp VDD VDS IAS Fig. 15 - Unclamped Inductive Waveforms S12-0691-Rev. A, 02-Apr-12 Document Number: 91490 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50D www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 18 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91490. S12-0691-Rev. A, 02-Apr-12 Document Number: 91490 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-220 FULLPAK (HIGH VOLTAGE) A E A1 ØP n d1 d3 D u L1 V L b3 A2 b2 c b e MILLIMETERS DIM. A A1 A2 b b2 b3 c D d1 d3 E e L L1 n ØP u v ECN: X09-0126-Rev. B, 26-Oct-09 DWG: 5972 MIN. 4.570 2.570 2.510 0.622 1.229 1.229 0.440 8.650 15.88 12.300 10.360 INCHES MAX. 4.830 2.830 2.850 0.890 1.400 1.400 0.629 9.800 16.120 12.920 10.630 MIN. 0.180 0.101 0.099 0.024 0.048 0.048 0.017 0.341 0.622 0.484 0.408 13.730 3.500 6.150 3.450 2.500 0.500 0.520 0.122 0.238 0.120 0.094 0.016 2.54 BSC 13.200 3.100 6.050 3.050 2.400 0.400 MAX. 0.190 0.111 0.112 0.035 0.055 0.055 0.025 0.386 0.635 0.509 0.419 0.100 BSC 0.541 0.138 0.242 0.136 0.098 0.020 Notes 1. To be used only for process drawing. 2. These dimensions apply to all TO-220, FULLPAK leadframe versions 3 leads. 3. All critical dimensions should C meet Cpk > 1.33. 4. All dimensions include burrs and plating thickness. 5. No chipping or package damage. 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