SHENZHENFREESCALE SIHD3N50D

SiHD3N50D
D Series Power MOSFET
FEATURES
• Optimal Design
- Low Area Specific On-Resistance
- Low Input Capacitance (Ciss)
- Reduced Capacitive Switching Losses
- High Body Diode Ruggedness
- Avalanche Energy Rated (UIS)
• Optimal Efficiency and Operation
- Low Cost
- Simple Gate Drive Circuitry
- Low Figure-of-Merit (FOM): Ron x Qg
PRODUCT SUMMARY
VDS (V) at TJ max.
550
RDS(on) max. () at 25 °C
VGS = 10 V
20
Qgs (nC)
3
Qgd (nC)
5
Configuration
- Fast Switching
• Material categorization: For definitions of compliance
please see www.freescale.net.cn
3.2
Qg (max.) (nC)
Single
D
APPLICATIONS
• Consumer Electronics
- Displays (LCD or Plasma TV)
• Server and Telecom Power Supplies
- SMPS
• Industrial
- Welding
- Induction Heating
- Motor Drives
• Battery Chargers
DPAK
(TO-252)
G
D
G
S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
Lead (Pb)-free
SiHD3N50D-E3
Lead (Pb)-free and Halogen-free
SiHD3N50D-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
LIMIT
VDS
500
VGS
Gate-Source Voltage AC (f > 1 Hz)
Continuous Drain Current (TJ = 150 °C)
SYMBOL
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
IDM
Linear Derating Factor
Single Pulse Avalanche
Energyb
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
TJ = 125 °C
Reverse Diode dV/dt (d)
Soldering Recommendations (Peak Temperature)c
for 10 s
UNIT
± 30
V
30
3.0
1.9
A
5.5
0.56
W/°C
EAS
9
mJ
PD
104
W
TJ, Tstg
- 55 to + 150
°C
dV/dt
24
0.22
300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 2.8 A.
c. 1.6 mm from case.
d. ISD  ID, starting TJ = 25 °C.
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V/ns
°C
SiHD3N50D
D Series Power MOSFET
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Maximum Junction-to-Case (Drain)
RthJC
-
1.8
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
VDS/TJ
Reference to 25 °C, ID = 250 μA
-
0.56
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3
-
5
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
Gate-Source Threshold Voltage (N)
Drain-Source On-State Resistance
Forward
Transconductancea
RDS(on)
VDS = 500 V, VGS = 0 V
-
-
1
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
10
-
2.6
3.2

S
VGS = 10 V
ID = 2.5 A
gfs
VDS = 8 V, ID = 1.5 A
-
1
-
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
175
-
-
21
-
-
5
-
-
21
-
-
26
-
μA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Effective Output Capacitance, Energy
Relatedb
Co(er)
Effective Output Capacitance, Time
Relatedc
Co(tr)
pF
VDS = 0 V to 400 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
-
6
12
-
2
-
Qgd
-
3
-
td(on)
-
12
24
tr
VDD = 400 V, ID = 1.5 A
Rg = 9.1 , VGS = 10 V
-
9
18
-
11
22
-
13
26
f = 1 MHz, open drain
-
3.3
-
-
-
3
-
-
12
-
-
1.2
-
293
-
ns
-
0.74
-
μC
-
5
-
A
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 1.5 A, VDS = 400 V
nC
ns

Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
P - N junction diode
D
A
G
TJ = 25 °C, IS = 1.5 A, VGS = 0 V
TJ = 25 °C, IF = IS = 1.5 A,
dI/dt = 100 A/μs, VR = 20 V
S
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
c. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
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V
SiHD3N50D
D Series Power MOSFET
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
5
4
TJ = 25 °C
ID = 1.5 A
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
6
3
8V
2
7V
1
2.5
2
1.5
VGS = 10 V
1
0.5
6V
0
0
5
10
15
20
25
0
- 60 - 40 - 20 0
30
Fig. 1 - Typical Output Characteristics
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
5.0 V
3
2
Fig. 4 - Normalized On-Resistance vs. Temperature
1000
Ciss
100
Coss
10
Crss
1
0
1
0
10
5
20
15
25
30
0
VDS, Drain-to-Source Voltage (V)
200
300
400
500
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
24
VGS, Gate-to-Source Voltage (V)
6
ID, Drain-to-Source Current (A)
100
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
5
4
3
2
TJ = 150 °C
1
TJ = 25 °C
VDS = 400 V
VDS = 250 V
VDS = 100 V
20
16
12
8
4
0
0
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
3/9
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
TJ = 150 °C
Capacitance (pF)
ID, Drain-to-Source Current (A)
4
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
25
0
3
6
9
12
Qg, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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SiHD3N50D
D Series Power MOSFET
3.0
ISD, Reverse Drain Current (A)
100
ID, Drain Current (A)
2.5
10
TJ = 150 °C
1
TJ = 25 °C
0.1
2.0
1.5
1.0
0.5
VGS = 0 V
0.01
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
25
1.6
VSD, Source-Drain Voltage (V)
75
100
125
Fig. 9 - Maximum Drain Current vs. Case Temperature
100
625
10
100 μs
1
1 ms
Limited by RDS(on)*
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
VDS, Drain-to-Source
Brakdown Voltage (V)
Operation in this area
limited by RDS(on)
600
575
550
525
500
BVDSS Limited
0.01
475
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Normalized Effective Transient
Thermal Impedance
Fig. 8 - Maximum Safe Operating Area
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 10 - Typical Drain-to-Source Voltage vs. Temperature
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
4/9
150
TJ, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
ID, Drain Current (A)
50
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SiHD3N50D
D Series Power MOSFET
RD
VDS
QG
10 V
VGS
D.U.T.
RG
QGS
+
- VDD
QGD
VG
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
+
10 %
VGS
D.U.T.
td(on)
td(off) tf
tr
-
VDS
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
Fig. 17 - Gate Charge Test Circuit
L
Vary tp to obtain
required IAS
VDS
D.U.T
RG
+
-
IAS
V DD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 15 - Unclamped Inductive Waveforms
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SiHD3N50D
D Series Power MOSFET
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel
6/9
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SiHD3N50D
D Series Power MOSFET
TO-252AA (HIGH VOLTAGE)
E
b3
E1
L3
D1
D
H
L4
b2
b
A
c2
e
A1
L1
L
c
θ
L2
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
E
6.40
6.73
0.252
0.265
L
1.40
1.77
0.055
L1
2.743 REF
L2
0.070
0.108 REF
0.508 BSC
0.020 BSC
L3
0.89
1.27
0.035
0.050
L4
0.64
1.01
0.025
0.040
D
6.00
6.22
0.236
0.245
H
9.40
10.40
0.370
0.409
b
0.64
0.88
0.025
0.035
b2
0.77
1.14
0.030
0.045
b3
5.21
5.46
0.205
e
2.286 BSC
0.215
0.090 BSC
A
2.20
2.38
0.087
A1
0.00
0.13
0.000
0.094
0.005
c
0.45
0.60
0.018
0.024
c2
0.45
0.58
0.018
0.023
D1
5.30
-
0.209
-
E1
4.40
-
0.173
-
θ
0'
10'
0'
10'
ECN: S-81965-Rev. A, 15-Sep-08
DWG: 5973
Notes
1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side.
2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
3. The package top may be smaller than the package bottom.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum
material condition. The dambar cannot be located on the lower radius of the foot.
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SiHD3N50D
D Series Power MOSFET
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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SiHD3N50D
D Series Power MOSFET
Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“freestyle”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
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Material Category Policy
freestyle Intertechnology, Inc. hereby certi fies that all its products that are id entified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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