SiHU3N50D Datasheet

SiHU3N50D
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Vishay Siliconix
D Series Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
• Optimal design
- Low area specific on-resistance
- Low input capacitance (Ciss)
- Reduced capacitive switching losses
- High body diode ruggedness
Available
- Avalanche energy rated (UIS)
• Optimal efficiency and operation
- Low cost
- Simple gate drive circuitry
- Low figure-of-merit (FOM): Ron x Qg
- Fast switching
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
550
RDS(on) max. () at 25 °C
VGS = 10 V
3.2
Qg max. (nC)
12
Qgs (nC)
2
Qgd (nC)
3
Configuration
Single
D
IPAK
(TO-251)
D
APPLICATIONS
G
G
D S
• Consumer electronics
-Displays (LCD or plasma TV)
• Server and telecom power supplies
- SMPS
• Industrial
- Welding
- Induction heating
- Motor drives
• Battery chargers
S
N-Channel MOSFET
ORDERING INFORMATION
Package
IPAK (TO-251)
Lead (Pb)-free
SiHU3N50D-E3
Lead (Pb)-free and Halogen-free
SiHU3N50D-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
LIMIT
VDS
500
VGS
Gate-Source Voltage AC (f > 1 Hz)
Continuous Drain Current (TJ = 150 °C)
SYMBOL
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
IDM
Linear Derating Factor
± 30
UNIT
V
30
3.0
1.9
A
5.5
0.56
W/°C
Single Pulse Avalanche Energy b
EAS
10.4
mJ
Maximum Power Dissipation
PD
69
W
TJ, Tstg
-55 to +150
°C
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
Reverse Diode dV/dt
TJ = 125 °C
d
Soldering Recommendations (Peak Temperature) c
for 10 s
dV/dt
24
0.22
300
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 3 A.
c. 1.6 mm from case.
d. ISD  ID, starting TJ = 25 °C.
S16-0110-Rev. C, 25-Jan-16
Document Number: 91493
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50D
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Maximum Junction-to-Case (Drain)
RthJC
-
1.8
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
VDS/TJ
Reference to 25 °C, ID = 250 μA
-
0.56
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3
-
5
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
1
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
10
-
2.6
3.2

S
Drain-Source On-State Resistance
Forward
Transconductance a
RDS(on)
VGS = 10 V
ID = 2.5 A
gfs
VDS = 8 V, ID = 1.5 A
-
1
-
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
175
-
-
21
-
-
5
-
-
21
-
-
26
-
μA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Effective Output Capacitance, Energy
Related b
Co(er)
Effective Output Capacitance, Time
Related c
Co(tr)
pF
VDS = 0 V to 400 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
-
6
12
-
2
-
Qgd
-
3
-
td(on)
-
12
24
tr
-
9
18
-
11
22
-
13
26
-
3.3
-
-
-
3
-
-
12
-
-
1.2
-
293
-
ns
-
0.74
-
μC
-
5
-
A
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 1.5 A, VDS = 400 V
VDD = 400 V, ID = 1.5 A
Rg = 9.1 , VGS = 10 V
f = 1 MHz, open drain
nC
ns

Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the 
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 1.5 A, VGS = 0 V
TJ = 25 °C, IF = IS = 1.5 A,
dI/dt = 100 A/μs, VR = 20 V
S
V
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
c. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
S16-0110-Rev. C, 25-Jan-16
Document Number: 91493
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50D
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
5
4
TJ = 25 °C
ID = 1.5 A
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
6
3
8V
2
7V
1
2.5
2
1.5
VGS = 10 V
1
0.5
6V
0
0
5
10
15
20
25
0
- 60 - 40 - 20 0
30
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
5.0 V
3
2
1000
Ciss
100
Coss
10
Crss
1
0
1
0
10
5
20
15
25
30
0
VDS, Drain-to-Source Voltage (V)
100
200
300
400
500
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
24
VGS, Gate-to-Source Voltage (V)
6
ID, Drain-to-Source Current (A)
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
TJ = 150 °C
Capacitance (pF)
ID, Drain-to-Source Current (A)
4
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
5
4
3
2
TJ = 150 °C
1
TJ = 25 °C
VDS = 400 V
VDS = 250 V
VDS = 100 V
20
16
12
8
4
0
0
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S16-0110-Rev. C, 25-Jan-16
25
0
3
6
9
12
Qg, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91493
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50D
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Vishay Siliconix
3.0
ISD, Reverse Drain Current (A)
100
ID, Drain Current (A)
2.5
10
TJ = 150 °C
1
TJ = 25 °C
0.1
2.0
1.5
1.0
0.5
VGS = 0 V
0.01
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
25
1.6
VSD, Source-Drain Voltage (V)
75
100
125
150
TJ, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
100
10
100 μs
1
1 ms
Limited by RDS(on)*
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
VDS, Drain-to-Source
Breakdown Voltage (V)
625
Operation in this area
limited by RDS(on)
ID, Drain Current (A)
50
600
575
550
525
500
BVDSS Limited
0.01
475
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Normalized Effective Transient
Thermal Impedance
Fig. 8 - Maximum Safe Operating Area
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 10 - Typical Drain-to-Source Voltage vs. Temperature
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
S16-0110-Rev. C, 25-Jan-16
Document Number: 91493
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50D
www.vishay.com
Vishay Siliconix
RD
VDS
QG
10 V
VGS
D.U.T.
RG
QGS
+
- VDD
QGD
VG
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
+
10 %
VGS
D.U.T.
td(on)
td(off) tf
tr
-
VDS
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
Fig. 17 - Gate Charge Test Circuit
L
Vary tp to obtain
required IAS
VDS
D.U.T
RG
+
-
IAS
V DD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 15 - Unclamped Inductive Waveforms
S16-0110-Rev. C, 25-Jan-16
Document Number: 91493
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50D
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel










Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91493.
S16-0110-Rev. C, 25-Jan-16
Document Number: 91493
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-251AA (HIGH VOLTAGE)
4
3
E1
E
Thermal PAD
4
b4
θ2
4
A
0.010 0.25 M C A B
L2 4
c2
A
θ1
B
D
D1
A
C
3
Seating
plane
5
C
L1 L3
(Datum A)
C
L
B
B
A
A1
3 x b2
View A - A
2xe
c
3xb
0.010 0.25 M C A B
Plating
5
b1, b3
Base
metal
Lead tip
c1
(c)
5
(b, b2)
Section B - B and C - C
MILLIMETERS
DIM.
MIN.
MAX.
INCHES
MIN.
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
2.18
2.39
0.086
0.094
D1
5.21
-
0.205
-
A1
0.89
1.14
0.035
0.045
E
6.35
6.73
0.250
0.265
4.32
-
0.170
-
b
0.64
0.89
0.025
0.035
E1
b1
0.65
0.79
0.026
0.031
e
b2
0.76
1.14
0.030
0.045
L
8.89
9.65
0.350
0.380
b3
0.76
1.04
0.030
0.041
L1
1.91
2.29
0.075
0.090
b4
4.95
5.46
0.195
0.215
L2
0.89
1.27
0.035
0.050
2.29 BSC
2.29 BSC
c
0.46
0.61
0.018
0.024
L3
1.14
1.52
0.045
0.060
c1
0.41
0.56
0.016
0.022
θ1
0'
15'
0'
15'
c2
0.46
0.86
0.018
0.034
θ2
25'
35'
25'
35'
D
5.97
6.22
0.235
0.245
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
Document Number: 91362
Revision: 15-Sep-08
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12
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Document Number: 91000